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Circuit Operation Description
5. Circuit Description
5-1 Power supply
5-1-1 Outline(PDP SMPS)
Considering various related conditions, the switching regulator with good efficiency and allowing for its small size and lightweight was used as the power supply for PDP. Most of the power supply components used forward converter, and Vsamp and Vsb used simple flyback converter. To comply with the international harmonics standards and improve the power factor, active PFC (Power Factor Correction) was used to rectify AC input into +400V DC output, which in turns used as input to the switching regulator.
5-1-2 42"SD SMPS SPECIFICATION
5-1-2(A) INPUT
PDP-42PS board is designed so that input power can be used within AC 90 VAC to 264 VAC with 50/60Hz ± 3Hz.
5-1-2(B) OUTPUT
PDP-42PS board provides 13 output switching power supplies for PDP 50inch (+165Vs, +220Set, +185Ve, +75Va, +80Scan, +18Vg, +5Vsb, +5V(D), +5V(A), +12V. +9V, +12Vfan, and +12Vsamp). The output voltage, and current requirements for continuous operation are stated below (Table 3). Table1. Specifications of Output Power Supplies for PDP SMPS Output Name Vs Va Vscan Vset Ve Vg Vfan V9 V5(A) V5(D) Vsb V12 Vsamp Output Voltage +165V +75V +80V +220V +185V +18.3V +12V +9V +5V +5.3V +5V +12V +12V Output Current 1.4A 0.5A 0.05A 0.05A 0.05A 0.3A 0.8A 0.3A 1.0A 3.5A 0.4 1.2A 1.5A Analog IC Drive Voltage of Video Board IC Drive Voltage of Logic Board Stand-by for Remote Control Using in PDP driving Sustain Voltage of Drive Board Address Voltage of Drive Board
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Circuit Operation Description
Table 2. Specifications to Protect PDP SMPS Division Vs Va +5V OCP Current 5A 2A 10A OVP Voltage 195V 90V 6.2V Short Circuit O.K O.K O.K
5-1-2(C) FUNCTION OF BOARD
(1) Remote control Using 250V/ 10A relay, the board makes remote control available. (2) Free voltage The board designed so that input voltage can be used within 90 VAC to 264VAC. (3) Embedded thermal sensor The board is equipped with thermal sensor to detect the internal temperature of the unit, and to short relay when the internal temperature is higher than specified temperature so as to shutdown the unit. (4) Improvement of power factor The board is designed using PFC circuit so that PF (Power Factor) can be over 0.95, because low PF can be a problem in high voltage power. (5) Protection The OCP (Over Current Protection), the OVP (Over voltage Protection), and the Short Circuit Protection functions are added against system malfunction.
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Circuit Operation Description
5-1-2(D) PDP-PS-42 BLOCK DIAGRAM
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Circuit Operation Description
(1) AC-DC Converter PDP-42PS outputs +400V DC from the common AC power supply using the active PFC booster converter. This converter is designed for improving the power factor and preventing the noise with high frequency and finally becomes the input power system for the switching regulator on the output side. (2) Auxiliary Power Supply The auxiliary power supply is a block generating power of ·Ï-com for remote controlling. Once the power plug is inserted, this block always comes into operation, causing ·Ï-com to get into the standby state for the output. Thus, this output is called the stand-by voltage. And with the relay ON signal inputted through the remote controller, this block turns the mechanical switch of relay to ON for driving the main power supply. (3) Implementation of Sustain Voltage As the main part of a SMPS for PDP, sustain voltage must supply a high power, +165V/ 1.4A. It is designed using forward converter basically. At the output stage two 90V converters are connected serially for high efficiency and reduction of system size against a single 180V converter. (4) Implementation of Small Power Output (Va, V(D), V(A), Vfan, V9, Vsamp, Ve, Vset, Vscan, V12, and Vg)Vset, Ve, and Vscan used DC-DC module. V(D), Va, V12, and Vfan used forward converter, and Vsamp used flyback converter. V(A), V9, and Vg are simply implemented using switching regulator.
5-1-3 Requirements of PDP SMPS
Since SMPS does not operate alone, but it operates with the load of the whole system, it should be designed carefully considering the load of the system. In addition, it should be designed considering emerging issues such as EMC, and protection against heat as well as system stability especially.
5-1-3(A) SAFETY AND REMOTE CONTROL CAPABILITY
Stability is one of the most important requirements for SMPS. SMPS should be designed to prevent abnormal status due to abnormal load variation so as to keep the system stable, and guarantee customer safety. The protection circuits of SMPS include over-current protection (OCP), over voltage protection (OVP), and under voltage lock-out (UVLO), and short circuit protection circuit. Although each circuit can be implemented by various procedures, the most popular is implementing with comparator that compares current value with that of standard and determine abnormality of the circuit. In addition, surge current protection, insulation management, and static electricity protection circuit should be added, because it uses commercial power source as an input. PDP SMPS should be designed using auxiliary power and relay to provide remote control capability.
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Circuit Operation Description
5-1-3(B) THE RELATION BETWEEN POWER CONSUMPTION AND POWER CONVERSION Efficiency
The power consumption and the power conversion efficiency of SMPS affect protection against heat and system operation much. [ If the power conversion efficiency of 100W SMPS is 70%, is the power loss of internal circuit 30W? ] Output power consumption Po is determined by the multiplication of DC output voltage Vo and output current Io. Input power consumption Pi is determined by the addition of output power consumption Po and internal power loss of SMPS Pl. Provided that the power conversion efficiency is _,
If the power conversion efficiency of 100W SMPS is 70%, the internal power loss is about 42.8W by Equation (1). If the power conversion efficiency of 400W SMPS for 42"SD is 82%, the internal power loss is 87.8W by Equation (1). Table 4 shows internal power loss as a function of output power for various power conversion efficiencies.
200 180 160 140
=50% = 60% =70%
Internal 120 Power 100 Loss ( W)
80 60 40 20 0 120 140 160 180 200 220 240
= 80% = 90%
260
280
300
Direct Current Output Power (W)
Table 4. Power Conversion Efficiency vs. Internal Power Loss
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Circuit Operation Description
5-1-3(C) PFC (Power Factor Correction) Circuit Descriptions
The current electric devices use DC power supply and require a rectifier circuit converting AC into DC. As most rectifier circuits apply a capacitor input type, the rectifier circuit becomes the core of the occurrence of harmonics with lower reverse rate.If various electronic and electric devices are connected to a power system, high-frequency current will occur due to a power rectifier circuit, a phase control circuit with power input current of non-sine wave, or components with non-linear load characteristics, such as capacitor, inductor, etc. As the result, the disturbance of voltage occurs, and finally a power capacitor or a transformer generates heat, fire or noise occurs, controls malfunction, or the accessed devices abnormally operate or their lives are shortened.To prevent those symptoms, IEC (International Electrotechnical Commission) regulated standards for Power Supply Harmonics. (Refer to IEC 1000-3-2.)Figure 8 shows the basic structure of Active Boost PFC and waveforms.
Standards for Power Supply Harmonics
Scale: Devices accessed to 220V/380V, 230V/400V, 240V/425V and lower than 16A (IEC 100-3-2) Devices with AC 230V and lower than 16A (IEC 555-2) Applied Classes : p Class A : Devices not included in another class p Class B : Portable tools p Class C : Lighting devices p Class D : Devices with special current waveforms Application Schedule : Except the devices less than rating input of 75W (1996~1999) Except the devices less than rating input of 50W (2000 and after)
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Circuit Operation Description
The architecture and the pulse of active boost PFC
5-1-3(D) CONCLUSION
Although SMPS (Switching Mode Power Supply) enables small lightweight high-power consumption power design, it is hard to be used when stability and precise control are required. Power stage for PDP can be designed using the lightweight SMPS feature. It is important to design SMPS considering system load, stability, and related international standards.
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Circuit Operation Description
5-2 Driver Circuit
5-2-1 Driver Circuit Overview
5-2-1(A) WHAT IS THE DEFINITION OF DRIVE CIRCUIT?
It is a circuit generating an appropriate pulse (High voltage pulse) and then driving the panel to implement images in the external terminals (X electrode group, Y electrode group and address electrode), and this high voltage switching pulse is generated by a combination of MOSFET's.
5-2-1(B) PANEL DRIVING PRINCIPLES
In PDP, images are implemented by impressing voltage on the X electrode, Y electrode and address electrode, components of each pixel on the panel, under appropriate conditions. Currently, ADS (Address & Display Separate: Driving is made by separating address and sustaining sections) is most widely used to generate the drive pulse. Discharges conducted within PDP pixels using this method can largely be classified into 3 types, as follows: (1) Address discharge : This functions to generate wall voltage within pixels to be lighted by addressing information to them (i.e., impressing data voltage) (2) Sustain discharge : This means a display section where only pixels with wall voltage by the address discharge display self-sustaining discharge by the support of such wall voltage. (Optic outputs realizing images are generated.) (3) Erase discharge : To have address discharge occur selectively in pixels, all pixels in the panel must have the same conditions (i.e., the same state of wall and space electric discharges). The ramp reset discharge section, therefore, is important to secure the drive margin, and methods most widely used to date include wall voltage controlling by ramp pulse.
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Circuit Operation Description
5-2-1(C) TYPES AND DETAILED EXPLANATION OF DRIVE DISCHARGES
(1 ) Sustaining discharge Sustaining discharge means a self-sustaining discharge generated by the total of the sustaining pulse voltage (usually, 160~170V) alternately given to X and Y electrodes during the sustaining period and the wall voltage that varies depending upon pixels' previous discharge status. It is operated by the memory function (through this, the current status is defined by previous operation conditions) AC PDP basically possesses. That is, when there is existing wall voltage in pixels (in other words, when pixels remain ON), the total of wall voltage and a sustaining voltage to be impressed subsequently impresses a voltage equal to or above the discharge start voltage, thereby generating discharge again, but when there is no existing wall voltage in pixels (in other words, when pixels remain OFF), the sustaining voltage only does not reach the discharge start voltage, thus causing no discharge. The sustaining discharge is a section generating actual optic outputs used in displaying images.
(2) Address discharge This means a discharge type generated by the difference between positive voltage of the address electrode (normally 70~75V determined by supplied Va voltage + positive wall charge) and the negative potential of Y electrode (supplied GND level voltage + negative wall charge). The address discharge serves to generate wall voltage in pixels where images are to be displayed (that is, discharge is to be generated) prior to the sustaining discharge section. Namely, pixels with wall voltage by the address discharge will generate sustaining discharge by the following sustaining pulses.
(3) Erase discharge The purpose of resetting or erase discharge is to make even wall voltage in all pixels on the panel. Wall voltage, which may vary depending upon the previous sustaining discharge status, must be made even. That is, wall voltage generated by the sustaining discharge must surely be removed, by making discharges and then supplying ions or electrons. Wall voltage can be removed by making discharges and then setting a limitation on time for opposite polarity charging of the wall voltage or generating weak discharge (Low voltage erasing) to supply an appropriate quantity of ions or electrons and keep polarities from being charged oppositely. The weak discharge (Low voltage erasing) methods, which have been known to date, can largely be into two types: 1) the log pulse adopted by most companies including F Company, and 2) the ramp pulse adopted by Matsushita. In both two methods, impression is made with a slow rising slope of the erasing pulse. Because the total of the existing wall voltage and a voltage on the rising pulse must be at least the drive start voltage to generate discharges, external impressed voltage is adjusted based on the difference in wall voltage between pixels. And, weak discharge is generated because of a small impressed voltage.
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Circuit Operation Description
5-2-2 SPECIFICATION OF DRIVE PULSES
5-2-2(A) DRIVE PULSES
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5-2-2(B) FUNCTIONS OF PULSES
(1) X rising ramp pulse Just before X rising ramp pulse is impressed, the last Y electrode sustain pulse of previous sub field is impressed. The pulse causes sustain discharge. Consequently, positive wall charge is accumulated in X electrode, and negative wall charge is accumulated in Y electrode. X rising ramp erases wall charge produced by the last sustain discharge pulse using weak-discharge. (2) Y rising ramp pulse During Y rising ramp period, weak-discharge begins when external voltage of about 390V~400V is impressed to Y electrode, and each gap voltage is equal to discharge start voltage. Sustaining the weak-discharge, positive wall charge is accumulated in X electrode and address electrode, and negative wall charge is accumulated in Y electrode of the entire panel. (3) Y falling ramp pulse During Y falling ramp period, the negative wall charge in Y electrode accumulated by 200V of X bias is used to erase positive wall charge in X electrode. Address electrode (0V) sustains most of the positive electric charge accumulated during rising ramp period so that it can maintain wall charge distribution beneficial to the upcoming address discharge. (4) Y scan pulse This is called the scan pulse, selecting each of Y electrodes on a one-line-at-a-time basis. In this case, Vscan means the scan bias voltage. About 70 V (Vscan) voltage is impressed on the selected electrode lines, while 0 V (GND) voltage is impressed on the other lines. In the cells the address pulse (70V~75V) is impressed on, address discharge is occurred because negative wall charge is accumulated in Y electrode, positive wall charge is accumulated in address electrode by the applied ramp pulse, and the sum of impressed voltage is greater than discharge start voltage. Thus, because scan pulse and data pulse are impressed line by line, very long time is taken for PDP addressing. (5) 1st sustain pulse The sustaining pulse always begins with the Y electrode. This is because when address discharge is generated, positive wall voltage is generated on the Y electrodes. Because wall electric charge generated by address discharge is generally smaller than wall voltage generated by sustaining discharge, initial discharges have small discharge strength, and stabilization is usually obtained after 5~6 times discharges, subject to variations depending on the structure and environment of electrodes. The purpose of impressing the initial sustaining pulses long is to obtain stable initial discharges and generate wall electric charges as much as possible.
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Circuit Operation Description
5-2-3 Configuration and Operation Principles of Driver Circuit
5-2-3(A) FUNCTIONS OF EACH BOARD
Y-Buffer (Upper)
Y Drive board
- Sustain pulse (Energy recovery) - Rising ramp pulse - Falling ramp pulse - Vscan pulse
X Drive board
- Sustain pulse (Energy recovery) - Rising ramp pulse - Ve bias
Y-Buffer (Lower)
Y-electrode blocks (6 blocks)
COF
X-electrode blocks (3 blocks)
(1) X board X board is connected to the panel's X-electrode blocks, 1) generates sustain voltage pulse (including ERC), 2) generates X rising ramp pulse, and 3) sustains Ve bias during scan period. (2) Y board Y board is connected to the Y-electrode blocks of panel, 1) generates sustain voltage pulse (including ERC), 2) generates Y rising and falling ramp pulse, and 3) sustains Vscan bias. (3) Y buffer board (upper and lower) Y buffer board impresses scan pulse to Y electrodes, and consists of upper and lower sub-boards. In case of SD class, one board is equipped with 4 scan driver IC's (STMicroelectronics STV7617 with 64 or 65 outputs). (4) COF Impresses Va pulse on address electrodes in the address section and generates address discharge based on a difference between such Va pulse and scan pulse impressed on Y electrodes. It is in the form of COF, and a COF is equipped with 4 data drive IC's (STMicroelectronics STV7610A with 96 outputs). For a single scan, 7 COF's are required.
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Circuit Operation Description
5-2-3(B) DRIVING BOARD'S BLOCK DIAGRAM (1) Y
POWER
220V 75V
17V
170V
(2) X
POWER
220V
17V
170V
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Circuit Operation Description
Components of driving board's operations
1. Power supply 1) Supplied from the power supply board - For sustaining discharge: 180V; - For logic signaling buffer: 5V; and - For gate driver IC: 15V. 2) Generated by the internal DC/DC part - For generating Vw pulse: 180V. 2. Logic signal 1) Supplied from the logic board - Gate signals for FETs.
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Circuit Operation Description
5-2-3(C) PRINCIPLES OF FET'S OPERATION AND HIGH VOLTAGE SWITCHIng
FET's operation principles (1) With signal impressed on the gate (Positive voltage), FET gets short-circuited (a conducting wire of zero (0) resistance); and (2) With no signal impressed on the gate (GND), FET gets open-circuited (a non-conducting wire of resistance).
FET's high voltage switching principles (1) With no signal impressed on G1, FET1 gets open-circuited, and with signal impressed on G2, FET2 gets short-circuited, thereby causing GND to be outputted to output terminals. (2) With signal impressed on G1, FET1 gets shortcircuited, and with no signal impressed on G2, FET2 gets open-circuited, thereby causing 180V to be outputted to output terminals.
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Circuit Operation Description
5-2-3 (D) DRIVER CIRCUIT DIAGRAM
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Circuit Operation Description
5-2-3(E) DRIVER BOARD CONNECTOR LAYOUT
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Circuit Operation Description
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Circuit Operation Description
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Circuit Operation Description
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Circuit Operation Description
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Circuit Operation Description
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Circuit Operation Description
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Circuit Operation Description
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Circuit Operation Description
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Circuit Operation Description
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Circuit Operation Description
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Circuit Operation Description
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Circuit Operation Description
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Circuit Operation Description
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Circuit Operation Description
5-3 Logic part
5-3-1 Logic Board Block diagram
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Circuit Operation Description
5-3-1(A) TDESCRIPTION OF LOGIC BOARD
The logic board consists of the logic main board and the buffer board. The logic main board processes video signal, generates, and output address driver output signal as well as XY drive signal. The buffer board stores address driver output signal, and sends the signal to the address driver IC (COF module). Logic Board Function - Video signal processing (W/L, Error diffusion, APC) - Outputs address drive control signal, and data signal to buffer board. - Outputs XY drive board control signal. Sends data and control signal to left-bottom COF Sends data and control signal to right-bottom COF
Login Main
Buffer board
E Buffer board F Buffer board
5-3-1 (B) NAME AND DESCRIPTION OF MAJOR COMPONENTS OF LOGIC BOARD
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Circuit Operation Description
No 1 2 3 4 5 6 7 8 9 10
Name LVDS Connector Operation LED Key-Scan Connector 256k Y Connector X Connector
Function Input connector to receive encoded RGB, H, V, DATAEN, and DCLK signal. It shows Sync and clock are properly received by the logic board. Connector to connect key scan board to check and adjust 256K data. EEPROM including gamma table, APC table, drive signal timing and other options Connector to output Y drive board control signal Connector to output X drive board control signal
LE01 (Address Buffer Connector) Connector to output address data, and control signal to the E and F buffer boards. LE02 (Address Buffer Connector) Connector to output address data, and control signal to the E and F buffer boards. Power Fuse Power Connector Fuse connected to the power source line of the logic board. Connector to connect the supply power (5V) with the logic board. drive board control signal.
5-3-1(C) WAVEFORMS IN NORMAL OPERATION
If the PDP unit and the logic board is in normal operation, the operation LED of Figure 1 would blink at about 1 second interval. If the unit is out of order, check the status of the operation LED through eye-inspection first. If the behavior of the operation LED is different from that of normal state, you have to replace the board. To check trouble on the board, the following logic board test procedures described below. 42°" SD s1.0 logic main board T/S Required test equipment: : - Oscilloscope (digital 400 MHz 3 channel or more) - Multi meter - DC power supply (5V: 1EA ) - Sub-PCB ASS'Y for JIG: 1 EA
Other equipment: :
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Circuit Operation Description
(1) First, perform eye-inspection and short circuit inspection for the power stage of the logic board to examine. Then, perform the following examinations on the board in order if no problem was found. (2) Replace IC2017(256K EEPROM) of the logic board with Test EERPOM. Change the clock setting of the logic board to internal referring to the configuration procedures described below. If there is no available Test EEPROM, you can use PG 00 for Windows NT systems, or PG 40 for NT/PAL compatible systems by setting address 20 to 81, 22 to 00, 23 to 00,and 70 to 01. (3) Connect power(5V) to LD1, and check that LED(LD2000) on the left top of the board blinks at about 1 second interval. (4) If the logic board is out of order, the LED would blink too fast or not be lighted on. (5) If no problem was found in the above examination, connect sub-PCB for logic output examination, measure output waveform, and compare the waveform with the appended waveform of normal state. Record either OK or NG after examination. (6) Check drive Y s/w, drive X s/w and address signal in order. (7) Set probe 1 of oscilloscope to trigger signal, and connect it to the TP31 of the logic board. (8) Set oscilloscope to 2ms/div. After adjusting probe 2 to 5V/div, check output signal. (9) After T/S, turn off the power supply, and disconnect connector. (10) Record the result on the examination sheet (either OK or NG). Jumper settings to select internal or external clock On the top of the logic main board, there is option jumper (CN01) that allows selecting internal/external clock. While T/S, set it to internal clock as the following figure shows. It is set to external clock in normal. Set it to internal clock while examination, and set it to external clock again after examination.
Figure 1. Jumper Settings to Select Internal / External Clock Signal
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Circuit Operation Description
160mm LA03 31 1 CN01 LD1
LD2000
IC1 IC2
256k
F1 D1 F2
Samsung Electronics
320mm M1 E1 M2 L Y 1 LX1 LE01
D2
IC3
TP31 GND7
LE02
Figure 2. Layout of 42" Signal Logic Main Board.
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Circuit Operation Description
(1) Checking Y S /W
Figure 3. Connecting The Logic Main Board and The Test JIG Board
Figure 4. Connecting Oscilloscope Probe 1 (Trigger)
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Circuit Operation Description
! Connect Probe 2 to LY1 30 of The JIG Board (8 (LE-Y) of The Logic Main Board F2016).
@ Connect Probe 2 to LY1 28 of The JIG Board (7 (STB_Y) of The Logic Main Board F2016).
# Connect Probe 2 to LY1 25 of The JIG Board (6 (TCS_Y) of The Logic Main Board F2016). Samsung Electronics 5-37
Circuit Operation Description
$ Connect Probe 2 to LY1 24 of The JIG Board (5 (CLK_Y) of The Logic Main Board F2016).
% Connect Probe 2 to LY1 21 of The JIG Board (8 (SIB) of The Logic Main Board F2016).
^ Connect Probe 2 to LY1 20 of The JIG Board (7 (SIA) of The Logic Main Board F2016). 5-38 Samsung Electronics
Circuit Operation Description
& Connect Probe 2 to LY1 14 of The JIG Board (5 (YSP) of The Logic Main Board F2016).
* Connect Probe 2 to LY1 13 of The JIG Board (6 (YSC) of The Logic Main Board F2016).
( Connect Probe 2 to LY1 10 of The JIG Board (7 (YER) of The Logic Main Board F2016). Samsung Electronics 5-39
Circuit Operation Description
) Connect Probe 2 to LY1 9 of The JIG Board (8 (YP) of The Logic Main Board F2016).
1 Connect Probe 2 to LY1 8 of The JIG Board (6 (YRR) of The Logic Main Board F2016).
2 Connect Probe 2 to LY1 5 of The JIG Board (5 (YG) of The Logic Main Board F2016). 5-40 Samsung Electronics
Circuit Operation Description
3 Connect Probe 2 to LY1 4 of The JIG Board (8 (YF) of The Logic Main Board F2016).
4 Connect Probe 2 to LY1 2 of The JIG Board (6 (YR) of The Logic Main Board F2016).
5 Connect Probe 2 to LY1 1 of The JIG Board (5 (YS) of The Logic Main Board F2016). Samsung Electronics 5-41
Circuit Operation Description
6 Connect Probe 2 to 1 and 72 of IC2005, and Check The Following Waveform Shows at Oscilloscope.
7 Connect Probe 2 to 1 and 72 of IC2006, and Check The Following Waveform Shows at Oscilloscope.
8 Connect Probe 2 to 1 and 81 of IC2007, and Check The Following Waveform Shows at Oscilloscope. 5-42 Samsung Electronics
Circuit Operation Description
9 Connect Probe 2 to 1 and 81 of IC2008, and Check The Following Waveform Shows at Oscilloscope.
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Circuit Operation Description
(1) Checking X S /W
! Connect Probe 2 to LX1 2 of The JIG Board (6 (XRR) of The Logic Main Board F2016).
@ Connect Probe 2 to LX1 4 of The JIG Board (7 (XR) of The Logic Main Board F2016).
# Connect Probe 2 to LX1 6 of The JIG Board (8 (XS) of The Logic Main Board F2016). 5-44 Samsung Electronics
Circuit Operation Description
$ Connect Probe 2 to LX1 8 of The JIG Board (5 (XF) of The Logic Main Board F2016).
% Connect Probe 2 to LX1 10 of The JIG Board (6 (XG) of The Logic Main Board F2016).
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Circuit Operation Description
I 42°"SD logic buffer board T/S Required test equipment : Other equipment : -.Oscilloscope (digital 400 MHz 2 channel or more) -.DC power supply (5V : 1EA ) -.Multi meter -.Logic board : 1EA -.Sub-PCB ASS'Y for JIG: 1 EA
(1) First, perform eye-inspection and short circuit inspection for the power stage of the logic board to examine. Then, perform the following examinations on the board in order if no problem was found. (2) If no problem was found in step ®ÿ, connect buffer board as Figure 5 shows, connect sub-PCB for COF data check and replace 256K EEPROM with Test EERPOM for the logic board to output fullwhite pattern. (3) Supply 5V to the logic board, and check that the LED on the left-top of the board blinks at about 1 second interval. If no problem is found, measure the output waveform of sub-PCB, and compare it with that of normal state. (4) Check EC1, EC2, EC3, EC4, FC5, FC6, and FC7 in order. You can only examine doubtable waveform selectively. (5) Set probe 1 of oscilloscope to trigger signal, and connect it to the TP31 of the logic board. (6) Set oscilloscope to 2ms/div. After adjusting probe 2 to 5V/div, check output signal zooming important points. (7) Appended waveform is for full-white input pattern. Output waveform when each of R, G and B pattern is supplied individually is summarized in the following table. For short check, it would be better to test waveform in the order of R, G and B pattern. Output waveform for the applied pattern Full-white Control signal output of sub-PCB for COF data check The output waveforms of all of the R, G, B TP's are the same as the attached waveform. R G B
The same as the attached waveform The output waveforms of all of the R0, R1 TP's are the same as the attached waveform. The output waveforms of all of the G0, G1 TP's are the same as the attached waveform. The output waveforms of all of the B0, B1 TP's are the same as the attached waveform.
R, B, G data signal output of sub-PCB for COF data check
R0(TP13,TP49), R1(TP16,TP52), G0(TP14,TP50), G1(TP17,TP53), B0(TP15,TP51), and B1(TP18,TP54) in The JIG Board (8) After T/S, turn off the power supply, and disconnect the connector. Record the result on the examination sheet.
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Circuit Operation Description
Figure 5. 42" Single logic buffer Samsung Electronics 5-47
Circuit Operation Description
(3) Checking buffer data
! TP 13 ~ 18, 49 ~ 54 of The Test JIG Board
@ 21, 57 of The Test JIG Board
# 24, 31, 60, 67 of The Test JIG Board 5-48 Samsung Electronics
Circuit Operation Description
$ TP 25, 32, 61, 68 of The Test JIG Board
% TP 19, 26, 55, 62 of The Test JIG Board
^ TP 20, 27, 56, 63 of The Test JIG Board Samsung Electronics 5-49
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I 2C
Vi deo
CVBS
MAI N
I 2C
EEPROM 24C16
I 2C( 1) I 2C DCKEXT M CKEXT IR Key L ED
DI S. OSC. ( 26Mhz ) ( 130Mhz ) Key Mat r i x
Output CL K
I R , L ED
( CVBS)
Circuit Operation Description
Y [7: 0] UV [7: ] H1_OUT V1_OUT CL K2 L L C1
Pr ogr es s i v e SDA9400 DAC
I VVS I VHS V_Y/ G V_Pr / R V_Pb/ B CL K2
5-4 Block Diagram
S-Vi deo
MA IN_Y
CVBS, Y
YI N [ 7: 0] UVI N [ 7: 0]
Video
( Y/ C)
MA IN_C
Dec oder SDA9280 Image Sc al i ng OSD Mi x er F rame Rat e Conv ers i on Wi t h CPU V PW364 Sandc as t l e Pul s e M4A3( CPL D)
S1_DET
YPr Pb(DVD)
VPC3230
Com ponent Input RCA YPr Pb( DTV)
RGB Mat r i x CXA2101AQ
SCP
H, V
5-4-1 42" Monitor Scaler Block Diagram
DVD VPC3230 ( 480i ) DTV
PI P
VS_OUT1
RE[ 7: 0] GE[ 7: 0] BE[ 7: 0] PROTECT L VS L HS L ENG DCL K
Sc art
CVBS R, G, B, F B
Video Dec oder VPC3230 FI FO
RCA OPTI ON
I 2C
Y DVD
Y DTV
R, G, B_OUT, HS_OUT1
#8 I D
ADC Wi t h PL L AD9884
VG[ 7: 0] VR[ 7: 0] VB[ 7: 0] VHS VCL K
PCF 8591
MHSYNC, MCOAST CKI NV, CL AMP SR[ 23: 0] , SQ [23: 0] MHS, PCL K , SOG
ADC
PC_R. G. B.
BA7657 SW
CHSYNC CVSYNC
SCART OPTI ON
PC I nput
( 15pi n D- SUB)
PC_R, PC_G, PC_B, PC_H, PC_V
PC_H, PC_V
ADC Wi t h PL L AD9884
G
Sub PCB for Audio Ser i al MAX232A
RS232C ( 9pi n,MAL E)
TXD/ RXD
RS- 232
( Audio Amp. TA1101 )
I 2C
I 2C
Audi o I n
SRAM KM616V1000
RTC PCF 8563
Samsung Electronics
3( L / R)
(
Audio Pr oc es s or TDA7429S
)
F l as h Mem ory 29L V160
Circuit Operation Description
5-5 Major In/Out Signal Waveforms and Voltages of the Unit
5-5-1 In/Out Waveforms
Y output waveform - It is the waveform when it is not connected to the panel. * You should check that a single scan waveform is outputted!!!
Y output waveform (200us/div, 100V/div) * You should check that energy recovery software is in operation!!!
Samsung Electronics
5-51
Circuit Operation Description
X output waveform - It is the waveform when it is not connected to the panel.
X output waveform (200us/div, 100V/div) * You should check that energy recovery software is in operation!!!
5-52
Samsung Electronics
Circuit Operation Description
5-6 Main I/O signal pules and voltages
5-6-1 Signal Pulses of Image Board(Input Signal Conditions : 7 Color bar)
Samsung Electronics
5-53
Circuit Operation Description
5-54
Samsung Electronics
Circuit Operation Description
Samsung Electronics
5-55
MEMO
5-56
Samsung Electronics
Circuit Operation Description
Samsung Electronics
5-57