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INTEGRATED CIRCUITS

DATA SHEET
For a complete data sheet, please also download:
· The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC · The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC

HEF4000B gates Dual 3-input NOR gate and inverter
Product specification File under Integrated Circuits, IC04 January 1995

Philips Semiconductors

Product specification

Dual 3-input NOR gate and inverter
DESCRIPTION The HEF4000B provides the positive dual 3-input NOR function. A single stage inverting function with standard output performance is also accomplished. The outputs are fully buffered for highest noise immunity and pattern insensitivity of output impedance.

HEF4000B gates

Fig.2 Pinning diagram.

HEF4000BP(N): HEF4000BD(F): HEF4000BT(D):

14-lead DIL; plastic (SOT27-1) 14-lead DIL; ceramic (cerdip) (SOT73) 14-lead SO; plastic (SOT108-1)

Fig.1 Functional diagram.

( ): Package Designator North America

FAMILY DATA, IDD LIMITS category GATES See Family Specifications

Fig.3 Logic diagram.

January 1995

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Philips Semiconductors

Product specification

Dual 3-input NOR gate and inverter
DC CHARACTERISTICS For the single inverter stage (I7/O3): see Family Specifications for input voltages HIGH and LOW (unbuffered stages only). AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times 20 ns VDD V Propagation delays I1 to I6 O1,O2 5 10 15 5 I7 O3 (unbuffered output) Output transition times HIGH to LOW 10 15 5 10 15 5 LOW to HIGH 10 15 tTLH tTHL tPHL; tPLH tPHL; tPLH SYMBOL TYP. 70 35 30 45 25 20 60 30 20 60 30 20 MAX. 140 70 55 90 50 40 120 60 40 120 60 40 ns ns ns ns ns ns ns ns ns ns ns ns

HEF4000B gates

TYPICAL EXTRAPOLATION FORMULA 43 ns + (0,55 ns/pF) CL 24 ns + (0,23 ns/pF) CL 22 ns + (0,16 ns/pF) CL 18 ns + (0,55 ns/pF) CL 14 ns + (0,23 ns/pF) CL 12 ns + (0,16 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL

VDD V Dynamic power dissipation per package (P) 5 10 15

TYPICAL FORMULA FOR P (µW) 1 000 fi + (foCL) × VDD2 7 700 fi + (foCL) × VDD 28 700 fi + (foCL) × VDD
2 2

where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) (foCL) = sum of outputs VDD = supply voltage (V)

January 1995

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Philips Semiconductors

Product specification

Dual 3-input NOR gate and inverter
APPLICATION INFORMATION The following information (Figs 4 to 7) is only for the single inverter stage (I7/O3).

HEF4000B gates

Fig.4

Voltage gain (VO/VI) as a function of supply voltage.

Fig.5

Supply current as a function of supply voltage.

This is also an example of an analogue amplifier using the single inverter stage (I7/O3) of the HEF4000B.

Fig.6

Test set-up for measuring graphs of Figs 4 and 5.

January 1995

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Philips Semiconductors

Product specification

Dual 3-input NOR gate and inverter

HEF4000B gates

Fig.7 Test set-up for measuring forward transconductance gfs = dio/dvi at vo is constant (see also graph Fig.8).

A: average B: average + 2 s, C: average - 2 s, in where `s' is the observed standard deviation.

Fig.8 Typical forward transconductance gfs as a function of the supply voltage at Tamb = 25 °C.

January 1995

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