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D Flip-Flops with Preset Clear and Complementary Outputs
54LS74 DM54LS74A DM74LS74A Dual Positive-Edge-Triggered
June 1989
54LS74 DM54LS74A DM74LS74A
Dual Positive-Edge-Triggered D Flip-Flops
with Preset Clear and Complementary Outputs
General Description
This device contains two independent positive-edge-trig- violated A low logic level on the preset or clear inputs will
gered D flip-flops with complementary outputs The informa- set or reset the outputs regardless of the logic levels of the
tion on the D input is accepted by the flip-flops on the posi- other inputs
tive going edge of the clock pulse The triggering occurs at a
voltage level and is not directly related to the transition time Features
of the rising edge of the clock The data on the D input may Y Alternate military aerospace device (54LS74) is avail-
be changed while the clock is low or high without affecting able Contact a National Semiconductor Sales Office
the outputs as long as the data setup and hold times are not Distributor for specifications
Connection Diagram
Dual-In-Line Package
TL F 6373