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CD40109BMS
December 1992

CMOS Quad Low-to-High Voltage Level Shifter
Description
CD40109BMS contains four low-to-high voltage level shifting circuits. Each circuit will shift a low voltage digital logic input signal (A, B, C, D) with logical 1 = VCC and logical 0 = VSS to a higher voltage output signal (E, F, G, H) with logical 1 = VDD and logical 0 = VSS. The CD40109BMS, unlike other low-to-high level shifting circuits, does not require the presence of the high voltage supply (VDD) before the application of either the low voltage supply (VCC) or the input signals. There are no restrictions on the sequence of application of VDD, VCC, or the input signals. In addition, with one exception there are no restrictions on the relative magnitudes of the supply voltages or input signals within the device maximum ratings, provided that the input signal swings between VSS and at least 0.7VCC; VCC may exceed VDD, and input signals may exceed VCC and VDD. When operated in the mode VCC > VDD, the CD40109BMS will operate as a high-to-low level shifter. The CD40109BMS also features individual three-state output capability. A low level on any of the separately enabled three-state output controls produces a high impedance state in the corresponding output. The CD40109BMS is supplied in these 16-lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack H4T H1E H6W

Features
· High Voltage Type (20V Rating) · Independence of Power Supply Sequence Considerations - VCC can Exceed VDD - Input Signals can Exceed Both VCC and VDD · Up and Down Level Shifting Capability · Three-State Outputs with Separate Enable Controls · 100% Tested for Quiescent Current at 20V · 5V, 10V and 15V Parametric Ratings · Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC · Noise Margin (Over Full Package/Temperature Range) - 1V at VCC = 5V, VDD = 10V - 2V at VCC = 10V, VDD = 15V · Standardized Symmetrical Output Characteristics · Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of `B' Series CMOS Devices"

Applications
· High or Low Level Shifting with Three-State Outputs for Unidirectional or Bidirectional Bussing · Isolation of Logic Subsystems Using Separate Power Supplies from Supply Sequencing, Supply Loss and Supply Regulation Considerations

Pinout
CD40109BMS TOP VIEW

Functional Diagram
1 OF 4 UNITS

VCC VCC 1 ENABLE A 2 A 3 E 4 F 5 B 6 ENABLE B 7 VSS 8 16 VDD 15 ENABLE D A 14 D 13 H 12 NC 11 G 10 C 9 ENABLE C ENABLE A LEVEL SHIFTER LEVEL SHIFTER

VDD

E

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

File Number

3196

7-36

Specifications CD40109BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum

Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . . ja jc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W Maximum Package Power Dissipation (PD) at +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2 VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 VDD = 18V Output Voltage Output Voltage Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) N Threshold Voltage P Threshold Voltage Functional VOL15 VOH15 IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VNTH VPTH F VDD = 15V, No Load VDD = 15V, No Load (Note 3) VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) Tri-State Output Leakage VIL VIH VIL VIH IOZL VDD = 10V, VOH > 9V, VOL < 1V VCC = 5V VDD = 10V, VOH > 9V, VOL < 1V VCC = 5V VDD = 15V, VOH > 13.5V, VOL < 1.5V, VCC = 10V VDD = 15V, VOH > 13.5V, VOL < 1.5V, VCC = 10V VIN = VDD or GND VOUT = 0V VDD = 20V VDD = 18V Tri-State Output Leakage IOZH VIN = VDD or GND VOUT = VDD VDD = 20V VDD = 18V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 3 1 2 3 1 2 3 1, 2, 3 1, 2, 3 1 1 1 1 1 1 1 1 1 7 7 8A 8B 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1 2 3 1 2 3 +25oC, LIMITS TEMPERATURE +25oC +125oC -55oC +25oC +125oC -55oC +25oC +125oC -55oC +25oC, +125oC, -55oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +125oC -55oC +125oC, -55oC 3.5 7 -0.4 -12 -0.4 1.5 3 0.4 12 0.4 V V V V µA µA µA µA µA µA MIN -100 -1000 -100 0.53 1.4 3.5 -2.8 0.7 MAX 2 200 2 100 1000 100 50 -0.53 -1.8 -1.4 -3.5 -0.7 2.8 UNITS µA µA µA nA nA nA nA nA nA mV V mA mA mA mA mA mA mA V V V

PARAMETER Supply Current

SYMBOL IDD

CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND

+25oC, +125oC, -55oC 14.95

VOH > VOL < VDD/2 VDD/2

+25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC +125oC -55oC +25oC +125oC -55oC

3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max.

7-37

Specifications CD40109BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS TEMPERATURE 9 10, 11 9 10, 11 9 10, 11 9 10, 11 9 10, 11 9 10, 11 9 10, 11 9 10, 11 9 10, 11 9 10, 11 9 10, 11 9 10, 11 9 10, 11 9 10, 11 +25oC +125 C, -55 C +25oC +125oC, -55oC +25oC +125 C, -55 C +25oC +125oC, -55oC +25oC +125oC, -55oC +25 C +125oC, -55oC +25oC +125 C, -55 C +25oC +125 C, -55 C +25oC +125oC, -55oC +25 C +125oC, -55oC +25oC +125 C, -55 C +25oC +125 C, -55 C +25oC +125oC, -55oC +25 C +125oC, -55oC
o o o o o o o o o o o o o o o

LIMITS MIN MAX 600 810 260 351 500 675 460 621 100 135 200 270 120 162 400 540 740 999 500 675 640 864 600 810 200 270 400 540 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

PARAMETER Propagation Delay Data In to Out Shift Mode L-H Propagation Delay Data In to Out Shift Mode L-H Propagation Delay Data In to Out Shift Mode H-L Propagation Delay Data In to Out Shift Mode H-L Transition Time Shift Mode L-H Transition Time Shift Mode H-L Propagation Delay 3-State Shift Mode L-H Propagation Delay 3-State Shift Mode H-L Propagation Delay 3-State Shift Mode L-H Propagation Delay 3-State Shift Mode H-L Propagation Delay 3-State Shift Mode L-H Propagation Delay 3-State Shift Mode H-L Propagation Delay 3-State Shift Mode L-H Propagation Delay 3-State Shift Mode H-L NOTES:

SYMBOL TPHL1

CONDITIONS VDD = 10V, VIN = VCC or GND VCC = 5V (Notes 1, 2) VDD = 10V, VIN = VCC or GND VCC = 5V (Notes 1, 2) VDD = 5V, VIN = VCC or GND VCC = 10V (Notes 1, 2) VDD = 5V, VIN = VCC or GND VCC = 10V (Notes 1, 2) VDD = 10V, VIN = VDD or GND VCC = 5V (Notes 1, 2) VDD = 5V, VIN = VDD or GND VCC = 10V (Notes 1, 2) VDD = 10V, VIN = VCC or GND VCC = 5V (Notes 2, 3) VDD = 5V, VIN = VCC or GND VCC = 10V (Notes 2, 3) VDD = 10V, VIN = VCC or GND VCC = 5V (Notes 2, 3) VDD = 5V, VIN = VCC or GND VCC = 10V (Notes 2, 3) VDD = 10V, VIN = VCC or GND VCC = 5V (Notes 2, 3) VDD = 5V, VIN = VCC or GND VCC = 10V (Notes 2, 3) VDD = 10V, VIN = VCC or GND VCC = 5V (Notes 2, 3) VDD = 5V, VIN = VCC or GND VCC = 10V (Notes 2, 3)

TPLH1

TPHL2

TPLH2

TTHL1 TTLH1 TTHL2 TTLH2 TPHZ1 TPHZ2 TPLZ1 TPLZ2 TPZH1 TPZH2 TPZL1 TPZL2

1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. 3. CL = 50pF, RL = 1K, Input TR, TF < 20ns.

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = 5V, VIN = VDD or GND NOTES 1, 2 TEMPERATURE -55oC, +25oC MIN MAX 1 30 2 60 2 120 50 UNITS µA µA µA µA µA µA mV

+125oC VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC

+125oC VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC

+125oC Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC

7-38

Specifications CD40109BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Output Voltage Output Voltage Output Voltage Output Current (Sink) SYMBOL VOL VOH VOH IOL5 CONDITIONS VDD = 10V, No Load VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, VOUT = 0.4V NOTES 1, 2 1, 2 1, 2 1, 2 TEMPERATURE +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +125oC -55oC Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC -55oC Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC -55oC Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC -55oC Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC -55oC Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC -55oC Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC -55oC Input Voltage Low Input Voltage High Propagation Delay Data In to Data Out Shift Mode L-H Propagation Delay Data In to Out Shift Mode L-H Propagation Delay Data In to Out Shift Mode H-L Propagation Delay Data In to Out Shift Mode H-L Transition Time Shift Mode L-H Transition Time Shift Mode H-L Propagation Delay 3-State Shift Mode L-H Propagation Delay 3-State Shift Mode H-L Propagation Delay 3-State Shift Mode L-H VIL VIH TPHL1 VDD = 10V, VOH > 9V, VOL < 1V VCC = 5V VDD = 10V, VOH > 9V, VOL < 1V VCC = 5V VDD = 15V, VCC = 5V VDD = 15V, VCC = 10V TPLH1 VDD = 15V, VCC = 5V VDD = 15V, VCC = 10V TPHL2 VDD = 5V, VCC = 15V VDD = 10V, VCC = 15V TPLH2 VDD = 5V, VCC = 15V VDD = 10V, VCC = 15V TTHL1 TTLH1 TTHL2 TTLH2 TPHZ1 VDD = 15V, VCC = 5V VDD = 15V, VCC = 10V VDD = 5V, VCC = 15V VDD = 10V, VCC = 15V VDD = 15V, VCC = 5V VDD = 15V, VCC = 10V TPHZ2 VDD = 5V, VCC = 5V VDD = 10V, VCC = 15V TPLZ1 VDD = 15V, VCC = 5V VDD = 15V, VCC = 10V 1, 2 1, 2 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC 3.5 440 360 240 140 500 240 460 160 80 80 200 100 150 70 400 80 600 500 V ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MIN 4.95 9.95 0.36 0.64 0.9 1.6 2.4 4.2 MAX 50 -0.36 -0.64 -1.15 -2.0 -0.9 -1.6 -2.4 -4.2 1.5 UNITS mV V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA V

7-39

Specifications CD40109BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Propagation Delay 3-State Shift Mode H-L Propagation Delay 3-State Shift Mode L-H Propagation Delay 3-State Shift Mode H-L Propagation Delay 3-State Shift Mode L-H Propagation Delay 3-State Shift Mode H-L NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. CL = 50pF, RL = 1K, Input TR, TF < 20ns. SYMBOL TPLZ2 CONDITIONS VDD = 5V, VCC = 15V VDD = 10V, VCC = 15V TPZH1 VDD = 15V, VCC = 5V VDD = 15V, VCC = 10V TPZH2 VDD = 5V, VCC = 15V VDD = 10V, VCC = 15V TPZL1 VDD = 15V, VCC = 5V VDD = 15V, VCC = 10V TPZL2 VDD = 5V, VCC = 15V VDD = 10V, VCC = 15V NOTES 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC MIN MAX 500 260 460 360 600 260 160 80 400 80 UNITS ns ns ns ns ns ns ns ns ns ns

TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional SYMBOL IDD VNTH VTN VTP VTP F CONDITIONS VDD = 20V, VIN = VDD or GND VDD = 10V, ISS = -10µA VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VSS = 0V, IDD = 10µA VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 1, 2, 3, 4 +25oC NOTES 1, 4 1, 4 1, 4 1, 4 1, 4 1 TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25oC MIN -2.8 0.2 VOH > VDD/2 MAX 7.5 -0.2 ±1 2.8 ±1 VOL < VDD/2 1.35 x +25oC Limit UNITS µA V V V V V

ns

NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

3. See Table 2 for +25oC limit. 4. Read and Record

TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER Supply Current - MSI-1 Output Current (Sink) Output Current (Source) SYMBOL IDD IOL5 IOH5A ± 0.2µA ± 20% x Pre-Test Reading ± 20% x Pre-Test Reading DELTA LIMIT

TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test (Pre Burn-In) MIL-STD-883 METHOD 100% 5004 GROUP A SUBGROUPS 1, 7, 9 READ AND RECORD IDD, IOL5, IOH5A

7-40

Specifications CD40109BMS
TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Interim Test 1 (Post Burn-In) Interim Test 2 (Post Burn-In) PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A Group B Group D Subgroup B-5 Subgroup B-6 MIL-STD-883 METHOD 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 Sample 5005 Sample 5005 Sample 5005 Sample 5005 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3 Subgroups 1, 2, 3, 9, 10, 11 IDD, IOL5, IOH5A READ AND RECORD IDD, IOL5, IOH5A IDD, IOL5, IOH5A

NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.

TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-883 METHOD 5005 TEST PRE-IRRAD 1, 7, 9 POST-IRRAD Table 4 READ AND RECORD PRE-IRRAD 1, 9 POST-IRRAD Table 4

CONFORMANCE GROUPS Group E Subgroup 2

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION Static Burn-In 1 (Note 1) Static Burn-In 2 (Note 1) Dynamic Burn-In (Note 4) Irradiation (Note 2) NOTES: 1. Each pin except Pin 1, VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except Pin 1, VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V 3. Pin voltage is VDD/2 4. Each pin except Pin 1, VDD and GND will have a series resistor of 4.75K ±5%, VDD = 18V ±0.5V. OPEN 4, 5, 11-13 4, 5, 11-13 12 4, 5, 11-13 GROUND 2, 3, 6-10, 14, 15 8 8 8 VDD 1, 16 16 16 1-3, 6, 7, 9, 10, 14-16 1-3, 4, 7, 9, 10, 14, 15 1, 4, 5, 11, 13 3, 6, 10, 14 (Note 3) 2, 7, 9, 15 (Note 3) 9V ± -0.5V 50kHz 25kHz

Logic Diagram
VCC A 3 (6, 10, 14) VDD LEVEL SHIFTER E 4 (5, 11, 13) ENABLE A 2 (7, 9, 15) VDD

*

TRUTH TABLE INPUTS A, B, C, D 0
VSS VCC = 1 VDD = 16 VSS = 8

OUTPUTS E, F, G, H 0 1 Z

ENABLE A, B, C, D 1 1 0

*

LEVEL SHIFTER VDD

1 X

*

ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK

Logic 0 = Low(VSS) X = Don't care Z = High impedance Logic 1 = VCC at Inputs and VDD at Outputs

VSS

FIGURE 1. 1 OF 4 UNITS

7-41

CD40109BMS Typical Performance Characteristics
OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC

30 25 20 15 10 5

GATE-TO-SOURCE VOLTAGE (VGS) = 15V

15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 7.5 5.0 2.5 10V

10V

5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V

FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5

0

0 -5 -10 -15

0

0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) 100

-10V

-20 -25

-10V

-10

-15V

-30

-15V

-15

FIGURE 4. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS

FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS

AMBIENT TEMPERATURE (TA) = +25oC TRANSITION TIME (tTHL, tTLH) (ns) 350 HIGH-TO-LOW PROPAGATION DELAY TIME (tPHL) (ns)

AMBIENT TEMPERATURE (TA) = +25oC VCC = 5V, VDD = 10V 300 250 200 150 100 50 VCC = 5V, VDD = 15V VCC = 10V, VDD = 15V

200 SUPPLY VOLTAGE (VDD) = 5V

150

100 10V 50 15V

0 0

20

40 60 80 100 LOAD CAPACITANCE (CL) (pF)

0 0

10

40 70 80 20 30 50 60 LOAD CAPACITANCE (CL) (pF)

90

FIGURE 6. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE

FIGURE 7. TYPICAL HIGH-TO-LOW PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE

7-42

CD40109BMS Typical Performance Characteristics
AMBIENT TEMPERATURE (TA) = +25oC 175 LOW-TO-HIGH PROPAGATION DELAY TIME (tPLH) (ns) 150 VCC = 5V, VDD = 10V 125 VCC = 5V, VDD = 15V 100 75 50 25 0 VCC = 10V, VDD = 15V

(Continued)

INPUT SWITCHING VOLTAGE (VSWITCH) (V)

AMBIENT TEMPERATURE (TA) = +25oC 10 VCC VIN VSS 8 VDD 6 VOUT VSS 50% VCC = 15V ENABLE = VCC 4 VCC = 10V

*VSWITCH

2

VCC = 5V

*

0

10

20

30

40

50

60

70

80

90

100

0 2.5

VSWITCH = INPUT VOLTAGE AT WHICH OUTPUT LEVEL IS 50% OF VDD - VSS 17.5 20

5

LOAD CAPACITANCE (CL) (pF)

7.5 10 12.5 15 SUPPLY VOLTAGE (VDD) (V)

FIGURE 8. TYPICAL LOW-TO-HIGH PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE

FIGURE 9. TYPICAL INPUT SWITCHING AS A FUNCTION OF HIGH LEVEL SUPPLY VOLTAGE
DISSIPATION PER LEVEL SHIFTER (PD) (µW) 105 8
6 4 2

AMBIENT TEMPERATURE (TA) = +25oC SUPPLY VOLTAGE (VDD) (V) 25

AMBIENT TEMPERATURE (TA) = +25oC VCC = 5V, VDD = 15V

104

20

8 6 4 2

VCC = 5V, VDD = 10V VCC = 10V, VDD = 15V

15

103 8
6 4 2

10

RECOMMENDED OPERATING BOUNDARY

VCC = 5V, VDD = 10V

102

5

8 6 4 2

LOAD CAPACITANCE CL = 50pF CL = 15pF
2 4 68

0 0 5 10 15 20 25 SUPPLY VOLTAGE (VCC) (V)

10 1

10

102 103 104 INPUT FREQUENCY (fi) (kHz)

2

4 68

2

4 68

2

4 68

2

4 68

105

FIGURE 10. HIGH LEVEL SUPPLY VOLTAGE vs LOW LEVEL SUPPLY VOLTAGE

FIGURE 11. TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF INPUT FREQUENCY

Test Circuit and Waveform
TEST VOLTAGE
VCC 1 2 3 A INPUT (SEE TABLE) 4 5 6 7 8 VSS 16 15 14 13 12 11 10 OUTPUT 9 OUTPUT OUTPUT tPHZ 10% 90% RS (SEE CL TABLE) 50pF VCC ENABLE 50% INPUT tPLZ 50% VSS tPZL VDD 90% VOL VOH 10% VSS tPZH PULSE GENERATOR 1K B VDD

CHAR tPHZ tPLZ tPZL tPZH

AT A VCC VSS VSS VCC

AT B VSS VDD VDD VSS

FIGURE 12. OUTPUT ENABLE DELAY TIMES TEST CIRCUIT AND WAVEFORMS

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CD40109BMS Chip Dimensions and Pad Layout

Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch).

METALLIZATION: PASSIVATION:

Thickness: 11kÅ - 14kÅ,

AL.

10.4kÅ - 15.6kÅ, Silane

BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches

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