Text preview for : 4020.pdf part of Philips 4020 HEF4020B
MSI
14-stage binary counter
Back to : 4020.pdf | Home
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
· The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC · The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC
HEF4020B MSI 14-stage binary counter
Product specification File under Integrated Circuits, IC04 January 1995
Philips Semiconductors
Product specification
14-stage binary counter
DESCRIPTION The HEF4020B is a 14-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (O0, O3 to O13). The counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. A feature of the HEF4020B is: high speed (typ. 35 MHz at VDD = 15 V).
HEF4020B MSI
Fig.1 Functional diagram.
HEF4020BP(N): HEF4020BD(F): HEF4020BT(D):
16-lead DIL; plastic (SOT38-1) 16-lead DIL; ceramic (cerdip) (SOT74) 16-lead SO; plastic (SOT109-1)
( ): Package Designator North America PINNING Fig.2 Pinning diagram. CP MR O0, O3 to O13 clock input (HIGH to LOW edge triggered) master reset input (active HIGH) parallel outputs
FAMILY DATA, IDD LIMITS category MSI See Family Specifications
January 1995
2
Philips Semiconductors
Product specification
14-stage binary counter
HEF4020B MSI
Fig.3 Logic diagram.
January 1995
3
Philips Semiconductors
Product specification
14-stage binary counter
AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times 20 ns; see also waveforms Fig.4 VDD V Propagation delays CP 0 HIGH to LOW 5 10 15 5 LOW to HIGH On On + 1 HIGH to LOW 10 15 5 10 15 5 LOW to HIGH MR On HIGH to LOW Output transition times HIGH to LOW 10 15 5 10 15 5 10 15 5 LOW to HIGH Minimum clock pulse width; HIGH Minimum MR pulse width; HIGH Recovery time for MR Maximum clock pulse frequency 10 15 5 10 15 5 10 15 5 10 15 5 10 15 fmax tRMR tWMRH tWCPH 50 25 20 130 95 90 115 65 55 5 13 18 tTLH tTHL tPHL tPLH tPHL tPLH tPHL 105 45 30 105 50 35 80 30 20 70 25 20 180 90 70 60 30 20 60 30 20 25 15 10 65 50 45 60 35 25 10 25 35 210 90 65 210 95 70 160 60 40 140 50 40 360 180 140 120 60 40 120 60 40 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz SYMBOL MIN. TYP. MAX.
HEF4020B MSI
TYPICAL EXTRAPOLATION FORMULA 78 ns + (0,55 ns/pF) CL 34 ns + (0,23 ns/pF) CL 22 ns + (0,16 ns/pF) CL 78 ns + (0,55 ns/pF) CL 39 ns + (0,23 ns/pF) CL 27 ns + (0,16 ns/pF) CL 53 ns + (0,55 ns/pF) CL 19 ns + (0,23 ns/pF) CL 12 ns + (0,16 ns/pF) CL 43 ns + (0,55 ns/pF) CL 14 ns + (0,23 ns/pF) CL 12 ns + (0,16 ns/pF) CL 153 ns + (0,55 ns/pF) CL 79 ns + (0,23 ns/pF) CL 62 ns + (0,16 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL
January 1995
4
Philips Semiconductors
Product specification
14-stage binary counter
HEF4020B MSI
VDD V Dynamic power dissipation per package (P) 5 10 15
TYPICAL FORMULA FOR P (µW) 600 fi + (fo CL) × VDD 2 2 800 fi + (fo CL) × VDD 8 200 fi + (fo CL) × VDD
2 2
where fi = input freq. (MHz) fo = output freq. (MHz) CL = load cap. (pF) (foCL) = sum of outputs VDD = supply voltage (V)
Fig.4 Waveforms showing propagation delays for MR to On and CP to O0, minimum MR and CP pulse widths.
January 1995
5
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... January 1995 6 Product specification Fig.5 Timing diagram. Philips Semiconductors
14-stage binary counter HEF4020B MSI