Text preview for : 82C5086_Synchronous_SCSI_Controller_Nov89.pdf part of chipsAndTech 82C5086 Synchronous SCSI Controller Nov89 . Rare and Ancient Equipment chipsAndTech 82C5086_Synchronous_SCSI_Controller_Nov89.pdf
Back to : 82C5086_Synchronous_SCSI_ | Home
CHIPS AND TECHNOLOGIES, INC.
3050 ZANKER ROAD, SAN JOSE, CA 95134
408-434-0600
PRELIMINARY
82C5086
REFERENCE MANUAL
NOVEMBER 1989
CPI063/11-89
REVC
STK# 10063-001
CHIPS 82C5086 SCSI-Bus Interface Controller
Reference Manual
Document Number: 3001711-0001
Revision C
The infonnation in this publication is subject to change without notice.
No part of this publication may be reproduced, stored in a retrieval system,
or transmitted, in any fonn or by any means, electronic, mechanical,
photocopying, recording, or otherwise. without the prior written pennission
of Chips and Technologies Inc.
Copyright 1989 Chips and Technologies, Inc.
All Rights Reserved
CHIPS is a trademark of Chips and Technologies, Inc.
The following products trademarked by other companies are referenced in
this manual:
IBM PC AT is an IBM trademark.
Z8 is a Zilog trademark.
80286 is an Intel trademark.
ii
Revision History
Revision Change Activity Date Applioved
A First Release 1/29/88 P.H./ P.D.
B Second Release 10/31/88 P.H . ./M.S.
C Third Release 10/10/89 BJM/JC
iii
PREFACE
AUDIENCE
This manual is intended for firmware design engineers who are interested
in programming the CHIPS 82C5086 SCSI-Bus Interface Controller;
however, such topics as pin descriptions that would be of interest to
hardware design engineers are also addressed.
SCOPE
This manual contains the information a firmware design engineer needs to
program this chip to implement the SCSI (Small Computer System
Interface) interface on a host computer or a device controller. It is assumed
the reader already has a working knowledge of the SCSI interface.
CONTENTS
The information in this manual is divided into five chapters, one appendix,
and a glossary.
o Chapter 1 provides an overview of the CHIPS 82C5086 SCSI-Bus
Interface Controller.
o Chapter 2 which is intended for hardware design engineers
describes the 82C5086 hardware specifications. It supplies physical
and functional pin specifications, signal descriptions, electrical
specifications, and packaging specifications.
o Chapter 3 which is directed at firmware engineers describes the
operational modes of the 82C5086.
o Chapter 4 which is intended for firmware engineers provides a
detailed description of the function and operation of each of the 24
internal registers of the 82C5086.
o Chapter 5 provides a detailed description of the operation of each of
the 46 commands of the 82C5086. This chapter is intended for
firmware engineers.
o Appendix A contains a sample flow chart that illustrates the steps
involved in completing an asynchronous data transfer to a target
c device.
v