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HCF4034B
8 STAGE STATIC BIDIRECTIONAL PARALLEL/SERIAL INPUT OUTPUT BUS REGISTER
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BIDIRECTIONAL PARALLEL DATA INPUT PARALLEL OR SERIAL INPUTS/PARALLEL OUTPUTS ASYNCHRONOUS OR SYNCHRONOUS PARALLEL DATA LOADING. PARALLEL DATA-INPUTS ENABLED ON "A" DATA LINES (3-STATE OUTPUT) DATA RECIRCULATION FOR REGISTER EXPANSION MULTIPACKAGE REGISTER EXPANSION FULLY STATIC OPERATIONAL : DC to 5MHz (Typ.) at VDD = 10V QUIESCENT CURRENT SPECIF. UP TO 20V INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25°C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES"
SOP
ORDER CODES
PACKAGE SOP TUBE HCF4034BM1 T&R HCF4034M013TR
DESCRIPTION HCF4034B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in SOP packages. HCF4034B is a static eight-stage parallel-or serial-input parallel-output register. It can be used to : 1) bidirectionally transfer parallel information between two buses ; 2) convert serial data to parallel form and direct the parallel data to either PIN CONNECTION
of the two buses ; 3) store (recirculate) parallel data, or 4) accept parallel data from either of the two buses and convert the data to serial form. Inputs that control the operations include a single-phase CLOCK (CL), A DATA ENABLE (AE), ASYNCHRONOUS/SYNCHRONOUS (A/ S), A-BUS-TO-B-BUS/B-BUS-TO-A-BUS (A/B), and PARALLEL/ SERIAL (P/S). Data inputs include 16 bidirectional parallel data lines of which the eight A data lines are inputs (3-state outputs) and the B data lines are outputs (inputs) depending on the signal level on the A/B input. In addition, an input for SERIAL DATA is also provided. All register stages are D-type master-slave flip-flops with separate master and slave clock inputs generated internally to allow
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synchronous or asynchronous data transfer from master to slave. Isolation from external noise and the effects of loading is provided by output buffering. PARALLEL OPERATION - A high P/S input signal allows data transfer into the register via the parallel data lines synchronously with the positive transition of the clock, provided the A/S input is low. If the A/S input is high, the transfer is independent of the clock. The direction of data flow is controlled by the A/B input. When this signal is high the A data lines are inputs (and B data lines are outputs) ; a low A/B signal reverses the direction of data flow. The AE-input is an additional feature which allows many registers to feed data to a common bus. The A DATA lines are IINPUT EQUIVALENT CIRCUIT enabled only when this signal is high. Data storage through recirculation of data in each register stage is accomplished by making the A/B signal high and the AE signal low. SERIAL OPERATION - A low P/S signal allows serial data to transfer into the register synchronously with the positive transition of the clock. The A/S input is internally disabled when the register is in the serial mode (asynchronous serial operation is not allowed). The serial data appears as output data on either the B lines (when A/B is high) or the A lines (when A/B is low and the AE signal is high). Register expansion can be accomplished by simply cascading HCC/ HCF4034B packages. PIN DESCRIPTION
PIN No 8, 7, 6, 5, 4, 3, 2, 1 16, 17, 18, 19, 20, 21, 22, 23 9 15 10 11 13 14 12 24 SYMBOL 1 to 8 1 to 8 AE CL SERIAL INPUT A/B P/S A/S VSS VDD NAME AND FUNCTION B Data Lines A Data Lines "A" Data Enable Clock Input Serial Data input "A" Bus to "B" Bus or "B" Bus to "A" Bus Selector Parallel/Serial Selector Asynchronous/Synchronous Selector Negative Supply Voltage Positive Supply Voltage
FUNCTIONAL DIAGRAM
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LOGIC DIAGRAM (Steering Logic)
LOGIC DIAGRAM (Register Stage 1 Of 8 Stages)
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TRUTH TABLE (of the register stage)
INPUTS CL M * CL S * D L L L X H H H
X : Don't Care * : Level Change · : Invalid Condition
OUTPUT Q L L · L H H ·
TRUTH TABLE FOR REGISTER INPUT-LEVELS AND RESULTING REGISTER OPERATION
"A" Enable L L L L L L H H H H H H P/S L L H H H H L L H H H H A/B L H L L H H L H L L H H A/S X X L H L H X X L H L H OPERATION* Serial Mode; Synch. Serial Data Input, "A" Parallel Data Outputs Disabled Serial Mode; Synch. Serial Data Input, "B" Parallel Data Output Parallel Mode; "B" Synch. Parallel Data Inputs, "A" Parallel Data Outputs Disabled Parallel Mode; "B" Asynch. Parallel Data Inputs, "A" Parallel Data Outputs Disabled Parallel Mode; "A" Parallel Data Input Disabled, "B" Parallel Data Output, Synch. Data Recirculation Parallel Mode; "A" Parallel Data Input Disabled, "B" Parallel Data Output, Asynch. Data Recirculation Serial Mode; Synch. Serial Data Input, "A" Parallel Data Output Serial Mode; Synch. Serial Data Input, "B" Parallel Data Output Parallel Mode; "B" Synch. Parallel Data Input, "A" Parallel Data Output Parallel Mode; "B" Asynch. Parallel Data Input, "A" Parallel Data Output Parallel Mode; "A" Synch. Parallel Data Input, "B" Parallel Data Output Parallel Mode; "A" Asynch. Parallel Data Input, "B" Parallel Data Output
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TIMING CHART
ABSOLUTE MAXIMUM RATINGS
Symbol VDD VI II PD Top Tstg Supply Voltage DC Input Voltage DC Input Current Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature Storage Temperature Parameter Value -0.5 to +22 -0.5 to VDD + 0.5 ± 10 200 100 -55 to +125 -65 to +150 Unit V V mA mW mW °C °C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage.
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RECOMMENDED OPERATING CONDITIONS
Symbol VDD VI Top Supply Voltage Input Voltage Operating Temperature Parameter Value 3 to 20 0 to VDD -55 to 125 Unit V V °C
DC SPECIFICATIONS
Test Condition Symbol Parameter VI (V) 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 0.5/4.5 1/9 1.5/13.5 4.5/0.5 9/1 13.5/1.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 VO (V) |IO| VDD (µA) (V) 5 10 15 20 5 10 15 5 10 15 5 10 15 5 10 15 5 5 10 15 5 10 15 18 18 TA = 25°C Min. Typ. 0.04 0.04 0.04 0.08 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 -1.36 -0.44 -1.1 -3.0 0.44 1.1 3.0 -3.2 -1 -2.6 -6.8 1 2.6 6.8 ±10-5 ±10-4 5 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 3.5 7 11 1.5 3 4 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 Max. 5 10 20 100 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 Value -40 to 85°C Min. Max. 150 300 600 3000 4.95 9.95 14.95 0.05 0.05 0.05 -55 to 125°C Min. Max. 150 300 600 3000 Unit
IL
Quiescent Current
µA
VOH
High Level Output Voltage Low Level Output Voltage High Level Input Voltage Low Level Input Voltage Output Drive Current
VOL
VIH
VIL
IOH
IOL
Output Sink Current Input Leakage Current 3-State Output Leakage Current Input Capacitance
0/5 0/5 0/10 0/15 0/5 0/10 0/15 0/18 0/18
<1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1
V
V
V
V
mA
mA
II
Any Input Any Input Any Input
±0.1 ±0.4
7.5
±1 ±12
±1 ±12
µA µA
pF
IOZ CI
The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
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DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25°C, CL = 50pF, RL = 200K, tr = tf = 20 ns)
Test Condition Symbol Parameter VDD (V) 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 Min. Value (*) Typ. 350 120 85 200 80 60 100 50 40 80 30 20 25 15 10 175 70 40 4 10 14 125 50 35 Max. 700 240 170 400 160 120 200 100 80 160 60 40 50 30 20 350 140 80 ns Unit
tPHL tPLH Propagation Delay Time A (B) Parallel Data In to B (A) Parallel Data Out tPLZ tPHZ 3-State Propagation Delay tPZL tPZH Time A/B or AE to "A" OUT tTHL tTLH Transition Time
ns
ns
tsetup
Data Set-Up Time Serial Data to Clock Data Set-Up Time Parallel Data to Clock High-level Pulse Width, AE, P/S, A/S Maximum Clock Frequency Clock Pulse Width
ns
tsetup
ns
tW
ns
fCL
2 5 7
MHz 250 100 70 15 15 15
tW
ns
tr , tf (1)
Clock Input Rise or Fall Time
µs
(*) Typical temperature coefficient for all VDD value is 0.3 %/°C (1) : If more than one unit is cascaded. tr should be made less than or equal to the sum of the transition time and the fixed propagation delay of the output of the driving stage for the estimated capacitive load.
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TYPICAL APPLICATIONS 16 BIT PARALLEL IN/PARALLEL OUT PARALLEL IN/SERIAL IN PARALLEL OUT, SERIAL IN/SERIAL OUT REGISTER
16 BIT SERIAL IN/GATED PARALLEL OUT REGISTER
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FREQUENCY AND PHASE COMPARATOR
TIMING DIAGRAM
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SHIFT RIGHT/SHIFT LEFT WITH PARALLEL INPUTS
A "High" ("Low") on the Shift Left/Shift Right input allows serial data on the Shift Left Input (Shift Right Input) to enter the register on the positive transition of the clock signal. A "high" on the "A" Enable Input disables the "A" parallel data lines on Reg. 1 and 2 and enables the "A" data lines on registers 3 and 4 and allows parallel data into
registers 1 and 2. Other logics schemes may be used in place of registers 3 and 4 for parallel loading. When parallel inputs are not used Reg. 3 and 4 and associated logic are not required. * Shift Left input must be disabled during parallel entry.
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N-STAGE REGISTER WITH FIXED SERIAL OUTPUT LINE
SAMPLE AND HOLD REGISTER-SERIAL/PARALLEL IN-PARALLEL OUT
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SINGLE AND DOUBLE BUS SYSTEMS
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TEST CIRCUIT
TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ
CL = 50pF or equivalent (includes jig and probe capacitance) RL = 200K RT = ZOUT of pulse generator (typically 50)
SWITCH Open VDD VSS
WAVEFORM : PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle)
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SO-24 MECHANICAL DATA
mm. DIM. MIN. A a1 a2 b b1 C c1 D E e e3 F L S 7.40 0.50 15.20 10.00 1.27 13.97 7.60 1.27 8 ° (max.) 0.291 0.020 15.60 10.65 0.35 0.23 0.5 45° (typ.) 0.598 0.393 0.050 0.550 0.300 0.050 0.614 0.419 0.1 TYP MAX. 2.65 0.2 2.45 0.49 0.32 0.014 0.009 0.020 0.004 MIN. TYP. MAX. 0.104 0.008 0.096 0.019 0.012 inch
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PO13T
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. © http://www.st.com
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