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6x86-P200+ PROCESSOR
®
Advancing the Standards
Sixth-Generation Superscalar Superpipelined x86-Compatible CPU
6x86-P200+ PROCESSOR DATA BOOK ADDENDUM
Sixth-Generation Superscalar Superpipelined Architecture
- Operating frequency of 150 MHz core, 75 MHz bus - Optimized to run both 16-bit and 32-bit software applications - Dual 7-stage integer pipelines - High performance 80-bit FPU with 64-bit interface - 16-KByte unified write-back L1 cache
Best In-Class Performance Through Superior Architecture
- Register renaming - Out-of-order completion - Data dependency removal - Multi-branch prediction - Speculative execution
X86 Instruction Set Compatible
- Runs Windows 95, Windows 3.x, Windows NT, DOS, UNIX, OS/2, Solaris, and others
The Cyrix 6x86TM -P200+ has an identical architecture compared to previous 6x86 processors, but operates at a core frequency of 150 MHz. The 6x86 series of CPUs are superscalar, superpipelined sixth generation CPUs that offer the highest level of performance available for desktop personal computers. Optimized to run both 16-bit and 32-bit software applications, the 6x86 processor is fully compatible with the x86 instruction set and delivers industry-leading performance running Windows® 95, Windows, Windows NT, OS/2®, DOS Solaris, UNIX® and other operating systems.
The 6x86 processor achieves top performance through the use of two optimized superpipelined integer units and an on-chip floating point unit. Additionally, the integer and floating point units are optimized for maximum instruction throughput by using advanced architectural techniques including register renaming, out-of-order completion, data dependency removal, branch prediction and speculative execution. These design innovations eliminate many data dependencies and resource conflicts to achieve high performance when executing existing 16-bit and future 32-bit software applications.
Instruction Address
IF
Sequence Control Lines
ID1 ID2 AC1 AC2 EX WB FPU OpCode
X Pipe
Instruction Data
128 ID2 AC1 AC2 EX WB Y Pipe
32 Address A31-A3 BE7#-BE0#
X Data 32 Y Data 32
256-Byte Instruction Line Cache
32
Bus Interface Unit
Floating Point Queue
Integer Unit 32 32 Y Linear Address
16- KByte Unified Cache Data Cache Unit
64
D63-D0 64
Floating Point Processor
X Linear Address
CLK Floating Point Unit
64
32
Memory Management Unit
X Physical Address
Y Physical Address
Control
32
Bus Interface
1738502
May 13, 1996 2:31 pm c:\dataoem\!m1p200\m1p200.fm Revision 1.2
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May 1996 Order Number: 941xx-01
1
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Electrical Connections
Advancing the Standards
1.0
OVERVIEW
The Cyrix 6x86-P200+ Processor operates at a frequency of 150 MHz, and interfaces to a system with a 75 MHz bus. This document includes the electrical specifications for the 6x86-P200+ devices. The 6x86-P200+ timing information is included for refrence. Refer to the 6x86 Processor Data Book for complete information on the achitecture, programming interface and bus interface. 2.0 2.1 ELECTRICAL SPECIFICATIONS Electrical Connections
by utilizing all of the VCC and GND pins. The 6x86 CPU contains 296 pins with 53 pins connected to VCC and 53 connected to VSS (ground). 2.3 Pull-Up/Pull-Down Resistors
This section provides information on electrical connections, absolute maximum ratings, recommended operating conditions, DC characteristics, and AC characteristics. All voltage values in Electrical Specifications are measured with respect to VSS unless otherwise noted. 2.2 Power and Ground Connections and Decoupling
Table 4-1 lists the input pins that are internally connected to pull-up and pull-down resistors. The pull-up resistors are connected to VCC and the pull-down resistors are connected to VSS. When unused, these inputs do not require connection to external pull-up or pull-down resistors. The SUSP# pin is unique in that it is connected to a pull-up resistor only when SUSP# is not asserted.
Table 4-1. Pins Connected to Internal Pull-Up and Pull-Down Resistors
SIGNAL PIN NO. RESISTOR
Testing and operating the 6x86 CPU requires the use of standard high frequency techniques to reduce parasitic effects. The high clock frequencies used in the 6x86 CPU and its output buffer circuits can cause transient power surges when several output buffers switch output levels simultaneously. These effects can be minimized by filtering the DC power leads with low-inductance decoupling capacitors, using low impedance wiring, and
BRDYC# CLKMUL QDUMP# SMI# SUSP# TCK TDI TMS TRST# Reserved Reserved Reserved Reserved
Y3 Y33 AL7 AB34 Y34 M34 N35 P34 Q33 J33 W35 Y35 AN35
20-k pull-up 20-k pull-down 20-k pull-up 20-k pull-up (see text)
20-k pull-up
20-k pull-down
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Absolute Maximum Ratings
2.3.1
Unused Input Pins
All inputs not used by the system designer and not listed in Table 4-1 should be connected either to ground or to VCC. Connect active-high inputs to ground through a 20 k (± 10%) pull-down resistor and active-low inputs to VCC through a 20 k (± 10%) pull-up resistor to prevent possible spurious operation. 2.3.2 NC and Reserved Pins
Pins designated NC have no internal connections. Pins designated RESV or RESERVED should be left disconnected. Connecting a reserved pin to a pull-up resistor, pull-down resistor, or an active signal could cause unexpected results and possible circuit malfunctions. 2.4 Absolute Maximum Ratings
Table 2-1 lists the absolute maximum ratings for the 6x86 Processors. For further information on these ratings refer to the 6x86 Processor Data Book.
Table 2-1. Absolute Maximum Ratings
PARAMETER MIN MAX UNITS NOTES
Operating Case Temperature Storage Temperature Supply Voltage, VCC Voltage On Any Pin Input Clamp Current, IIK Output Clamp Current, IOK
-65 -65 -0.5 -0.5
110 150 4.0 VCC + 0.5 10 25
°C °C V V mA mA
Power Applied
Power Applied Power Applied
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Recommended Operating Conditions
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2.5
Recommended Operating Conditions
Table 2-2 presents the recommended operating conditions for the 6x86 CPU device.
Table 2-2. Recommended Operating Conditions
PARAMETER MIN MAX UNITS NOTES
TC Operating Case Temperature VCC Supply Voltage VIH High-Level Input Voltage VIL Low-Level Input Voltage IOH High-Level Output Current IOL Low-Level Output Current
0 3.15 2.0 -0.3
70 3.70 5.5 0.8 -1.0 5.0
°C V V V mA mA
Power Applied
VO=VOH(MIN) VO=VOL(MAX}
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DC Characteristics
2.6
DC Characteristics
Table 2-3. DC Characteristics (at Recommended Operating Conditions)
PARAMETER MIN TYP MAX UNITS NOTES
VOL VOH II
Output Low Voltage Output High Voltage Input Leakage Current For all pins except those listed in Table 4-1. Input Leakage Current For all pins with internal pull-downs. Input Leakage Current For all pins with internal pull-ups. Active ICC 150 MHz 5.9 64 35 2.4
0.4 ±15
V V
IOL = 5 mA IOH = -1 mA 0 < VIN < VCC
µA
IIH IIL ICC
200 -400
µA µA
VIH = 2.4 V See Table 4-1. VIL = 0.45 V See Table 4-1. Note 1, 5
7.0 105 55 15 20 25 15
A Note 1, 3, 5 mA mA pF pF pF pF Note 4,5 f = 1 MHz, Note 2 f = 1 MHz, Note 2 f = 1 MHz, Note 2 f = 1 MHz, Note 2
ICCSM Suspend Mode ICC 150 MHz ICCSS Standby ICC 0 MHz (Suspended/CLK Stopped) CIN Input Capacitance COUT Output Capacitance COUT I/O Capacitance CCLK CLK Capacitance
Notes: 1. Frequency (MHz) ratings refer to the internal clock frequency. 2. Not 100% tested. 3. All inputs at 0.4 or VCC - 0.4 (CMOS levels). All inputs held static except clock and all outputs unloaded (static IOUT = 0 mA). 4. All inputs at 0.4 or VCC - 0.4 (CMOS levels). All inputs held static and all outputs unloaded (static IOUT = 0 mA). 5. Typical, measured at VCC = 3.52 V.
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AC Characteristics
Advancing the Standards
2.7
AC Characteristics
Tables 2-6 through 2-11 (Pages 2-7 through 2-13) list the AC characteristics including output delays, input setup requirements, input hold requirements and output float delays. These measurements are based on the measurement points identified in Figure 2-1 (Page 2-5) and Figure 2-2 (Page 2-6). The rising , clock edge reference level VREF and other reference levels are shown in Table 2-4. Input or output signals must cross these levels during testing. Figure 2-1 shows output delay (A and B) and input setup and hold times (C and D). Input setup and hold times (C and D) are specified minimums, defining the smallest acceptable sampling window a synchronous input signal must be stable for correct operation.
The AC tables lists the 6x86-P166+ (66 MHz) device for comparison with the 6x86-P200+ (75 MHz). The correspondence between core frequency, bus frequency and Performance (P) rating is shown Table 2-4. The plus sign (+) indicates that testing has shown that the performance of the device was actually higher than its stated P rating.
Table 2-4. 6x86 Devices
DEVICE NUMBER FREQUENCY (MHz) CORE BUS
6x86-P90 GP 6x86-P120+GP 6x86-P133+GP 6x86-P150+GP 6x86-P166+GP 6x86-P200+GP
+
80 100 110 120 133 150
40 50 55 60 66 75
6
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AC Characteristics
Tx
VIHD
CLK: VILD
VREF
VREF
A B
OUTPUTS:
MAX
MIN VREF Valid Output n+1
Valid Output n
VREF
C
VIHD INPUTS: VILD LEGEND:
A - Maximum Output Delay Specification B - Minimum Output Delay Specification C - Minimum Input Setup Specification D - Minimum Input Hold Specification
D
VREF Valid VREF Input
1709407
Figure 2-1. Drive Level and Measurement Points for Switching Characteristics
Table 2-5. Drive Level and Measurement Points for Switching Characteristics
SYMBOL VOLTAGE (Volts)
VREF VIHD VILD
Note: Refer to Figure 2-1.
1.5 2.3 0
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AC Characteristics
Advancing the Standards
Table 2-6. Clock Specifications TCASE = 0°C to 70°C, See Figure 2-2
PARAMETER 66-MHz BUS MIN MAX 75-MHz BUS MIN MAX UNITS
T1 T2 T3 T4 T5 T6
CLK Frequency CLK Period CLK Period Stability CLK High Time CLK Low Time CLK Fall Time CLK Rise Time
15.0 4.0 4.0 0.15 0.15
66.6 30.0 ±250
13.3 4.0 4.0 0.15 0.15
75 26.7 ± 250
1.5 1.5
1.5 1.5
MHz ns ps ns ns ns ns
T1
T3 V IH(MIN)
V REF V IL(MAX) T6 T4 T5
1740503
Figure 2-2. CLK Timing and Measurement Points
8
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AC Characteristics
.
Table 2-7. Output Valid Delays CL = 50 pF, Tcase = 0°C to 70°C, See Figure 2-3
PARAMETER 66-MHz BUS MIN MAX 75-MHz BUS MIN MAX UNITS
T7a
T7b T8 T9 T10 T11 T12a T12b T13 T14
A31-A3, BE7#-BE0#, CACHE#, D/C#, LBA#, LOCK#, PCD, PWT, SCYC, SMIACT#, W/R# ADS#, M/IO# ADSC# AP APCHK#, PCHK#, FERR# D63-D0, DP7-DP0 (Write) HIT# HITM# BREQ, HLDA SUSPA#
1.0
7.0
1.0
7.0
ns
1.0 1.0 1.0 1.0 1.3 1.0 1.1 1.0 1.0
6.0 7.0 8.5 7.0 7.5 8.0 6.0 8.0 8.0
1.0 1.0 1.0 1.0 1.3 1.0 1.1 1.0 1.0
6.0 7.0 8.5 7.0 7.5 8.0 6.0 8.0 8.0
ns ns ns ns ns ns ns ns ns
Tx CLK
Tx
Tx
Tx
MIN
MAX
T7 - T14
OUTPUTS
VALID n
VALID n+1
1740901
Figure 2-3.
Output Valid Delay Timing
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AC Characteristics
Advancing the Standards
Table 2-8. Output Float Delays , CL = 50 pF Tcase = 0°C to 70°C, See Figure 2-5
PARAMETER 66-MHz BUS MIN MAX 75-MHz BUS MIN MAX UNITS
T15
T16 T17
A31-A3, ADS#, BE7#-BE0#, BREQ, CACHE#, D/C#, LBA#, LOCK#, M/IO#, PCD, PWT, SCYC, SMIACT#, W/R# AP D63-D0, DP7-DP0 (Write)
10
10
ns
10 10
10 10
ns ns
Tx CLK
Tx
Tx
Tx
MIN MAX
T15 - T17 OUTPUTS VALID 1741001
Figure 2-4. Output Float Delay Timing
10
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AC Characteristics
Table 2-9. Input Setup Times Tcase = 0°C to 70°C, See Figure 2-5
PARAMETER 66-MHz BUS MIN 75-MHz BUS MIN UNITS
T18 T19 T20 T21 T22a T22b T22c T23 T24 T25 T26
A20M#, FLUSH#, IGNNE#, SUSP# AHOLD, BHOLD, BOFF#, DHOLD, HOLD BRDY# BRDYC# A31-A3, BE7#-BE0# AP D63-D0 (Read), DP7-DP0 (Read) EADS#, INV INTR, NMI, RESET, SMI#, WM_RST EWBE#, KEN#, NA#, WB/WT# QDUMP#
5.0 5.0 5.0 5.0 5.0 5.0 3.0 5.0 5.0 4.5 5.0
3.3 3.3 3.3 3.3 3.3 4.0 3.0 3.3 3.3 3.0 3.3
ns ns ns ns ns ns ns ns ns ns ns
Table 2-10. Input Hold Times Tcase = 0°C to 70°C, See Figure 2-5
SYMBOL PARAMETER 66-MHz BUS MIN 75-MHz BUS MIN UNITS
T27 T28 T29 T30 T31a T31b T32 T33 T34 T35
A20M#, FLUSH#, IGNNE#, SUSP# AHOLD, BHOLD, BOFF#, DHOLD, HOLD BRDY# BRDYC# A31-A3, AP, BE7#-BE0# D63-D0, DP7-DP0 (Read) EADS#, INV INTR, NMI, RESET, SMI#, WM_RST EWBE#, KEN#, NA#, WB/WT# QDUMP#
1.0 1.0 1.0 1.0 1.0 2.0 1.0 1.0 1.0 1.0
1.0 1.0 1.0 1.0 1.0 2.0 1.0 1.0 1.0 1.0
ns ns ns ns ns ns ns ns ns ns
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AC Characteristics
Advancing the Standards
Tx CLK T18 - T26 SETUP
Tx
Tx
Tx
T27 - T35 HOLD
1740600
Figure 2-5. Input Setup and Hold Timing
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AC Characteristics
Table 2-11. JTAG AC Specifications
SYMBOL PARAMETER ALL BUS FREQUENCIES MIN MAX UNITS FIGURE
T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47 T48 T49
TCK Frequency (MHz) TCK Period TCK High Time TCK Low Time TCK Rise Time TCK Fall Time TDO Valid Delay Non-test Outputs Valid Delay TDO Float Delay Non-test Outputs Float Delay TRST# Pulse Width TDI, TMS Setup Time Non-test Inputs Setup Time TDI, TMS Hold Time Non-test Inputs Hold Time
20 50 25 25 5 5 20 20 25 25
3 3
40 20 20 13 13
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
4-6 4-6 4-6 4-6 4-6 4-7 4-7 4-7 4-7 4-8 4-7 4-7 4-7 4-7
T36
T37 V IH VREF V IL T39 T38 T40
1741103
Figure 2-6. TCK Timing and Measurement Points
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AC Characteristics
Advancing the Standards
TCK
1.5 V T46 T48
TDI TMS
T41 T43
TDO
T42 T44
OUTPUT SIGNALS
T47 T49
INPUT SIGNALS
1740400
Figure 2-7. JTAG Test Timings
T45 TRST#
1.5 V 1741200
Figure 2-8. Test Reset Timing
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