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Cyrix III CPU BIOS Writer’s Guide
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Application Note 120 Cyrix III CPU BIOS Writer's Guide
Cyrix Processors
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REVISION HISTORY
Date 11/24/99 5/20/99 4/19/99 3/22/99 3/17/99 2/23/99 1/29/99 12/14/98 9/21/98 Version 1.1 1.0 0.43 0.42 0.41 0.4 0.3 0.2 0.1 Revision Updated register 49h and DIR1 table Updated for Cyrix III Format changes, chapter 6. Changed processor internal code name from MXs to Cyrix III. Page 55: Added Core to Bus Clock Ratio Configuration Register. Added Confidential Notice. Made all pages same width. Minor changes: Changed fonts, added revision page, changed DIR table titles Cyrix III information added. Completed Table page 32 Intial First Draft based on App Notes 112 and 118. C:\documentation\joshua\appnotes\j120ap.fm (confidential)
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Table of Contents 1.0 1.1 1.2 1.3 2.0 2.1 2.2 2.3 2.4 3.0 3.1 3.2 3.3 3.4 3.5 3.6 4.0 4.1 4.2 4.3 5.0 5.1 5.2 5.3 5.4 5.5 6.0 6.1 6.2 6.3 6.4 Introduction Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Cyrix Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Summary of Cyrix III, MII, 6x86MX and 6x86 Differences . . . . . . . . . . . . . . . . . . . . 4 Cyrix III CPU Detection CPU Detection and Inquiry Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 CPU Detection Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Standard and Extended CPUID Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Non CPUID Test and Inquiry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Cyrix III Configuration Register Index Assignments Accessing a Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cyrix III Configuration Register Index Assignments . . . . . . . . . . . . . . . . . . . . . . . . Configuration Control Registers (CCR0-6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Region Registers (ARR0-7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Region Control Registers (RCR0-7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BIOS Clock Multiplier Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Cyrix III Configuration Register Settings PC Memory Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 General Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Recommended Bit Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Model Specific Registers Time Stamp Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Performance Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Performance Monitoring Counters 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Counter Event Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PM Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming Model Differences Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuring Internal Cyrix III Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INVD and WBINVD Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Register 0 (CR0) CD and NW Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -Sample Code: Detecting a Cyrix CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -Sample Code: Determining CPU MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -Example CPU Type and Frequency Detection Program . . . . . . . . . . . . . . . . -Sample Code: Programming Cyrix III Configuration Registers . . . . . . . . . . -Sample Code: Controlling the L1 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . -Example Configuration Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 57 57 57 59 60 63 65 66 67 50 50 51 51 52 23 23 26 33 35 40
Appendix A Appendix B Appendix C Appendix D Appendix E Appendix F
Cyrix Application Note 120: Cyrix III BIOS Writer's Guide
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APPLICATION NOTE 120
Cyrix III BIOS Writer's Guide
1. Introduction 1.1 Scope
This document is intended for Cyrix III system BIOS writers. It is not a stand-alone document, but a supplement to other Cyrix documentation including the Cyrix III Data Books, and Cyrix SMM Programmer's Guide. Recommendations for Cyrix III detection and configuration register settings are included. The recommended settings are optimized for performance and compatibility in Windows95 or Windows NT, Plug and Play (Pnp), PCI-based system. Performance optimization, CPU detection, chipset initialization, memory discovery, I/O recovery time, and other functions are described in detail.
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1.2 Cyrix Configuration Registers
The Cyrix III uses on-chip configuration registers to control the on-chip cache, system management mode (SMM), device identification, and other Cyrix III specific features. The on-chip registers are used to activate advanced performance features. These performance features may be enabled "globally" in some cases, or by a user-defined address region. The flexible configuration of the Cyrix III is intended to fit a wide variety of systems. BIOS needs to perform 3 basic functions outlined in this document. They are: 1) Identification of Cyrix III cpu, frequency, and performance rating. 2) Set up of Configuration Registers in the cpu to enable features, turn on cache, and set clock multiplier. 3) Set up Address Region Registers and Region Control Registers to control memory accesses.
The Importance of Non-Cacheable Regions
The Cyrix III has fourteen internal user-defined Address Region Registers and Region Control Registers. Among other attributes, the regions define cacheability of the address regions. Using this cacheability information, the Cyrix III is able to implement high performance features, that would otherwise not be possible. A non-cacheable region implies that read sourcing from the write buffers, data forwarding, data bypassing, speculative reads, and fill buffer streaming are disabled for memory accesses within that region. Additionally, strong cycle ordering is also enforced. The Cyrix III also uses these Address Region Registers to setup the write gathering, or write combining, feature normally used for improving performance of video buffer memory. This feature is enabled differently from the Intel Celeron. Celeron uses machine specific registers (MSR's) called memory type and range registers (MTRR's). Cyrix III uses the Address Region Registers (ARR's) and Region Control Registers (RCR's) to perform this same feature. Thus BIOS, operating system calls, and video drivers should be updated with ARR and RCR setup instead of MTRR setup whenever Cyrix III is detected to enable write combining feature.
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2. CPU Detection
The Cyrix III cpu can be identified using the CPU_ID instruction as explained below. It can also be identified using Cyrix specific Device Identification Registers (DIR). The methods for identifying the cpu and its available features are explained below. Once the Cyrix III cpu is identified, it should be named correctly as explained in the next section.
2.1 CPU Name and Performance Rating
The Cyrix III uses the performance rating system of speed measurement and reporting. The following table is used to identify the performance rating of the Cyrix III compared to actual Mhz. The performance rating is achieved by benchmarking the Cyrix III vs. a Celeron cpu in the same configuration.
CPU Name and PR rating Cyrix III - 433 Cyrix III - 466 Cyrix III - 500 Cyrix III - 533 Cyrix III - 533 Cyrix III - 566 Cyrix III - 600
Bus Speed Mhz 100 122 133 124 100 133 100
Core Speed Mhz 350 366 400 433 450 466 500
Clock Multiplier 3.5 3.0 3.0 3.5 4.5 3.5 5.0
2.2 Cyrix CPU Identification and Inquiry Flow Chart
The Cyrix CPU Identification process (Figure1 on page6) consists of up to three tests and three inquiries. If CPUID is not supported, a 5/2 Test is performed to check if the CPU is a Cyrix part. If CPUID is supported, a second test is made to see if extended level CPUID is supported.
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The numbers in parenthesis shown in Figure 1 refer to the supporting paragraphs in this manual.
Cyrix CPU Detection and Inquiry
Supports CPUID? (3.1) No Yes Cyrix CPU (3.2) (Perform "CyrixInstead" Test)? Yes Perform DIR0, DIR1 Inquiry (3.4.2) No Non-Cyrix CPU
Exit Supports Extended CPUID? (3.3.1) No Perform Standard CPUID (3.3.2) Yes
Perform Extended CPUID Inquiry (3.3.3)
FIGURE 1.
CPU Identification and Inquiry
Note: The testing must be performed in the order shown in Figure 1 or testing may be invalid.
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2.3 CPU Detection Steps: CPUID Support Test
In order to avoid an invalid opcode exception on processors that do not support the CPUID instruction, software must first verify that the processor supports the CPUID instruction. The presence of the CPUID instruction is indicated by the ID bit (bit 21) in the EFLAGS register. If this bit can be toggled, the CPUID instruction is present and enabled on the processor. The following code will check for the presence of the CPUID instruction. CPUID Support Test Sample Code*:
pushfd ; get extended flags pop eax ; store extended flags in eax mov ebx, eax ; save current flags xor eax, 200000h ; toggle bit 21 push eax ; put new flags on stack popfd ; flags updated now in flags pushfd ; get extended flags pop eax ; store extended flags in eax xor eax, ebx ; if bit 21 r/w then eax <> 0 je no_cpuid ; can't toggle id bit (21) no cpuid here
*Note: It has been assumed that the tests for EFLAGS support has been complete prior to this point. If CPUID is supported, it can be assumed that the CPU is an 80486 or above class processor.
2.3.1
"CyrixInstead" Test
The CPUID instruction level 0 provides vendor information. Following execution of the CPUID instruction with an input value of "0" in EAX, the EBX, ECX and EDX registers contain the vendor string of the CPU. To verify that the processor is a Cyrix CPU, the software checks for "CyrixInstead" in the return registers as shown in the sample code below: "CyrixInstead" Test Sample Code
mov cpuid cmp jne cmp jne cmp jne eax, 0 ebx, 'iryC' not_cyrix edx, 'snIx' not_cyrix ecx, 'daet' not_cyri ; CPUID standard level 0
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2.4 Standard and Extended CPUID Levels
The CPUID instruction has been extended on recent processors so that additional information can be obtained from the CPU concerning items including stepping, model, family, type, TLB and cache information. The original levels of the CPUID instruction are termed "the standard CPUID levels" and the newer levels are termed the "extended CPUID levels." The standard and extended CPUID levels differ in that the EAX register's most significant bit is set for the extended CPUID levels. Both the standard and extended CPUID levels may be executed at any privilege level. The EAX register provides the input value for the CPUID instruction to indicate what information should be returned by the instruction.
2.4.1
Extended CPUID Level Support Testing
This test is performed to determine if the CPU supports the extended CPUID levels. Extended CPUID Instruction support testing consists of executing a CPUID instruction with the EAX register initialized to 8000 0000h and testing the return value in EAX. If a value greater than or equal to 8000 0000h is returned to the EAX register by the CPUID instruction, the CPU can execute extended CPUID instructions. The following sample code tests for Extended CPUID support. Extended CPUID Instruction Test Sample Code:
mov eax, 80000000h ; try extended cpuid level cpuid ; execute cpuid instruction cmp eax, 80000000h ; check if extended levels are supported jb no_extended ; extended cpuid functions not available
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2.4.2
Standard CPUID Instruction Inquiry
The CPUID instruction provides processor and feature set information. This instruction may be executed at any privilege level. The standard CPUID instruction is defined as a CPUID instruction with the EAX register initialized to one of the following values: 0000 0000h - maximum standard levels supported and vendor string 0000 0001h - family, model and stepping information 0000 0002h - cache and TLB information Table 1. summarizes the CPUID values returned by standard CPUID levels on Cyrix III processors. Table 1. Summary of Returned Standard CPUID Values
DESCRIPTION Maximum Standard Value Stepping Model Family Type TLB/Cache IN ITIAL EAX V ALUE 0h 1h 1h 1h 1h 2h CYRIX III 2h xxh 5h 6h 0h xxh
Note: xx = stepping revision specific.
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2.4.3
CPUID Instruction with EAX = 0000 0000h
Standard function 0h (EAX = 0) of the CPUID instruction returns the maximum standard CPUID levels supported by the current processor to the EAX register. The maximum standard CPUID level is the highest acceptable value for the EAX register input. After the instruction is executed registers EBX through EDX contain the vendor string of the processor. Note that the middle section is placed (out of order) into the EDX register (Table 2). Table 2.
REGISTER * EAX EBX EDX ECX
Standard CPUID with EAX = 0000 0000h
C ONT ENT S Max Standard Levels Vendor ID String 1="CYRI" Vendor ID String 2="XINS" Vendor ID String 3="TEAD"
*Note: The register order is correct.
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2.4.4
CPUID Instruction with EAX = 0000 0001h
Standard function 01h (EAX = 1) of the CPUID instruction returns the Processor Type, Family, Model, and Stepping information of the current processor in EAX (Table 3). The Standard Feature Flags supported are returned in the EDX register. The other registers upon return are currently reserved. Table 3.
REGISTER EAX[3:0] EAX[7:4] EAX[11:8] EAX[15:12] EAX[31:16] EBX ECX EDX
Standard CPUID with EAX = 0000 0001h
CONTENTS Stepping ID=revision specific step id Model=5 h Family=6 h Type=0 h Reserved Reserved Reserved Standard Feature Flags=0080A13D h
Standard Feature Flags The standard feature flags are returned in the EDX register when the CPUID instruction is called with standard function 01h (EAX = 1). Each flag refers to a specific feature and indicates if that feature is present on the processor. Some of these features require enabling or have protection control in CR4. Table 4. summarizes the standard feature flags.
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Before using any of these features on the processor, the software should check the corresponding feature flag (Table 4). Attempting to execute an unavailable feature can cause exceptions and unexpected behavior. For example, software must check bit 4 before attempting to use the Time Stamp Counter instruction. Table 4. Standard Feature Flags Values Returned in EDX
EDX B IT CR4 B IT C YRIX III 1 01 1 1 1 1 0 0 1 0 0 0 0 1 0 1 0 0 00000 1 0 0000000
FEATUR E F LAG
FPU On-Chip Virtual Mode Extensions (V86) Debug Extension 4 MB Page Size Time Stamp Counter RDMSR/WRMSR Instructions Physical Address Extensions Machine Check Exception CMPXCHG8B Instruction Support On-chip APIC Hardware Reserved SYSENTER/SYSEXIT Instructions Memory Type Range Registers (MTRR) Page Global Enable (PTE-PGE) Machine Check Architecture Conditional Move Instruction (CMOV) Page Attribute Table 36-Bit Page Size Extensions Reserved MMXTM Instructions Fast FPU Save and Restore Reserved
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18-22 23 24 25-31
0,1 3 4 2 8 5 6 7 -
*Note: The CPUID instruction is disabled by default.
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2.4.5
CPUID Instruction with EAX = 0000 0002h
Standard function 02h (EAX = 02h) of the CPUID instruction returns information that is specific to the Cyrix family of processors. Information about the TLB is returned in EAX. Information about the L1 Cache is returned in EDX. This information is to be looked up in a lookup table. See Table 13 on page 19. Table 5.
REGISTER EAX EBX ECX EDX
Standard CPUID with EAX = 0000 0002h
C ON TEN TS TLB Information = 00747701 h Reserved Reserved L1 Cache Information = 00008242 h
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2.4.6
Extended CPUID Levels
The extended CPUID Instruction is defined when the EAX register is initialized to one of the following values (Table 6.): 8000 0000h - Maximum Levels 8000 0001h - Processor Information/Extended features 8000 0002h - Processor Marketing Name 8000 0003h - Processor Marketing Name 8000 0004h - Processor Marketing Name 8000 0005h - TLB/Cache Information Each of the extended CPUID levels reports information that is specific to the Cyrix family of processors. Table 6. Summary of Returned Extended CPUID Values
D ESCRIPTION Extended Levels TLB Info Cache Info INITIA L EAX V ALU E 8000 0000h 8000 0005h 8000 0005h CYRIX III 5h TBD TBD
*Note: The CPUID instruction is disabled by default.
Table 7.
E XTENDED F UNCTION 8000 0000h 8000 0001h 8000 0002h 8000 0003h 8000 0004h 8000 0005h
Summary of CPUID Functions
D ESCRIPTION Extended Levels Extended Processor Info. Extended Feature Flags Processor Marketing Name Processor Marketing Name Processor Marketing Name TLB & Cache Information X X X X CYRIX III X X
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2.4.7
CPUID Instruction with EAX = 8000 0000h
Extended function 8000 0000h (EAX = 8000 0000h) of the CPUID instruction returns the maximum extended CPUID levels supported by the current processor in EAX (Table 8). The other registers are currently reserved. Table 8.
REGISTER EAX EBX ECX EDX
Maximum Extended CPUID Level
C ON TENTS Maximum Extended Levels = 5 h Reserved Reserved Reserved
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2.4.8
CPUID Instruction with EAX = 8000 0001h
Extended function 8000 0001h (EAX = 8000 0001h) of the CPUID instruction returns the Processor Type, Family, Model, and Stepping information of the current processor in EAX (Table 9). The Extended Feature Flags supported are returned in EDX. The other registers are currently reserved. Table 9.
REGISTER EAX[3:0] EAX[7:4] EAX[11:8] EAX[15:12] EAX[31:16] EBX ECX EDX
. Processor Signature and Extended Feature Flags
C ON TENTS Stepping ID = revision specific step id Model = 5 Family = 6 Processor Type = 0 Reserved Reserved Reserved Extended Feature Flags = 0080A13D
Extended Feature Flags The extended feature flags are returned in the EDX register when the CPUID instruction is called with extended function 8000 0001h (EAX = 8000 0001h). Each flag refers to a specific feature and indicates if that feature is present on the processor. Some of these features require enabling or have protection control in CR4. Table 10. summarizes the extended feature flags.
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Table 10.
F EATURE F LAG Floating Point Unit Virtual Mode Extensions (V86) Debug Extension Page Size Extensions (4 MByte) Time Stamp Counter Cyrix Model-Specific Registers (MSR) Reserved Machine Check Exception CMPXCHG8B Instruction SYSCALL and SYSRET Instructions Reserved Global Paging Extension (PTE-PGE) Reserved
Extended Feature Flags
EDX B IT 0 1 2 3 4 5 6 7 8 11 12 13 14 15 16 17-22 23 24 25 - 30 31 X X X CR4 B IT 0,1 3 4 2 8 6 7 C YR IX III 1 01 X X X X
Integer Conditional Move Instructions (CMOV) Floating-Point Conditonal Move Instructions Reserved MMXTM Instructions Cyrix 6x86MX Multimedia Extensions Reserved 3DNow!TM Instructions
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2.4.9
CPUID Instruction with EAX = 8000 0002h - 8000 0004h
Extended functions 8000 0002h through 8000 0004h (EAX = 8000 0002h through EAX = 8000 0004h) of the CPUID instruction returns an ASCII string containing the name of the current processor (Table 11). These functions eliminate the need to look up the processor name in a lookup table. Software can simply call these functions to obtain the name of the processor. The string may be 48 ASCII characters long, and is returned in little endian format. If the name is shorter than 48 characters long, the remaining bytes will be filled with ASCII NUL character (00h). Table 11.
8000 0002 H EAX EBX ECX EDX CPU Name 1 CYRI X II I(tm) EAX EB X EC X EDX
Official CPU Name
8000 0003H CPU Name 5 CPU Name 6 CPU Name 7 CPU Name 8 EAX EBX ECX EDX 8000 0004 H CPU Name 9 CPU Name 10 CPU Name 11 CPU Name 12
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2.4.10 CPUID Instruction with EAX = 8000 0005h
Extended function 8000 0005h (EAX = 8000 0005h) of the CPUID instruction returns information about the TLB and L1 Cache to be looked up in a lookup table. Refer to Tables Figure 12 and Figure 13 shown below. Table 12.
R EGIST ER EAX EBX ECX EDX Reserved TLB Information L1 Cache Information Reserved
Cache and TLB Information
C ONT EN TS
Table 13.
CPUID L EVEL Standard Extended Standard Extended Standard Extended R EGISTER EAX EBX EAX EBX EDX ECX
Cache and Descriptor Lookup Table
V ALUE COMMENTS The CPUID instruction needs to be executed only once with an input value of 02h to retrieve complete information about the cache and TLB. TLB is 32 Entry, 4-way set associative, and has 4 KByte Pages L1 cache is 16 KBytes, 4-way set associative, and has 16 bytes per line.
xx xx xx 01h
xx xx 70 xxh
xx xx xx 80h
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2.5 Non-CPUID Testing and Inquiry
The Cyrix III processor supports CPUID to determine processor type. If it is a Cyrix processor, inquires may also be made to the Device Identification Registers (DIR0 and DIR1) to determine which Cyrix processor is present.
2.5.1
DIR0, DIR1 Inquiry
After determining that a Cyrix processor without CPUID exists, its Device ID Registers (DIR) can be read to identify the Cyrix processor type. The Device ID Registers are located using register indexes FEh and FFh. Access to these registers is achieved by writing the index of the register to I/O port 22h. I/O port 23h is then used for data transfer. Each port 23h data transfer must be preceded by a port 22h-register index selection; otherwise the second and later port 23h operations are directed off-chip and produce external I/O cycles. The Tables 14 and 15 describe the bit definitions for the DIR0 and DIR1 Registers. Table 14.
B IT P OSIT ION 7-4 3-0
DIR0 Bit Definitions
D ESCR IPTION
CPU Device Identification Number (read only) CPU Clock Multiplier (read only)
Table 15.
B IT P OSIT ION 7-4 3-0
DIR1 Bit Definitions
DESCRIPTION
CPU Step Identification Number (read only) CPU Revision Identification (read only)
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Table 16. describes the range of DIR0 values for the different generations of Cyrix CPU's Table 16. CPU Generation Values in DIR0
DIR0 V ALUES 80h - 8Fh D ESCRIPT ION Cyrix III
Table 17.
Cyrix III CPU DIR Values
CORE CL OCK T O B US CL OCK RAT IO 2.5 x 3.0 x 3.5 x 4.0 x 4.5 x 5.0 x 5.5 x 6.0 x 6.5 x 7.0 x 7.5 x
DIR0 84h 81h 85h 82h 86h 83h 87h 88h 8Ah 89h 8Bh
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3. Cyrix III Configuration Register Index Assignments
On-chip configuration registers are used to control the on-chip cache, system management mode and other Cyrix III unique features.
3.1 Accessing a Configuration Register
Access to the configuration registers is achieved by writing the index of the register to I/O port 22h. I/O port 23h is then used for data transfer. Each I/O port 23h data transfer must be preceded by an I/O port 22h register index selection, otherwise the second and later I/O port 23h operations are directed off-chip and produce external I/O cycles. Reads of I/O port 22h are always directed off-chip. Appendix D contains example code for accessing the Cyrix III configuration registers.
3.2 Cyrix III Configuration Register Index Assignments
The table on the following page lists the Cyrix III configuration register index assignments. After reset, configuration registers with indexes C0-CFh and FC-FFh are accessible. In order to prevent potential conflicts with other devices which may use ports 22 and 23h to access their registers, the remaining registers (indexes 00-BFh, D0-FBh) are accessible only if the MAPEN(3-0) bits in CCR3 are set to 1h. With MAPEN(3-0) set to 1h, any access to an index in the 00-FFh range does not create external I/O bus cycles. Registers with indexes C0-CFh, FC-FFh are accessible regardless of the state of the MAPEN bits. If the register index number is outside the C0-CFh or FE-FFh ranges, and MAPEN is set to 0h, external I/O bus cycles occur. The table on the next page lists the MAPEN values required to access each Cyrix III configuration register. The configuration registers are described in more detail in the following sections.
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Table 18.
R EGIST ER INDEX 00h-BFh C0h C1h C2h C3h E8h E9h EAh EBh C4h-C6h C7h-C9h CAh-CCh CDh-CFh D0h-D2h D3h-D5h D6h-D8h D9h-DBh A4h-A6h A7h-A9h AAh-ACh ADh-AFh D0h-D2h D6h-D8h DCh DDh DEh DFh E0h E1h E2h E3h DCh DDh DEh Reserved
Configuration Register Index Assignments
ACR ONYM -- CCR0 CCR1 CCR2 CCR3 CCR4 CCR5 CCR6 CCR7 ARR0 ARR1 ARR2 ARR3 ARR4 ARR5 ARR6 ARR7 ARR8 ARR9 ARRA ARRB ARRC ARRD RCR0 RCR1 RCR2 RCR3 RCR4 RCR5 RCR6 RCR7 RCR8 RCR9 RCRA -- 8 8 8 8 8 8 8 8 24 24 24 24 24 24 24 24 24 24 24 24 24 24 8 8 8 8 8 8 8 8 8 8 8 W IDTH (BITS) -- Don't care Don't care Don't care Don't care 1h 1h 1h 1h Don't care Don't care Don't care Don't care 1h 1h 1h 1h x01x x01x x01x x01x x01x x01x 1h 1h 1h 1h 1h 1h 1h 1h x01x x01x x01x MAPEN(3-0)
REGISTER NA ME
Configuration Control 0 Configuration Control 1 Configuration Control 2 Configuration Control 3 Configuration Control 4 Configuration Control 5 Configuration Control 6 Configuration Control 7 Address Region 0 Address Region 1 Address Region 2 Address Region 3 Address Region 4 Address Region 5 Address Region 6 Address Region 7 Address Region 8 Address Region 9 Address Region A Address Region B Address Region C Address Region D Region Configuration 0 Region Configuration 1 Region Configuration 2 Region Configuration 3 Region Configuration 4 Region Configuration 5 Region Configuration 6 Region Configuration 7 Region Configuration 8 Region Configuration 9 Region Configuration A
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Table 18.
DFh E0h E1h E4h-E7h EBh-FAh FBh FCh FDh FEh FFh 48h 49h 41h 20h
Configuration Register Index Assignments
RCRB RCRC RCRD -- -- DIR2 DIR3 DIR4 DIR0 DIR1 BCR1 BCR2 LCR1 TWR0 8 8 8 -- -- 8 8 8 8 8 8 8 8 8 x01x x01x x01x -- -- 1h 1h 1h Don't care Don't care 0100 0100 0100 0001
Region Configuration B Region Configuration C Region Configuration D Reserved Reserved Device Identification 2 Device Identification 3 Device Identification 4 Device Identification 0 Device Identification 1 Bus Configuration Register 1 Bus Configuration Register 2 L2 Configuration Register 1 Table Walk Register 0
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The Cyrix III configuration registers can be grouped into five areas:
· · · · ·
Configuration Control Registers (CCRs) Address Region Registers (ARRs) Region Control Registers (RCRs) Device Identification Registers (DIRs) Cache and Bus Configuration Registers (BCRs)
CCR bits independently control Cyrix III features. ARRs and RCRs define regions of memory with specific attributes. DIRs are used for CPU detection as discussed earlier in Chapter 3. All bits in the configuration registers are initialized to zero following reset unless specified otherwise. The appropriate configuration register bit settings vary depending on system design. Optimal settings recommended for a typical PC environment are discussed in Chapter 5.
3.3 Configuration Control Registers (CCR0-7)
There are seven CCRs in the Cyrix III which control the cache, power management and other unique features. The following paragraphs describe the CCRs and associated bit definitions in detail.
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3.3.1
Configuration Control Register 0 (CCR0)
Table 19.
B IT 7 Reserved BIT 6 Reserved
Configuration Control Register 0 (CCR0)
B IT 4 Reserved B IT 3 Reserved BIT 2 Reserved BIT 1 NC1 B IT 0 Reserved
B IT 5 Reserved
Table 20.
B IT N AME NC1 B IT N O. 1
CCR0 Bit Definitions
D ESCRIPT ION
If = 1, designates 640KBytes -1MByte address region as non-cacheable. If = 0, designates 640KBytes -1MByte address region as cacheable.
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3.3.2
Configuration Control Register 1 (CCR1)
Table 21.
B IT 7 SM3 B IT 6 Reserved BIT 5
Configuration Control Register 1 (CCR1)
B IT 4 Reserved B IT 3 Reserved BIT 2 Reserved B IT 1 Reserved B IT 0 Reserved
Reserved
Table 22.
B IT NAME SM3 B IT NO . 7
CCR1 Bit Definitions
D ESCR IPTION
If = 1, designates Address Region Register 3 as SMM address space.
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3.3.3
Configuration Control Register 2 (CCR2)
Table 23.
BIT 7 Reserved B IT 6 Reserved
Configuration Control Register 2 (CCR2)
BIT 4 WPR1 BIT 3 SUSP_HLT BIT 2 LOCK_NW B IT 1 Reserved BIT 0 Reserved
B IT 5 Reserved
Table 24.
B IT N AME WPR1 BIT N O. 4
CCR2 Bit Definitions
DESCRIPTION
If = 1, designates that any cacheable accesses in the 640 KBytes-1MByte address region are write-protected. With WPR1=1, any attempted write to this range will not update the internal cache. If = 1, execution of the HLT instruction causes the CPU to enter low power suspend mode. This bit should be used with caution since the CPU must recognize and service an INTR, NMI or SMI to exit the "HLT initiated" suspend mode. If = 1, the NW bit in CR0 becomes read only and the CPU ignores any writes to this bit.
SUSP_HLT
3
LOCK_NW
2
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3.3.4
Configuration Control Register 3 (CCR3)
Table 25.
B IT 7 B IT 6 MAPEN
Configuration Control Register 3 (CCR3)
BIT 4 BIT 3 Reserved BIT 2 Reserved BIT 1 NMI_EN B IT 0 SMI_LOCK
BIT 5
Table 26.
B IT N AME MAPEN NMI_EN SMI_LOCK BIT N O. 7-4 1 0
CCR3 Bit Definitions
D ESCRIPTION
Can be set to access various registers for read and write according to table 18. If = 1, NMI interrupt is recognized while in SMM. This bit should only be set while in SMM, after the appropriate NMI interrupt service routine has been setup. If = 1, the CPU prevents modification of the following SMM configuration bits, except when operating in an SMM service routine: CCR1 USE_SMI, SMAC, SM3 CCR3 NMI_EN ARR3 Starting address and block size. Once set, the SMI_LOCK bit can only be cleared by asserting the RESET pin.
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3.3.5
Configuration Control Register 4 (CCR4)
Table 27.
B IT 7 CPUID BIT 6 Reserved
Configuration Control Register 4 (CCR4)
B IT 5 BIT 4 Reserved BIT 3 Reserved B IT 2 Reserved B IT 1 Reserved B IT 0 Reserved
Reserved
Table 28.
B IT N AME CPUID BIT N O. 7
CCR4 Bit Definitions
DESCRIPTION
If = 1, bit 21 of the EFLAG register is write/readable and the CPUID instruction will execute normally. If = 0, bit 21 of the EFLAG register is not write/readable and the CPUID instruction is an invalid opcode.
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3.3.6
Configuration Control Register 5 (CCR5)
Table 29.
B IT 7 Reserved BIT 6 Reserved B IT 5
Configuration Control Register 5 (CCR5)
BIT 4 Reserved B IT 3 Reserved B IT 2 Reserved B IT 1 Reserved B IT 0 WT_ALLOC
ARREN
Table 30.
B IT N AME ARREN WT_ALLOC B IT NO . 5 0
CCR5 Bit Definitions
DESCRIPTION
If = 1, enables all Address Region Registers (ARRs). If clear, disables the ARR registers. If SM3 is set, ARR3 is enabled regardless of the ARREN setting. If = 1, new cache lines are allocated for both read misses and write misses. If = 0, new cache lines are only allocated on read misses.
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Configuration Control Register 6 (CCR6)
Table 31.
B IT 7 Reserved BIT 6 Reserved B IT 5
Configuration Control Register 6 (CCR6)
BIT 4 Reserved B IT 3 Reserved B IT 2 Reserved B IT 1 WP_ARR3 B IT 0 SMM_MODE
Reserved
Table 32.
B IT N AME WP_ARR3 B IT NO . 1
CCR6 Bit Definitions
DESCRIPTION
If = 1: Memory region defined by ARR3 is write protected when operating outside of SMM mode. If = 0: Disable write protection for memory region defined by ARR3. Reset State = 0.
SMM_MODE
0
If = 1: Enables Cyrix Enhanced SMM mode. If = 0: Disables Cyrix Enhanced SMM mode.
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3.3.8
Configuration Control Register 7 (CCR7)
Table 33.
B IT 7 Reserved BIT 6 Reserved
Configuration Control Register 7 (CCR7)
B IT 5 B IT 4 3DNOW_EN BIT 3 Reserved BIT 2 Reserved BIT 1 Reserved B IT 0 Reserved
Reserved
Table 34.
B IT N AME 3DNOW_EN B IT NO . 4
CCR7 Bit Definitions
DESCRIPTION
If = 1: 3DNOW instruction set is enabled If = 0: 3DNOW instruction set it disabled
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3.3.9
Table Walk Register 0 (TWR0)
Table 35.
B IT 7 Reserved BIT 6 Reserved B IT 5 Reserved
Table Walk Register 0 (TWR0)
B IT 4 BIT 3 Reserved BIT 2 Reserved BIT 1 Reserved B IT 0 Reserved
CACHE_TE
Table 36.
B IT N AME CACHE_TE B IT NO . 4
TWR0 Bit Definitions
DESCRIPTION
If = 1: Cache Page Table Entries and Directory Table Entries. This is a performance enhancement If = 0:Do not cache table entries. Performance will be less.
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3.4 Address Region Registers (ARR0-7)
The Address Region Registers (ARRs) are used to define up to eight memory address regions. Each ARR has three 8-bit registers associated with it which define the region starting address and block size. The Table "ARRx Index Assignments" below shows the general format for each ARR and lists the index assignments for the ARR's starting address and block size. The region starting address is defined by the upper 12 bits of the physical address. The region size is defined by the BSIZE(3-0) bits as shown in the Table "BSIZE (3-0) Bit Definitions" on the next page. The BIOS and/or its utilities should allow definition of all ARRs. There is one restriction when defining the address regions using the ARRs. The region starting address must be on a block size boundary. For example, a 128KByte block is allowed to have a starting address of 0KBytes, 128KBytes, 256KBytes, and so on.
Table 37.
ADD RESS REGION REGIST ER ARR0 ARR1 ARR2 ARR3 ARR4 ARR5 ARR6 ARR7 ARR8 ARR9 ARRA ARRB ARRC ARRD
ARRx Index Assignments
S TA RTING A DDRESS R EGION B LOC K S IZE A15-A12 B ITS (7-4) C6h C9h CCh CFh D2h D5h D8h DBh A6h A9h ACh AFh D2h D5h BSIZE(3-0) B IT S (3-0)
A31-A24 B ITS (7-0) C4h C7h CAh CDh D0h D3h D6h D9h A4h A7h AAh ADh D0h D3h
A23-A16 B ITS (7-0) C5h C8h CBh CEh D1h D4h D7h DAh A5h A8h ABh AEh D1h D4h
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Table 38.
BSIZE(3-0) 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh
BSIZE (3-0) Bit Definitions
ARR(0-6) R EGION S IZE Disabled 4 KBytes 8 KBytes 16 KBytes 32 KBytes 64 KBytes 128 KBytes 256 KBytes 512 KBytes 1 MByte 2 MBytes 4 MBytes 8 MBytes 16 MBytes 32 MBytes 4 GBytes ARR(7-D) R EGION S IZE Disabled 256 KBytes 512 KBytes 1 MByte 2 MBytes 4 MBytes 8 MBytes 16 MBytes 32 MBytes 64 MBytes 128 MBytes 256 MBytes 512 MBytes 1 GBytes 2 GBytes 4 GBytes
3.5 Region Control Registers (RCR0-D)
The RCRs are used to define attributes, or characteristics, for each of the regions defined by the ARRs. Each ARR has a corresponding RCR with the general format shown below. New to the Cyrix III is the Invert Region feature. This feature is controlled by the INV_RGN bit of the Region Control Registers. If the INV_RGN bit is set, the controls specified in the RCR (RCD, WT, WG, WP) will be applied to all memory addresses outside the region specified in the corresponding ARR. If the INV_RGN bit is cleared, the Cyrix III functions identically to the 6x86 and MII (the controls specified in the RCR will be applied to all memory addresses inside the region specified by the corresponding ARR).
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The INV_RGN bit is defined for RCR(0-6) only. 6x86 Weak Write Ordering and Local Bus Access features have been eliminated on the Cyrix III. Therefore, bit 5 and bit 1 are reserved bits for the Cyrix III.
Table 39.
BIT 7 Reserved BIT 6 INV_RGN BIT 5 Reserved
RCR Bit Definitions
BIT 4 WT BIT 3 WG BIT 2 WP BIT 1 Reserved BIT 0 RCD/RCE
Note: RCD is defined for RCR0-RCR6. and RCR8-RCRD. RCE is defined for RCR7 only.
Table 40.
B IT N AME RCD RCE WP WG WT INV_RGN B IT N O. 0 0 2 3 4 6
RCR Bit Definitions
D ESCRIPTION
Applicable to RCR(0-6) only. If set, the address region specified by the corresponding ARR is non-cacheable. Applicable to RCR7 only. If set, the address region specified by ARR7 is cacheable and implies that address space outside of the region specified by ARR7 is non-cacheable. If set, write protect is enabled for the corresponding region. If set, write gathering is enabled for the corresponding region. If set, write through caching is enabled for the corresponding region. Applicable to RCR(0-6) only. If set, apply controls specified in RCR to all memory addresses outside the region specified in the corresponding ARR.
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Detailed Description of RCR Attributes
Region Cache Disable (RCD)
Setting RCD=1 defines the corresponding address region as non-cacheable. RCD prevents caching of any access within the specified region. Additionally, RCD implies that high performance features are disabled for accesses within the specified address region.
Region Cache Enable (RCE)
Setting RCE=1 defines the corresponding address region as cacheable. RCE is applicable to ARR7 only. RCE in combination with ARR7, is intended to define the Main Memory Region. All memory outside ARR7 is non-cacheable when RCE is set. This is intended to define all unused memory space as non-cacheable.
Write Protect (WP)
Setting WP=1 enables write protect for the corresponding address region. With WP enabled, The memory region is treated as read-only when cached into the cpu cache. During a cache-hit write, the cache will not be modified. The data will still be written through to main memory however, and it is up to the chipset memory controller to ignore the main memory write if necessary. This is useful for caching of shadowed ROM data.
Write Gathering (WG)
Setting WG=1 enables write gathering for the corresponding address region. With WG enabled, multiple byte, word or dword writes to sequential addresses that would normally occur as individual write cycles are combined and issued as a single write cycle. WG improves bus utilization and should be used for memory regions that are not sensitive to the "gathering." WG can be enabled for both cacheable and non-cacheable regions.
Write Through (WT)
Setting WT=1 defines the corresponding address region as write-through instead of write-back. Any system ROM that is allowed to be cached by the processor should be defined as write-through. Note that only one of these properties may be set per region. These are mutually exclusive memory type definitions, not properties that can be combines. For example WP basically means read only, thus write gathering and write though are irrelevant. WT means update main memory immediately upon writes, thus this excludes write gathering. Write gathering also defines when to write out data onto the bus, thus violating normal write back cache mode.
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3.5.2
Attributes for Accesses Outside Defined Regions
If an address is accessed that is not in a region defined by the ARRs and ARR7 is defined with RCE=1, the following conditions apply:
· The memory access is not cached. · Writes are not gathered. · Strong write ordering occurs.
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3.5.3
Attributes for Accesses in Overlapped Regions
If two defined address regions overlap (including NC1 and LBR1) and conflicting attributes are specified, the following attributes take precedence:
· · · ·
Write-back is disabled. Writes are not gathered. Strong write ordering occurs. The overlapping regions are non-cacheable.
Since the CCR0 bit NC1 affects cacheability, a potential exists for conflict with the ARR7 main memory region which also affects cacheability. This overlap in address regions causes a conflict in cacheability. In this case, NC1 takes precedence over the ARR7/RCE setting because non-cacheability always takes precedence. For example, for the following settings:
· NC1=1 · ARR7 = 0-16 MBytes · RCR7 bit RCE = 1
The Cyrix III caches accesses as shown in the table below.
Table 41.
A DDRESS R EGION 0 to 640 KBytes 640 KBytes- 1 MByte 1 MByte - 16 MBytes 16 MBytes - 4 GBytes
Cacheability for Example 1
C ACHEABLE Yes No Yes No C OM MEN TS ARR7/RCE setting. NC1 takes precedence over ARR7/ RCE setting. ARR7/RCE setting. Default setting.
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3.6 BIOS Core-to-Bus Clock Ratio Configuration Registers
Index: Default Value: Access: MAPEN:
BIT 7 6 5:4 3:0
48h Read/Write 0100b
N AME HOTRST_TRIGGERED Reserved. BSEL[1- 0] BIOS_CLKRATIO[3-0] BITS (3:0) 4h 1h 5h 2h 6h 3h 7h 8h Ah 9h Bh D ESCRIPTION A read/write bit used to indicate to the BIOS whether hot reset has been triggered or not. Default value is 0. 0 Indicate the P6 bus speed. Core-to-bus clock ratio as described below. C LOCK R ATIO 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5
Index: Default Value: Access: MAPEN:
BIT 7:1 0
49h Read/Write 0100b
N AME Reserved BIOS_HOTRESET Writing a 1 to this bit will start the internal reset sequence to the PLL and load the BIOS_CLKRATIO(3-0) value to the PLL. D ESCRIPTION
These registers may be used for motherboards that do not have jumpers for selecting the clock ratios. The following flowchart illustrates the procedure to set the clock multiplier through BIOS.
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Yes Is Index register 48h bit(7) set to 1?
No Program CCR2 bit(3) to 1 to enable suspend on HALT. Program index register 48h bit(3:0) to the desired clock ratio, and set bit(7) to 1 to remember that clock ratio has been programmed.
Program index register 49h bit(0) to 1 to initiate the hot reset sequence. This bit will be reset automatically upon the deassertion of hot reset.
Execute a HALT Instruction
Continue Boot Up Procedure
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3.7 L2 Cache Control
Index: Default Value: Access: MAPEN:
BIT 3
41h Read/Write 0100b
N AME DESCRIPTION
L2_WT
L2 Write Through. All L1 evictions (cache line writes) are not stored in the L2. If the evicted cache line is modified, the cache line is written to the P6 bus. If the cache line is in the shared or exclusive state, it is discarded. L2 Enable. All L2 accesses (reads, writes or snoops) will miss the L2. An eviction from the L1 (cache line write) will not update the L2. A WBINV instruction must be generated when changing this bit from a 1 to a 0. The POR value of this bit is 0.
2
L2_ENABLE
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4. PC Memory Model
The table below defines the allowable attributes for a typical PC memory model. Actual recommended configuration register settings for a typical PC system are listed in AppendixF.
Table 42.
ADDRESS SPACE DOS Area Video Buffer Video ROM Expansion Card/ROM Area System ROM Extended Memory Unused/PCI MMIO ADDRESS RANGE 0-9 FFFFh A 0000-B FFFFh C 0000-C 7FFFh C 8000h-D FFFFh CACHEABLE Yes No Yes No
PC Memory Model
WRITE PROTECTED No No Yes No WRITE GATHERED No Yes No No WRITETHROUGH No No No No Note 1 Note 2 NOTES
E 0000h-F FFFFh 10 0000hTop of Main Memory Top of Main Memory-FFFF FFFFh
Yes Yes
Yes No
No Yes
No No
Note 2
No
No
No
No
Note 3
Notes 1: Video Buffer Area A non-cacheable region must be used to enforce strong cycle ordering in this area and to prevent caching of Video RAM. The Video RAM area is sensitive to bus cycle ordering. The VGA controller can perform logical operations which depend on strong cycle ordering (found in Windows 3.1 code). To guarantee that the Cyrix III performs strong cycle ordering, a non-cacheable area must be established to cover the Video RAM area. Video performance is greatly enhanced by gathering writes to Video RAM. For example, video performance benchmarks have been found to use REP STOSW instructions that would normally execute as a series of sequential 16-bit write cycles. With WG enabled, groups of four 16-bit write cycles are reduced to a single 64-bit write cycle.
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Note 2: Video ROM and System ROM Caching of the Video and System ROM areas is permitted, but is normally non-cacheable because NC1 is set. If these areas are cached, they must be cached as write-through regions. Cyrix III system benchmarking in a Windows environment has shown no benefit to caching these ROM areas. Therefore, it is recommended that these areas be set as non-cacheable using the NC1 bit in CCR0. Note 3: Top of Main Memory-FFFF FFFFh (Unused/PCI Memory Space) Unused/PCI Memory Space immediately above physical main memory must be defined as non-cacheable to ensure proper operation of memory sizing software routines and to guarantee strong cycle ordering. Memory discovery routines must occur with cache disabled to prevent read sourcing from the write buffers. Also, PCI memory mapped I/O cards that may exist in this address region may contain control registers or FIFOs that depend on strong cycle ordering. The appropriate non-cacheable region must be established using ARR7. For example, if 32 MBytes (000 0000h-1FF FFFFh) are installed in the system, a non-cacheable region must begin at the 32 MByte boundary (200 0000h) and extend through the top of the address space (FFFF FFFFh). This is accomplished by using ARR7 (Base = 0000 0000h, BSize = 32 MBytes) in combination with RCE=1.
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4.1 4.1.1
General Recommendations
Main Memory
Memory discovery routines should always be executed with the L1 cache disabled. By default, L1 caching is globally disabled following reset because the CD bit in Control Register 0 (CR0) is set. Always ensure the L1 cache is disabled by setting the CD bit in CR0 or by programming an ARR to "4 GByte cache disabled" before executing the memory discovery routine. Once BIOS completes memory discovery, ARR7 should be programmed with a base address of 000 0000h and with a "Size" equal to the amount of main memory that was detected. The intent of ARR7 is to define a cacheable region for main memory and simultaneously define unused/PCI space as non-cacheable. More restrictive regions are intended to overlay the 640k to 1MByte area. Failure to program ARR7 with the correct amount of main memory can result in:
· Incorrect memory sizing by the operating system eventually resulting in failure, · PCI devices not working correctly or causing the system to hang, · Low performance if ARR7 is programmed with a smaller size than the actual amount of memory.
If the granularity selection in ARR7 does not accommodate the exact size of main memory, unused ARRs can be used to fill-in as non-cacheable regions. All unused/PCI memory space must always be set as noncacheable.
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4.1.2
BIOS Creation Utilities
BIOS creation utilities or setup screens must have the capability to easily define and modify the contents of the Cyrix III configuration registers. This allows OEMs and integrators to easily configure these register settings with the values appropriate for their system design.
4.2 Recommended Bit Settings
4.2.1 NC1
The NC1 bit in CCR0 controls the predefined non-cacheable region from 640K to 1MByte. The 640K to 1MByte region should be non-cacheable to prevent L1 caching of expansion cards using memory mapped I/ O (MMIO). Setting NC1 also implies that the video BIOS and system BIOS are non-cacheable. Experiments with both the Cyrix III and Pentium CPUs have shown that performance is largely unchanged whether the video BIOS and system BIOS was cached or not. This assumes that a modern operating system was used and that the measurements are taken with a recent benchmark applications, such as WinStone95. Recommended setting: NC1 = 1
4.2.2
LOCK_NW
Once set, LOCK_NW prohibits software from changing the NW bit in CR0. Since the definition of the NW bit is the same for both the Cyrix III and the Pentium, it is not necessary to set this bit. Recommended setting: LOCK_NW = 0
4.2.3
WPR1
WPR1 forces cacheable accesses in the 640k to 1MByte address region to be write-protected. If NC1 is set (recommended setting), all caching is disabled from 640k to 1MByte and WPR1 is not required. However, if ROM areas within the 640k-1MByte address region are cached, WPR1 should be set to protect against errant self-modifying code. Recommended setting: WPR1 = 0 unless ROM areas are cached
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4.2.4
MAPEN
When set to 1h, the MAPEN bits allow access to all Cyrix III configuration registers including indices outside the C0h-CFh and FCh-FFh ranges. MAPEN should be set to 1h only to access specific configuration registers and then should be cleared immediately after the access is complete. Recommended setting: MAPEN(3-0) = 0 except for specific configuration register accesses
4.2.5
CPUID
When set, the CPUID bit enables the CPUID instruction. By default, the CPUID instruction is enabled (CPUID = 1). When enabled, the CPUID opcode is enabled and the CPUID bit in the EFLAGS can be modified. The CPUID instruction can then be called to inspect the type of CPU present. When the CPUID instruction is disabled (CPUID = 0), the CPUID opcode 0FA2 causes an invalid opcode exception. Additionally, the CPUID bit in the EFLAGS register cannot be modified by software. Recommended setting: CPUID = 1
4.2.6
WT_ALLOC
Write Allocate (WT_ALLOC) allows L1 cache write misses to cause a cache line allocation. This feature improves the L1 cache hit rate resulting in higher performance. Especially useful for Windows applications. Recommended setting: WT_ALLOC = 1
4.2.7
ARREN
The ARREN bit enables or disables all eight ARRs. When ARREN is cleared (default), the ARRs can be safely programmed. Most systems will need to use at least one address region register (ARR). Therefore, ARREN should always be set after the ARRs and RCRs have been initialized. Recommended setting: ARREN = 1 after initializing ARR0-ARR7, RCR0-RCR7
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4.2.8
ARR7 and RCR7
Address Region 7 (ARR7) defines the Main Memory Region (MMR). This region specifies the amount of cacheable main memory and it's attributes. Once BIOS completes memory discovery, ARR7 should be programmed with a base address of 000 0000h and with a "Size" equal to the amount of main memory installed in the system. Memory accesses outside of this region are defined as non-cacheable to ensure compatibility with PCI devices. Recommended settings: ARR7 Base Addr= 0000 0000h ARR7 Block Size= amount of main memory RCR7 RCE =0 RCR7 WL =0 RCR7 WG =1 RCR7 WT =0 If the granularity selection in ARR7 does not accommodate the exact size of main memory, unused ARRs can be used to fill-in as non-cacheable regions (RCD = 1) as shown in the table below. All unused/PCI memory space must always be set as non-cacheable. Table 43.
MEM SIZE (MB) 8 16 24 32 40 48 64 72 80 96 128 160 192 256 ARR7 BASE (HEX) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIZE (MB) 8 16 32 32 64 64 64 128 128 128 128 256 256 256 0E00 0000 0E00 0000 32 32 0C00 0000 0C00 0000 32 32 0A00 0000 32 0600 0000 0600 0000 0600 0000 32 32 32 0500 0000 0500 0000 16 16 0480 0000 8 0300 0000 0300 0000 16 16 0280 0000 8 0180 0000 8 BASE (HEX)
ARR Settings for Various Main Memory Sizes
ARR6 SIZE (MB) BASE (HEX) ARR5 SIZE (MB) BASE (HEX) ARR4 SIZE (MB)
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4.2.9
Regions above Main Memory
Memory regions above main memory such as memory mapped i/o and write gathering or write combining regions for video memory can be setup using ARRs as well. The memory map table below gives an example of how to setup entire memory up to 4G to include physical memory, i/o space, write gathering regions for video, and uncacheable unused space.
ADDRESS SPACE Main Memory Memory mapped i/o space Write gathering region
ARR ARR7 ARR8 ARR9
START 0 Physical Memory i/o space top Write Gathering region top
SIZE Physical Memory i/o space size Write Gathering region size 4G minus top of Write Gathering Region
RCR BIT(7) RCD/E 1 1 0
RCR BIT(2) WP 0 0 0
RCR BIT(3) WG 0 0 1
RCR BIT(4) WT 0 0 0
Uncacheable region
ARRA
1
0
0
0
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4.2.10 SMM Features
The Cyrix III supports SMM mode through the use of the SMI# and SMIACT# pins, and a dedicated memory region for the SMM address space. SMM features must be enabled prior to servicing any SMI interrupts. The following paragraphs describe each of the SMM features and recommended settings.
SM3 and ARR3
Address Region Register 3 (ARR3) can be used to define the System Management Address Region (SMAR). Systems that use SMM features must use ARR3 to establish a base and limit for the SMM address space. Only ARR3 can be used to establish the SMM region. Typically, SMAR overlaps normal address space. RCR3 defines the attributes for both the SMM address region and the normal address space. If SMAR overlaps main memory, write gathering should be enabled for ARR3. If SMAR overlaps video memory, ARR3 should be set as non-cacheable and write gathering should be enabled.
NMI_EN
The NMI_EN bit allows NMI interrupts to occur within an SMI service routine. If this feature is enabled, the SMI service routine must guarantee that the IDT is initialized properly to allow the NMI to be serviced. Most systems do not require this feature.
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SMI_LOCK
Once the SMM features are initialized in the configuration registers, they can be permanently locked using the SMI_LOCK bit. Locking the SMM related bits and registers prevents applications from tampering with these settings. Even if SMM is not implemented, setting SMI_LOCK in combination with SMAC=0 prevents software SMIs from occurring. Once SMI_LOCK is set, it can only be cleared by a processor RESET. Consequently, setting SMI_LOCK makes system/BIOS/SMM debugging difficult. To alleviate this problem, SMI_LOCK must be implemented as a user selectable "Secure SMI (enable/disable)" feature in CMOS setup. If SMI_LOCK is not user selectable, it is recommended that SMI_LOCK = 0 to allow for system debug. Suggested settings for systems not using SMM:
SM3 ARR3 SMI_LOCK NMI_EN
=0 = may be used as normal address region register =0 =0
Suggested settings for systems using SMM:
SM3 ARR3 Base Addr ARR3 Block Size SMI_LOCK NMI_EN
=1 = as required = as required =0 =0
4.2.11 Power Management Features SUSP_HALT
Suspend on Halt (SUSP_HLT) permits the CPU to enter a low power suspend mode when a HLT instruction is executed. Although this provides some power management capability, it is not optimal.
Suggested setting: SUSP_HALT =1
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5. Model Specific Registers
The Cyrix III contains four model specific registers (MSR0 - MSR3). These 64-bit registers are listed in the table below. Table 44. Machine Specific Register
MSR ADDRESS 10h 11h 12h 13h REGISTER MSR10 MSR11 MSR12 MSR13
REGISTER DESCRIPTION Time Stamp Counter (TSC) Counter Event Selection and Control Register Performance Counter #0 Performance Counter #1
The MSR registers can be read using the RDMSR instruction, opcode 0F32h. During an MSR register read, the contents of the particular MSR register, specified by the ECX register, is loaded into the EDX:EAX registers. The MSR registers can be written using the WRMSR instruction, opcode 0F30h. During a MSR register write the contents of EDX:EAX are loaded into the MSR register specified in the ECX register. The RDMSR and WRMSR instructions are privileged instructions.
5.1 Time Stamp Counter
The Time Stamp Counter (TSC) Register (MSR10) is a 64-bit counter that counts the internal CPU clock cycles since the last reset. The TSC uses a continuous CPU core clock and will continue to count clock cycles even when the Cyrix III is suspend mode or shutdown. The TSC can be accessed using the RDMSR and WRMSR instructions. In addition, the TSC can be read using the RDTSC instruction, opcode 0F31h. The RDTSC instruction loads the contents of the TSC into EDX:EAX. The use of the RDTSC instruction is restricted by the Time Stamp Disable, (TSD) flag in CR4. When the TSD flag is 0, the RDTSC instruction can be executed at any privilege level. When the TSD flag is 1, the RDTSC instruction can only be executed at privilege level 0.
5.2 Performance Monitoring
Performance monitoring allows counting of over a hundred different event occurrences and durations. Two 48-bit counters are used: Performance Monitor Counter 0 and Performance Monitor Counter 1. These two performance monitor counters are controlled by the Counter Event Control Register (MSR11). The perfor-
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mance monitor counters use a continuous CPU core clock and will continue to count clock cycles even when the Cyrix III is in suspend mode or shutdown.
5.3 Performance Monitoring Counters 1 and 2
The 48-bit Performance Monitoring Counters (PMC) Registers (MSR12, MSR13) count events as specified by the counter event control register. The PMCs can be accessed by the RDMSR and WRMSR instructions. In addition, the PMCs can be read by the RDPMC instruction, opcode 0F33h. The RDPMC instruction loads the contents of the PMC register specified in the ECX register into EDX:EAX. The use of RDPMC instructions is restricted by the Performance Monitoring Counter Enable, (PCE) flag in C4. When the PCE flag is set to 1, the RDPMC instruction can be executed at any privilege level. When the PCE flag is 0, the RDPMC instruction can only be executed at privilege level 0.
5.4 Counter Event Control Register
Register MSR 11h controls the two internal counters, #0 and #1. The events to be counted have been chosen based on the micro-architecture of the Cyrix III processor. The control register for the two event counters is described on page 46.
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5.5
5.5.1
Performance Monitor Control Counter Type Control
The Counter Type bit determines whether the counter will count clocks or events. When counting clocks the counter operates as a timer.
5.5.2
CPL Control
The Current Privilege Level (CPL) can be used to determine if the counters are enabled. The CP02 bit in the MSR 11 register enables counting when the CPL is less than three, and the CP03 bit enables counting when CPL is equal to three. If both bits are set, counting is not dependent on the CPL level; if neither bit is set, counting is disabled.
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2 6 T C 1 *
2 5 P M 1
2 4 C T 1
2 3 C P 1 3
2 2 C P 1 2
21
16
15
10
9
8
7
6
5
0
TC1*
RESERVED
T C 0 *
P M 0
C T 0
C P 0 3
C P 0 2
TC0*
*Note: Split Fields
Table 45.
Counter Event Control Register
Table 46.
BIT POSITION 25 24 NAME RSV CT1
Counter Event Control Register Bit Definitions
DESCRIPTION Reserved Counter #1 Counter Type If = 1: Count clock cycles If = 0: Count events (reset state). Counter #1 CPL 3 Enable If = 1: Enable counting when CPL=3. If = 0: Disable counting when CPL=3. (reset state) Counter #1 CPL Less Than 3 Enable If = 1: Enable counting when CPL < 3. If = 0: Disable counting when CPL < 3. (reset state) Counter #1 Event Type Reset state = 0 Reserved Counter #0 Counter Type If = 1: Count clock cycles If = 0: Count events (reset state). Counter #0 CPL 3 Enable If = 1: Enable counting when CPL=3. If = 0: Disable counting when CPL=3. (reset state) Counter #0 CPL Less Than 3 Enable If = 1: Enable counting when CPL < 3. If = 0: Disable counting when CPL < 3. (reset state) Counter #0 Event Type Reset state = 0
23
CP13
22
CP12
26, 21 - 16 9 8
TC1(5-0) RSV CT0
7
CP03
6
CP02
10, 5 - 0
TC0(5-0)
Note: Bits 10 - 15 are reserved.
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5.5.3
Event Type and Description
The events that can be counted by the performance monitoring counters are listed in Figure 47. Each of the 127 event types is assigned an event number. A particular event number to be counted is placed in one of the MSR 11 Event Type fields. There is a separate field for counter #0 and #1. The events are divided into two groups. The occurrence type events and duration type events. The occurrence type events, such as hardware interrupts, are counted as single events. The duration type events such as "clock while bus cycles are in progress" count the number of clock cycles that occur during the event. During occurrence type events, the PM pins are configured to indicate the counter has incremented The PM pins will then assert every time the counter increments in regards to an occurrence event. Under the same PM control, for a duration event the PM pin will stay asserted for the duration of the event.
Table 47.
NUMBER 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h COUNTER 0 yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes COUNTER 1 yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes
Event Type Register
DESCRIPTION TYPE Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence Occurrence
Data Reads Data Writes Data TLB Misses Cache Misses: Data Reads Cache Misses: Data Writes Data Writes that hit on Modified or Exclusive Liens Data Cache Lines Written Back External Inquiries External Inquires that hit Memory Accesses in both pipes Cache Bank conflicts Misaligned data references Instruction Fetch Requests L2 TLB Code Misses Cache Misses: Instruction Fetch Any Segment Register Load Reserved Reserved Any Branch BTB hits Taken Branches or BTB hits Pipeline Flushes Instructions executed in both pipes
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Table 47.
NUMBER 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Bh 2Bh 2Dh 2Dh 2Eh 2Fh 2Fh 30h 31h 32h 32h 33h 34h 34h 35h 35h 36 36 37 COUNTER 0 yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes no yes no no yes no yes yes yes no no yes no yes no yes no yes COUNTER 1 yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes no yes no yes yes no yes no no no yes yes no yes no yes no yes no
Event Type Register
DESCRIPTION TYPE Occurrence Duration Duration Duration
Instructions executed in Y pipe Clocks while bus cycles