Text preview for : cyr3_board.pdf part of VIA Cyrix III Application Note 127
Cyrix III CPU MotherBoard Design Considerations
Back to : cyr3_board.pdf | Home
Application Note 127 Cyrix III CPU MotherBoard Design Considerations
Cyrix Processors
REVISION HISTORY
Date 5/20/99 4/5/99 Version 1.0 0.54 Revision Added Diagrams Page 5, Table 1, Pin AK30 Description. Changed description. Page 5, Table 1, Moved third column and changed heading. Other minor editing on pages 7, 8, 9,and 13 . Typo Page 5, AK30 pin BSEL1 changed to 1 = 133 MHz, 0 =100 MHz Changed MXs processor name to Cyrix III. Corrected typos. Added paragraphs to pages 4, 7, 8 and 9 Renamed document to include the word "Considerations" Renamed document to better reflect the content. Repaired Table 1-4. BSEL0 and BSEL1 columns were reversed. Changed BSEL66# to BSEL0, Changed BSEL133# to BSEL1. BSEL1 now requires pull-down 10K resistor instead of 200 ohm pull-up resistor. Pins now listed in Table 1-2. Bus speed signals redefined in Table 1-4. Initial Version C:\documentation\joshua\appnotes\cIII_board.fm
4/2/99 3/22/99 3/15/99 3/12/99 3/11/99 2/26/99 2/26/99
0.53 0.52 0.51 0.5 0.4 0.3 0.2
2/25/99
0.1
Application Note 127
Cyrix III Board Design Considerations and AC/DC Specifications
1.
Introduction
The Cyrix III is the next generation processor from Cyrix. This application note describes board design considerations unique to the Cyrix III processor. In this document, pin differences are described and design considerations are discussed. Also the AC/DC Specifications are presented to a aid in proper timing design. The Cyrix III CPU is designed to be compatible with the Intel Celeron CPU. It is a socket 370 compatible processor and thus is intended to work with the common Socket 370 motherboards. There are however some differences between the Cyrix III as the Intel Celeron that impact motherboard design.
Cyrix III Board Design Considerations and AC/DC Specifications
There are four major differences between the Cyrix III and Celeron CPUs that are important to motherboard designers: 1) Core voltages: the Cyrix III operates at 2.2 volts and the Celeron operates at 2.0 volts. It thus requires the VID4 pin to be tied to cpu and VR. 2) Bus speed: the Cyrix III can run with a bus at high as 133 MHz bus whereas the Celeron can run with a bus as high as 100 MHz. 3) Clock multiplier: the Cyrix III built in default clock multiplier can be changed (either by jumpers or by BIOS), whereas the Celeron has a inflexible built-in clock multiplier. 4) BIOS update: BIOS needs to be programmed to identify Cyrix III cpu and set up all cpu registers. Performance Rating must be added to CPU name.
Operating the Cyrix III processor at 100 MHz and 133 MHz bus speeds requires careful board design. Signal timing analysis and signal integrity analysis must be done to ensure reliable operation. Factors such as clock skew, board and connector parasitics, and signal overshoot and ringback must be considered. Refer to 100MHz GTL+ Layout Guidelines (Intel document 243330-001) and Cyrix Application Notes 101 and 113 for implementation suggestions.
4
Application Note 127 Cyrix III Board Design and AC/DC Specifications
2.
PPGA 370 Package Pinout Differences
The Cyrix III processor has some advanced features which are not supported by the Intel® CeleronTM processor. Refer to the Cyrix III Databook chapter 5 for information on pin numbering and package footprint. Table 1 lists the pins that are defined differently for the Cyrix III and Celeron processors.
Table 1. Cyrix III and Intel Celeron Pin Differences
PINS AK36 CYRIX III SIGNAL VID[4] CELERO N SIGNAL GND TYP E O DES CRIP TIO N Voltage ID bit 4. Used by Cyrix III when signaling 2.2 V operation (VID[4-0] = 11101). Connecting AK36 to the voltage regulator will be compatible with both Cyrix III and Celeron since VID4 will be grounded by Celeron. Used with BSEL0 to select system bus frequency. This is legacy Cyrix III pin. New Celeron has defined a different pin for its BSEL1 signal, which Cyrix III also supports. Motherboard may use either pin for Cyrix III. AK30 and AJ31 are tied together internally to Cyrix III to be compatible with both legacy Cyrix III and new Celeron boards. When low, Cyrix III samples clock multiplier pins from jumpers, when high external jumpers are ignored and default clock multiplier is selected.
AK30
BSEL1
Reserved
I
AJ31
BSEL1
BSEL1
I
AB2
EXTRATIOPIN#
Vdd
I
The following signals are not supported by Cyrix III, but may be connected the same as Celeron. C35, E35 Reserved BPM[1-0]# I/O Output driven by Celeron to indicate the status of breakpoints and programmable counters used for monitoring processor performance. AE35 Reserved IERR# O Asserted by Celeron as a result of an internal error. A35 J37 Reserved Reserved PRDY# PREQ# O I Probe ready. This output signal is used to determines Celeron debug readiness and is not supported. Probe request. This input signal is used by Intel debug tools to request debug operation of the Celeron processor. Thermal trip. Output from the Celeron processor to signal severe over-temperature operation. The Cyrix III CPU always drives this signal high.
AH28
Reserved
THERMTRIP#
I
Application Note 127 Cyrix III Board Design and AC/DC Specifications
5
Cyrix III Board Design Considerations and AC/DC Specifications
3.
Voltage ID Signaling
The Cyrix III processor uses a 5-pin VID bus to signal its core voltage requirement as shown below: The Cyrix III CPU currently operates at 2.2 volts. The Intel Celeron currently operates at 2.0 volts. Due to the voltage regulator protocol, Cyrix III CPU requires an additional voltage identification signal--VID4.
Table 2. Core Voltage Requirement Bus Signaling
VID[4] L L L L L L H H VID[3] L L L L L L H H VID[2] H H L L L L H H VID[1] L L H H L L H L VID[0] H L H L H L L H VDDCO RE 1.80 V 1.85 V 1.90 V 1.95 V 2.00 V 2.05 V 2.10 V 2.20 V
NOTES: L = processor pin connected to GND. H = open on processor. The board must provide pull-up resistors to 2.5 V on VID[4-0]. The VID encodings are the same as for Celeron for voltages at or below 2.05 V. All other VID encodings are reserved.
The Cyrix III expands the VID bus by defining pin AK36 as VID4. Pin AK36 is defined as GND on the Celeron processor. By connecting the AK36 CPU pin to the VID4 voltage-regulator input pin makes the motherboard compatible with both Cyrix III and Intel Celeron processors. The following schematic diagrams explain how to make a standard socket 370 motherboard compatible with the Cyrix III cpu.
6
Application Note 127 Cyrix III Board Design and AC/DC Specifications
Figure 3.1: VID4 Signal Implementation
Celeron Only Circuit
VID1 VID2
VID1 VID2 VID3 VID4 VID5 Vout 2.0v
Celeron
VID3 VID4
VR
Celeron and Cyrix III Compatible Circuit VID1 VID2 VID1 VID2 VID3 VID4 Vout VID5 2.0v / 2.2v
Celeron or Cyrix III
VID3 VID4 VID5 (ak36)
VR
*ak36 is VID4 for Cyrix III, and GND for Celeron Note: VID pins are open-drain cmos meaning the motherboard must provide pullups to Vdd_cmos on all VID signals.
Application Note 127 Cyrix III Board Design and AC/DC Specifications
7
Cyrix III Board Design Considerations and AC/DC Specifications
4.
Bus Speed Signaling
The Cyrix III processor supports 66 MHz, 100 MHz and 133 MHz bus frequencies through the use of BSEL0 and BSEL1. The CPU must be informed of the bus frequency in order to properly generate its internal clocks and to tune its I/O performance. Bus speed signaling is defined in the following table:
Table 3. Speed Bus Signaling
BSEL1 L L H H BSEL0 L H H L BUS FREQ UENCY 66 MHz 100 MHz 133 MHz Reserved
The Celeron CPU drives the clock chip with the signal BSEL# instead of BSEL0 and BSEL1. The BSEL# output signal (pin AJ33) directs the clock chip to generate either a 66 or 100 MHz bus clock frequency. Almost all motherboards have a provision to override the BSEL# signal with a jumper selection. The flexible Cyrix III CPU supplies two input signals, BSEL0 (pin AJ33) and BSEL1 (pin AK30), allowing the selection of up to four different bus speeds. Since these signals are inputs when using the Cyrix III, two motherboard jumpers may be used to select the correct bus speed. When no jumpers are employed, the Cyrix III will drive the clock chip to the Cyrix III default bus speed. The Celeron BSEL# (pin AJ33) is defined on the Cyrix III CPU as BSEL0. The Celeron reserved pin (AK30) is defined on the Cyrix III as BSEL1. IMPORTANT: The new Celeron Specification defines its own BSEL1 pin which is pin AJ31. To be compatible, Cyrix III connects AJ31 to AK30 internally to the cpu. So the motherboard may use either pin as BSEL1. The only problem occurs when a legacy Celeron (no BSEL1 defined) is updated for Cyrix III (BSEL1=AK30). Since old celeron defines AJ31 as GND (BSEL1 in new celeron), if GND is connected to AJ31 and BSEL1 is connected to AK30, then BSEL1 will be grounded through the cpu. This will disable 133 Mhz. (66 and 100 Mhz will work fine). If this type of board wants to run 133 Mhz, then AJ31 should be disconnected, or else use I2C to program clock chip to 133 Mhz. To make a motherboard compatible for both Celeron and the Cyrix III, connect the BSEL0 pins on the clock chip and CPU together. Do the same for the BSEL1 pins. Also connect each line to a jumper, so that the lines can be jumpered high or low. JUMPERLESS: If no jumpers are used on the BSEL lines, Cyrix III defaults to its proper bus speed, but then the BIOS may use I2C to program the clock chip to any Mhz, providing a jumperless solution.
8
Application Note 127 Cyrix III Board Design and AC/DC Specifications
Figure 4.1: BSEL Signal Implementation
Celeron Only Circuit
BSEL
sel0 sel1
Celeron
CLK
66/100
Clock Generator
Celeron and Cyrix III Compatible Circuit 1kohm * BSEL0 1kohm * sel0
Celeron or Cyrix III
BSEL1
sel1 CLK 66/100/133
Clock Generator
*1kohm pullup to Vcc_cmos, and jumpers to GND are required for user setting.
Application Note 127 Cyrix III Board Design and AC/DC Specifications
9
Cyrix III Board Design Considerations and AC/DC Specifications
5.
CPU Core Clock Ratio Signaling
Like the Intel Celeron processor, the Cyrix III processor has a built in clock multiplier, but Cyrix III can also use the original Pentium II method for setting the core clock ratio to override the built in value. Cyrix III samples NMI, INTR, A20M# and IGNNE# while RESET# is asserted (low) and latches the values at the rising edge of RESET#. These signals must be stable for 1 ms prior to the rising edge of RESET# to ensure proper operation. This solution requires four jumpers to be placed on the motherboard so that these signals may be driven high or low. The use of these jumpers requires EXTRATIOPIN# to be unconnected (It defaults to low pull down inside cpu).
Table 4. Clock Ratio Signaling
RATIO 2:5 3:1 3.5:1 4:1 4.5:1 5:1 5.5:1 6:1 6.5:1 7:1 7.5:1 NMI L L L L L L L H H H H INTR] H L H L H L H L H L H A20M# L L L H H H H L L L L IGGNE# L H H L L H H L L H H 300 MHz 333 MHz 366 MHz 400 MHz 433 MHz 466 MHz 500 MHz 300 MHz 350 MHz 400 MHz 450 MHz 500 MHz CO RE CLO CK 66 MHZ BUS 100 MHZ BUS 133 MHZ BUS 333 MHz 400 MHz 466 MHz
JUMPERLESS: the Cyrix III has a built in clock multiplier that will run the cpu at the proper frequency. Also the BIOS can override the built in value by setting the Clock Multiplier Configuration Register during bootup. This alternative eliminates the need for clock multiplier jumper pins on the motherboard. See the Cyrix III BIOS Writer's Guide, or Cyrix III Data Book for complete information. If there are no jumpers on the board to set the clock multiplier, so that the board is relying on the built in multiplier or the BIOS to program the Cyrix III clock multiplier, the pin EXTRATIO# should be tied high (2.5v). This will make sure the Cyrix III does not latch in an invalid clock multiplier from the NMI-INTR-A20M#-IGGNE# pins. Instead the Cyrix III will boot up in default mode and the new clock multiplier can be programmed by BIOS. EXTRATIO# pin is a Vdd pin for Celeron so this pin will be high by default on most motherboards.
10
Application Note 127 Cyrix III Board Design and AC/DC Specifications
Design for Jumper Usage NMI NMI
Celeron or Cyrix III
IGGNE
INTR
INTR A20M
A20M# IGGNE#
EXTRATIOPIN# (ab2, internal PD)
no connect
NB
Design for Jumperless NMI NMI
Celeron or Cyrix III
IGGNE
INTR
INTR A20M
A20M# IGGNE#
EXTRATIOPIN# (ab2, internal PD)
NB
Application Note 127 Cyrix III Board Design and AC/DC Specifications
11
Cyrix III Board Design Considerations and AC/DC Specifications
6.
BUS SIGNAL GROUPS
The GTL+ signals are applied to open-drain receivers that differentially compare input signals to a reference voltage V REF and determine if the input signals are logically high or low. Termination resistors are needed to pull the signal high. The high termination voltage, V TT , is a typical value of 1.5 V. The reference voltage is typically 2/3 of VTT. The following table defines which signals are GTL+ and which are CMOS levels.
Table 5. Bus Signal Groups
SIGNAL T YPE GTL+ Input GTL+ I/O CMOS Input CMOS Output PARAME TER BPRI#, DEFER#, RESET#, RS[2-0]#, TRDY# A[31-3]#, ADS#, BNR#, BUSSEL66#, BUSSEL133#, D[63-0]#, DBSY#, DRDY#, HIT#, HITM#, LOCK#, REQ[4-0]# A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PWRGOOD, SMI#, SLP#, STPCLK# FERR#, VID[4-0],
12
Application Note 127 Cyrix III Board Design and AC/DC Specifications
7.
DC Characteristics
Below are the preliminary DC characteristics for the Cyrix III bus signals, and the GTL+ termination specifications that should be followed in order to design to this bus interface.
Table 6. GTL+ DC Characteristics
SY MBOL VIL VIH VOL VOH IOL IL ILO PARAME TE R Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Current Leakage Current Output Leakage Current 36 MIN -0.3 1.22 MAX 0.82 VTT 0.60 VTT 48 +/- 100 +/- 15 UNIT V V V V mA uA uA See bus termination table Measured into 25 ohm resistor to 1.5v See bus termination table NOTES
Table 7. GTL+ Termination Specifications
SY MBO L VTT BTT VREF PARAME TE R Bus Termination Voltage Bus Termination Resistance Input Reference Voltage 2/3 VTT 2% 1.365 MIN TYP ICAL 1.5 56 2/3 VTT 2/3 VTT +2% 1.635 MAX UNIT V Ohms V
Application Note 127 Cyrix III Board Design and AC/DC Specifications
13
Cyrix III Board Design Considerations and AC/DC Specifications
Table 8. CMOS DC Characteristics
SYMBOL VIL VIH VOL VOH IOL IL ILO PARAME TER Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Current Leakage Current Output Leakage Current 14 +/- 100 +/- 10 MIN -0.3 1.7 MAX 0.7 2.625 0.4 2.625 UNIT V V V V mA uA uA NOTE S
14
Application Note 127 Cyrix III Board Design and AC/DC Specifications
8.
AC Characteristics
Below are the preliminary AC characteristics for the system bus clock, BCLK, and the Cyrix III GTL+ and CMOS signals at different bus clock speeds.
Table 9. 66 MHz System Bus AC Characteristics
SYMBOL BCLK T1 T2 T3 T4 T5 T6 PARAMETER System Bus Frequency BCLK Period BCLK Period Stability BCLK High Time BCLK Low Time BCLK Rise Time BCLK Fall Time 3.6 3.6 0.34 0.34 1.40 1.40 MIN TYP ICAL 66.67 15.0 +/- 300 MAX UNIT MHz ns ps ns ns ns ns 0.5 V to 2.0 V 2.0 V to 0.5 V NO TES
Table 10. 100 MHz System Bus AC Characteristics
SYMBO L BCLK T1 T2 T3 T4 T5 T6 PARAMETE R System Bus Frequency BCLK Period BCLK Period Stability BCLK High Time BCLK Low Time BCLK Rise Time BCLK Fall Time 2.4 2.4 0.34 0.34 1.40 1.40 MIN TY PICAL 100.00 10.0 +/- 250 MAX UNIT MHz ns ps ns ns ns ns NOTES
Application Note 127 Cyrix III Board Design and AC/DC Specifications
15
Cyrix III Board Design Considerations and AC/DC Specifications
Table 11. 133 MHz System Bus AC Characteristics
SYMBO L BCLK T1 T2 T3 T4 T5 T6 PARAMETE R System Bus Frequency BCLK Period BCLK Period Stability BCLK High Time BCLK Low Time BCLK Rise Time BCLK Fall Time 1.8 1.8 0.34 0.34 1.40 1.40 MIN TY PICAL 133.00 7.5 +/- 200 MAX UNIT MHz ns ps ns ns ns ns NO TES
Table 12. GTL+ Bus AC Specifications
PARAMETER GTL+ Output Valid Delay GTL+ Input Setup Time GTL+ Input Hold Time RESET# pulse width 66 MHZ BUS MIN 0.17 1.60 0.90 1.00 MAX 4.40 100 MHZ BUS MIN 0.17 1.60 0.90 1.00 MAX 3.45 133 MHZ BUS MIN 0.17 1.40 0.90 1.00 MAX 3.00 UNIT ns ns ns ms NO TES 1, 2 1 1 3
Notes: 1. All timings are referenced from the rising edge of BCLK at 1.25 V and are measured to the GTL+ signal when it crosses 1.00 V. 2. Valid delay timings are specified for a 25 resistance to VT T and with V REF at 1.0 V. 3. RESET# must remain asserted for the time specified after VDDCORE and BCLK are stable.
16
Application Note 127 Cyrix III Board Design and AC/DC Specifications
Table 13. CMOS Signal AC Characteristics
PARAMETE R 2.5 V Output Valid Delay 2.5 V Input Setup Time 2.5 V Input Hold Time 66 MH Z MIN 0 4.0 1.3 MAX 8.0 100 MHZ MIN 0 4.0 1.3 MAX 8.0 133 MHZ MIN 0 4.0 1.3 MAX 7.0 UNIT ns ns ns See Note See Note NO TES
Application Note 127 Cyrix III Board Design and AC/DC Specifications
17
Cyrix III Board Design Considerations and AC/DC Specifications
©1999 Copyright Via Technologies. All rights reserved. Printed in the United States of America Trademark Acknowledgments: Cyrix is a registered trademark of Via Technologies. Cyrix III is a trademarks of Via Technologies. Intel and Celeron are registered trademarks of the Intel Corporation. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Via-Cyrix Corporation 2703 North Central Expressway Richardson, Texas 75080-2010 United States of America Via Technologies reserves the right to make changes in the devices or specifications described herein without notice. Before design-in or order placement, customers are advised to verify that the information is current on which orders or design activities are based. ViaCyrix warrants its products to conform to current specifications in accordance with the Via-Cyrix standard warranty. Testing is performed to the extent necessary as determined by Via-Cyrix to support this warranty. Unless explicitly specified by customer orde r requirements, and agreed to in writing by Via-Cyrix, not all device characteristics are necessarily tested. Via-Cyrix assumes no liability, unless specifically agreed to in writing, for customers' product design or infringement of patents or copyrights of third parties arising from use of Via-Cyrix devices. No license, either express or implied, to Via-Cyrix patents, copyrights, or other intellectual property rights pertaining to any machine or combination of Via-Cyrix devices is hereby granted. Via-Cyrix products are not intended for use in any medical, life saving, or life sustaining system. Information in this document is subject to change without notice.
18
Application Note 127 Cyrix III Board Design and AC/DC Specifications