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Cyrix CPU Detection Guide
Preliminary Revision 1.01

© 1997 Cyrix Corporation. All Rights Reserved. Cyrix reserves the right to make changes in its products without notice in order to improve design or performance characteristics. The information in this publication is believed to be accurate at the time of publication, but Cyrix makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication or the information contained herein, and reserves the right to make changes at any time, without notice. Cyrix disclaims responsibility for any consequences resulting from the use of the information included in this publication. This publication neither states nor implies any representations or warranties of any kind, including but not limited to, any implied warranty of merchantability or fitness for a particular purpose. Cyrix products are not authorized for use as critical components in life support devices or systems without Cyrix's written approval. Cyrix assumes no liability whatsoever for claims associated with the sale or use (including the use of engineering samples) of Cyrix products except as provided in Cyrix's Terms and Conditions of Sale for such product.

Trademarks Cyrix, the Cyrix logo, and combinations thereof are trademarks of Cyrix Corporation. 5x86, 6x86, 6x86MX, MediaGX are registered trademarks of Cyrix Corporation. MMX is a trademark of Intel Corporation. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

Revision History
REVISION 1.00 1.01 RELEASE DATE 09/30/97 10/02/97 DESCRIPTION OF CHANGES First Release (preliminary). Corrected the GXm and MediaGX values for DIR0 lookups

Cyrix CPU Detection
Introduction This document provides an overview of the three possible methods for detecting a Cyrix CPU. Once the correct method is identified (flowchart below), each detection method is covered in detail. This includes: How to detect the Cyrix CPU; Which CPU is present; What is the standard feature set; What are the Cyrix specific features. The three CPU detection methods are: 1. CPUID - Standard Levels This method provides the standard feature set (not vendor specific feature such as Extended MMX) and requires a look-up table. 2. CPUID - Extended Levels This is the preferred method of detection because it provides the ability to get the CPU name without requiring a look-up table. It also provides information that may be Cyrix specific. The CPUID - Extended Levels are only supported in the most recent CPUs such as GXm. 3. The 5/2 Method This method is used for older CPUs that do not support CPUID such as the 486DLC, 486SLC, 486DX, 486DX2 etc. The flowchart below should be used to determine the correct detection method. After identifying which method to use, refer to the correct section for further explanation. CPUID Supported? | No ------------------------------------------ Yes | | ( Use 5/2 Method ) Vendor = "CyrixInstead"? | Yes -------------------- No | | Extended ( Other Vendor ) CPUID Supported? | Yes ------------------------------------ No | | ( Use Extended Method ) ( Use Standard Method )

CPUID - Standard Levels
Overview The CPUID instruction is an application level (ring 3) instruction that provides information about the system's processor and its feature set. The CPUID instruction provides multiple functions, each containing different information about the processor. The CPUID instruction is used to identify the vendor, family, and type of processor, as well as information about any special features, like MMXTM, that the processor may support. The CPUID instruction may be executed at any privilege level. Testing for CPUID Support In order to avoid an invalid opcode exception on processors that do not support the CPUID instruction, software must first verify that the processor supports the CPUID instruction. The presence of the CPUID instruction is indicated by the ID bit (bit 21) in the EFLAGS register. If this bit can be toggled, the CPUID instruction is present and enabled on the processor. The following sample code will check for the presence of the CPUID instruction. The following code should be executed after support for EFLAGS is verified, or at least a 80386/80486 is known to be present.
Sample Code:
pushfd pop mov xor push popfd pushfd pop xor je eax ebx, eax eax, 200000h eax eax eax, ebx no_cpuid ; ; ; ; ; ; ; ; ; ; get extended flags store extended flags in eax save current flags toggle bit 21 put new flags on stack flags updated now in flags get extended flags store extended flags in eax if bit 21 r/w then eax <> 0 can't toggle id bit (21) no cpuid here

Standard CPUID Levels Each of the standard CPUID levels (EAX = 0 and EAX = 1) contain the same information for all vendors. The higher CPUID levels, including the extended levels, report information that is specific to the Cyrix family of processors.

Table 1 summarizes the actual CPUID values currently returned by Cyrix processors. Table 1. Actual CPUID Result Values: Description Standard Levels1 Stepping Model Family Type Extended Levels2 TLB Info 3 Cache Info 3 6x86 1 xx 2 5 0 6x86 (4.x) 1 xx 2 5 0 MediaGX 1 xx 4 4 0 6x86MX 1 0 0 6 0 GXm 2 0 4 5 0 8000 0005h 00 00 70 01h 00 00 00 80h

(EAX = 0h) - Vendor String and Max Standard CPUID Levels Supported Standard function 0h (EAX = 0) of the CPUID instruction returns the maximum standard CPUID levels supported by the current processor in EAX. EBX through EDX return the vendor string of the processor. Please make note of the order of the registers. EAX EBX ECX EDX
1 2 3

Max Standard Levels Vendor ID String 1 Vendor ID String 3 Vendor ID String 2

EAX Value when CPUID (EAX= 0) Executed Extended CPUID - EAX = 8000 0000h EAX = 2; See Table 5 for Value Definitions

(EAX = 01h) - Processor Signature and Standard Feature Flags Standard function 01h (EAX = 1) of the CPUID instruction returns the Processor Type, Family, Model, and Stepping information of the current processor in EAX. The Standard Feature Flags supported are returned in EDX. The other registers upon return are currently reserved. The breakdown of the EAX register is as follows: EAX[3:0] EAX[7:4] EAX[11:8] EAX[15:12] EAX[31:16] EBX ECX EDX Stepping ID Model Family Type Reserved Reserved Reserved Standard Feature Flags

(EAX = 02h) - TLB and L1 Cache Information Standard function 02h (EAX = 02h) of the CPUID instruction returns information that is specific to the Cyrix family of processors. Information about the TLB is returned in EAX. Information about the L1 Cache is returned in EDX. This information is to be looked up in a lookup table. (See Table 4) EAX EBX ECX EDX TLB Information Reserved Reserved L1 Cache Information

Standard Feature Flags The standard feature flags are returned in the EDX register when the CPUID instruction is called with standard function 01h (EAX = 1). Each flag refers to a specific feature and indicates if that feature is present on the processor. Some of these features require enabling or have protection control in CR4. Table 2 summarizes the standard feature flags. Before using any of these features on the processor, the software should check the corresponding feature flag. Attempting to execute an unavailable feature can cause exceptions and unexpected behavior. For example, software must check bit 4 before attempting to use the Time Stamp Counter instruction. See the glossary for a definition of each feature.

Table 2 - Standard Feature Flags Values: Feature Flag FPU V86 Debug Extension 4MB Page Size Time Stamp Counter RDMSR/WRMSR PAE MC Exception CMPXCHG8B APIC on Chip Reserved MTRR Global Bit Machine Check CMOV Reserved MMX EDX Bit 0 1 2 3 4 5 6 7 8 9 10-11 12 13 14 15 16-22 23 CR4 Bit 0,1 3 4 2 8 5 6 7 6x86* 6x86* (4.x) X X X X MediaGX* X 6x86MX X X X X X X X X X GXm X X X X X X

Extended CPUID Levels
Overview The extended CPUID levels are provided to simplify the detection routines used by developers as well as provide information on processor specific extensions. Like the CPUID instruction, the extended CPUID levels may be executed at any privilege level. Testing for Extended CPUID Support Before executing CPUID at the extended levels, software must first verify that the processor supports the CPUID instruction. The presence of the CPUID instruction is indicated by the ID bit (bit 21) in the EFLAGS register. If this bit can be toggled, the CPUID instruction is present and enabled on the processor.
Sample Code:
pushfd pop mov xor push popfd pushfd pop xor je eax ebx, eax eax, 200000h eax eax eax, ebx no_cpuid ; ; ; ; ; ; ; ; ; ; get extended flags store extended flags in eax save current flags toggle bit 21 put new flags on stack flags updated now in flags get extended flags store extended flags in eax if bit 21 r/w then eax <> 0 can't toggle id bit (21) no cpuid here

To verify that the processor supports the extended CPUID levels, software checks for "CyrixInstead" in the vendor string returned by CPUID level 0, and a value greater than or equal to 8000 0000h in the EAX register returned by CPUID level 8000 0000h.
Sample Code:
mov cpuid cmp jl eax, 8000000 eax, 8000000 no_extended ; ; ; ; try extended cpuid level execute cpuid instruction check if extended levels are supported extended cpuid functions not available

Among the processors in the Cyrix family, different ones may execute different levels of CPUID. Table 3 summarizes the CPUID levels currently implemented on Cyrix processors.

Table 3. Summary of CPUID Functions: Standard Functions 0 1 2 Extended Functions Description Standard Levels Vendor String Processor Information Standard Feature Flags TLB & Cache Information 5x86 & Prior 6x86* X X Media GX* X X 6x86MX X X GXm X X X X X X X X X

8000 0000h Extended Levels 8000 0001h Extended Processor Info. Extended Feature Flags 8000 0002h Processor Marketing Name 8000 0003h Processor Marketing Name 8000 0004h Processor Marketing Name 8000 0005h TLB & Cache Information

Extended CPUID Levels Each of the extended CPUID levels reports information that is specific to the Cyrix family of processors. (EAX = 8000 0000h) - Maximum Extended CPUID Levels Supported Extended function 8000 0000h (EAX = 8000 0000h) of the CPUID instruction returns the maximum extended CPUID levels supported by the current processor in EAX. The other registers upon return are currently reserved. EAX EBX ECX EDX Max Extended Levels Reserved Reserved Reserved

(EAX = 8000 0001h) - Processor Signature and Extended Feature Flags Extended function 8000 0001h (EAX = 8000 0001h) of the CPUID instruction returns the Processor Type, Family, Model, and Stepping information of the current
*

CPUID is turned off by default on this CPU and most BIOS

processor in EAX. The Extended Feature Flags supported are returned in EDX. The other registers upon return are currently reserved. The breakdown of the EAX register is as follows: EAX[3:0] EAX[7:4] EAX[11:8] EAX[15:12] EAX[31:16] EBX ECX EDX Stepping ID Model Family Processor Type Reserved Reserved Reserved Extended Feature Flags

(EAX = 8000 0002h - 8000 0004h) - Official CPU Name Extended functions 8000 0002h through 8000 0004h (EAX = 8000 0002h through EAX = 8000 0004h) of the CPUID instruction returns an ASCII string containing the name of the current processor. These functions eliminate the need to look up the processor name in a lookup table. Software can simply call these functions to obtain the name string. The string may be 48 ASCII characters long, and is returned in little endian format. If the name is shorter than 48 characters long, the remaining bytes will be filled with ASCII NUL character (00h). 8000 0002h EAX EBX ECX EDX 8000 0003h EAX EBX ECX EDX 8000 0004h EAX EBX ECX EDX

CPU Name 1 CPU Name 2 CPU Name 3 CPU Name 4

CPU Name 5 CPU Name 6 CPU Name 7 CPU Name 8

CPU Name 9 CPU Name 10 CPU Name 11 CPU Name 12

(EAX = 8000 0005h) - TLB and L1 Cache Information Extended function 8000 0005h (EAX = 8000 0005h) of the CPUID instruction returns information about the TLB and L1 Cache to be looked up in a lookup table. EAX EBX ECX EDX Reserved TLB Information L1 Cache Information Reserved

Extended Feature Flags The extended feature flags are returned in the EDX register when the CPUID instruction is called with extended function 8000 0001h (EAX = 8000 0001h). Each flag refers to a specific feature and indicates if that feature is present on the processor. Some of these features require enabling or have protection control in CR4. Table 4 summarizes the extended feature flags. See the glossary for a definition of each feature. Table 4 - Extended Feature Flags Values: Feature Flag EDX CR4 Bit CPUs Prior to Bit GXm FPU 0 V86 Debug Extension Page Size Extensions Time Stamp Counter Cyrix MSR PAE MC Exception CMPXCHG8B APIC on Chip SYSCALL/SYSRET Reserved MTRR Global Bit Machine Check CMOV FPU CMOV Reserved MMX Extended MMX 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17-22 23 24 0,1 3 4 2 8 5 6 7 -

GXm X X X X X X X X

Table 5 - Cache and TLB Descriptor Lookup Table Value
01h

Name

Size

Associative

Comments

If the least-significant byte (byte 0) is set to 01h, this indicates that the CPUID instruction needs to be executed only once with an input value of 2 to retrieve complete information about the processor's caches and TLBs. TLB Level 1 Cache 32 Entry 16K 4 Way 4 Way 4K-Byte Pages 16 Bytes/Line

70h 80h

Cyrix CPU Detection - "The 5/2 Method"
Overview Each of the CPU vendors has created a unique way of determining which CPU is in a user's machine. A developer may detect if a Cyrix CPU is present by using a simple division routine then checking the status of the Flags register. This method is only valid after determining that the CPU does not support CPUID. Software that does not first check for CPUID may report a Cyrix CPU when one is not present. Once a Cyrix CPU is determined to be present, the software may use the "Cyrix Device ID Registers" and a lookup table to determine which CPU is present. Detecting a Cyrix CPU A software check is required to determine if the CPU is an 80486 or above class processor, since all Cyrix CPUs are 80486 and above class processors. If this check is not made, the software may report a Cyrix CPU when one is not present. The following code is an example of how to detect an 80486 and above class processor.
Sample Code:
pushfd pop mov xor push popfd pushfd pop cmp jz eax ecx, eax eax, 40000h eax eax eax, ecx is_not_80486 ; ; ; ; ; ; ; ; ; ; save EFLAGS get EFLAGS temp storage EFLAGS change AC bit in EFLAGS put new EFLAGS value on stack replace current EFLAGS value get EFLAGS save new EFLAGS in EAX compare temp and new EFLAGS not a 486 or above class processor

The division routine is used after it has been determined that the processor is a 80486 or above class processor. Detection of a Cyrix CPU is accomplished by checking the state of the undefined flags following execution of the divide instruction that divides 5 by 2 (5 ÷2). The undefined flags in a Cyrix processor remain unchanged following the divide operation. Other vendor's processors will modify some of the undefined flags.
Sample Code:
xor sahf mov mov div lahf cmp jne ax, ax ax, 5 bx, 2 bl ah, 2 not_cyrix ; ; ; ; ; ; ; ; clear ax clear flags, bit 1 is always 1 in flags move 5 into the dividend move 2 into the divisor do an operation that does not change flags get flags check for change in flags flags changed, not a Cyrix CPU

Determining which Cyrix CPU is present After determining that a Cyrix processor exists, its Device ID Registers can be read to identify its type. The Device ID Registers exist at register indexes FEh and FFh. Access to these registers is achieved by writing the index of the register to I/O port 22h. I/O port 23h is then used for data transfer. Each port 23h data transfer must be preceded by a port 22h-

register index selection, otherwise the second and later port 23h operations are directed offchip and produce external I/O cycles. The following is a table describing the bit definitions of each Device ID Register: DIR0 Bit Definitions Bit Position Description 7-0 CPU Device Identification Number (read only)

DIR1 Bit Definitions Bit Position Description 7-4 CPU Step Identification Number (read only) 3-0 CPU Revision Identification (read only)

The following is a table describing the base level DIR0 values for the different generations of Cyrix CPUs. A more detailed table of each generation of Cyrix CPU is located in Appendix A. DIR1 Values 00h - 07h 10h - 13h 1Ah - 1Fh 28h - 2Fh 30h - 35h 50h - 5Fh 40h - 4xh 42h Description Cx486SLC/DLC/SRx/DRx Cx486S Cx486DX/DX2 5x86 6x86 / 6x86L 6x86MX MediaGX GXm

GLOSSARY:
Feature Flags Descriptions: FPU A Floating-point unit is onboard the CPU. V86 Virtual mode extensions are available. Debug I/O Breakpoint debug extensions are supported. Page Size 4-Mbyte pages are supported. Time Stamp A time stamp counter is available, and the RDTSC instruction is available. MSRs Cyrix model-specific registers are available, and the RDMSR and WRMSR instructions are supported. PAE Physical Address Extensions. (Need more info...) MCExt Machine Check Exception is supported. CMPXCHG8B Compare Exchange Eight Byte instruction is supported. APIC A local APIC unit is available. MTRR Memory Type Range Register (Need more info...) Global Paging Global paging extensions are available. Machine Check Machine Check Arch. (Need more info...) Cond. Move The conditional move instructions CMOV, FCMOV, and FCOMI are supported. MMX MMXTM instruction set is supported. SYSCALL/RET SYSCALL and SYSRET instructions and associated extensions are supported. FPU CMOVs Floating-point conditional move instructions FCMOV and FCOMI are supported.

Appendix A:
Tables of DIR values for each Cyrix Processor Cx486SLC/DLC/SRx/DRx (M0.5)
DIR0 00h 01h 02h 03h 04h 05h 06h 07h DIR1 Stepping Stepping Stepping Stepping Stepping Stepping Stepping Stepping Description Cx486_SLC Cx486_DLC Cx486_SLC2 Cx486_DLC2 Cx486SRx (Retail Upgrade CPU) Cx486DRx (Retail Upgrade CPU) 2x Cx486SRx2 (Retail Upgrade CPU) 2x Cx486DRx2 (Retail Upgrade CPU)

Cx486S (M0.6)
DIR0 10h 11h 12h 13h DIR1 Stepping Stepping Stepping Stepping Description Cx486S (B step) Cx486S2 (B step) Cx486Se (B step) Cx486S2e (B step)

Cx486DX/DX2 (M0.7)
DIR0 1Ah 1Bh 1Fh DIR1 Stepping Stepping Stepping Description Cx486DX Cx486DX2 Cx486DX4

5x86 (M0.9)
DIR0 28h 2Ah 29h 2Bh 2Dh 2Fh 2Ch 2Eh DIR1 Stepping Stepping Stepping Stepping Stepping Stepping Stepping Stepping Description 1x Clock (Core/Bus) 1x Clock (Core/Bus) 2x Clock (Core/Bus) 2x Clock (Core/Bus) 3x Clock (Core/Bus) 3x Clock (Core/Bus) 4x Clock (Core/Bus) 4x Clock (Core/Bus)

6x86 (M1)
DIR0 30h 31h 35h 34h DIR1 Stepping Stepping Stepping Stepping Description 1x Clock (Core/Bus) 2x Clock (Core/Bus) 3x Clock (Core/Bus) 4x Clock (Core/Bus)

6x86L (M1)
DIR0 30h 31h 35h 34h DIR1 > 21h > 21h > 21h > 21h Description 1x Clock (Core/Bus) - Supports CMPEX8B, Debug Ext. 2x Clock (Core/Bus) - Supports CMPEX8B, Debug Ext. 3x Clock (Core/Bus) - Supports CMPEX8B, Debug Ext. 4x Clock (Core/Bus) - Supports CMPEX8B, Debug Ext.

6x86MX (M2)
DIR0 50h 58h 51h 59h 52h 5Ah 53h 5Bh 54h DIR1 Stepping Stepping Stepping Stepping Stepping Stepping Stepping Stepping Stepping Description 1x Clock (Core/Bus) 1x Clock (Core/Bus) 2x Clock (Core/Bus) 2x Clock (Core/Bus) 2.5x Clock (Core/Bus) 2.5x Clock (Core/Bus) 3x Clock (Core/Bus) 3x Clock (Core/Bus) 3.5x Clock (Core/Bus)

5Ch 55h 5Dh 56h 5Eh 57h 5Fh

Stepping Stepping Stepping Stepping Stepping Stepping Stepping

3.5x Clock (Core/Bus) 4x Clock (Core/Bus) 4x Clock (Core/Bus) 4.5x Clock (Core/Bus) 4.5x Clock (Core/Bus) 5x Clock (Core/Bus) 5x Clock (Core/Bus)

MediaGX (Gx86)
DIR0 41h 45h 47h 44h 46h DIR1 Stepping Stepping Stepping Stepping Stepping Description 3x Clock (Core/Bus) 3x Clock (Core/Bus) 3x Clock (Core/Bus) 4x Clock (Core/Bus) 4x Clock (Core/Bus)

(GXm)
DIR0 40h 42h 47h 41h 43h 44h 46h 45h DIR1 Stepping Stepping Stepping Stepping Stepping Stepping Stepping Stepping Description 4x Clock (Core/Bus) 4x Clock (Core/Bus) 5x Clock (Core/Bus) 6x Clock (Core/Bus) 6x Clock (Core/Bus) 7x Clock (Core/Bus) 7x Clock (Core/Bus) 8x Clock (Core/Bus)