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Excerpt Edition
This PDF is an excerpt from Chapter 8
of the Parametric Measurement Handbook.
The
Parametric Measurement
Handbook
Third Edition
March 2012
Chapter 8: Capacitance Measurement Fundamentals
"Furious activity is no substitute for understanding." -- H. H. Williams
Introduction
Capacitance measurement is one area of parametric test where many easily
preventable measurement mistakes are often made. The reason for this is not
lack of intelligence on the part of the user, but rather a lack of fundamental
training on capacitance measurement theory and how to make good capacitance
measurements. Unfortunately, this type of information is typically not taught
in universities and can usually only be learned either through (rather painful)
experience or by reading about it in a publication such as this.
Why do engineers make so many mistakes when measuring capacitance
(especially on-wafer)? The most common reasons are:
1. Capacitance measurement requires compensation to remove parasitic
inductance and capacitance from the measurement cables and fixturing, and
many times this is done improperly (or not at all).
2. An induced current flows through the outer shield of the BNC connectors
(if used) on a capacitance meter, and this current is necessary to balance
the measurement current of the capacitance meter. If the outer shield is
grounded, then the induced current flow is shorted to ground and the bridge
may not be able to balance. Many users are unaware of this issue.
3. Measuring capacitance on a semiconductor wafer on a wafer chuck is very
different from measuring a discrete device. The effects of the wafer prober
chuck on the measurement cannot be ignored.
4. For higher measurement frequencies (> 5 MHz), structure (layout) design has
a major impact on the success or failure of the measurements.
As we progress through this (rather lengthy) chapter we will cover all of these
issues in detail
145
MOSFET capacitance measurement
Review of MOSFET capacitance behavior
Before delving into capacitance measurement theory, it is useful to first review
MOSFET device operation to remind ourselves as to why we are making
these measurements in the first place. While the capacitance measurement
techniques discussed in this chapter are general and can be used on a variety
of different device types, the dominance of MOSFETs in modern electronics
elevates them enough in importance to justify devoting a section to reviewing
their operating characteristics.
MOSFETs are voltage-dependent capacitors. The MOSFET gate-to-substrate
capacitance depends upon the applied dc voltage (which we measure using an
ac voltage of much smaller magnitude that rests on top of the dc voltage). The
following set of diagrams shows the behavior of an NMOS transistor as the
voltage applied to the gate is varied from negative to positive.
Figure 8.1. Capacitive behavior of an NMOS transistor to changes in the voltage applied
to the gate.
If the silicon is held at ground and a negative voltage is applied to the gate, the
MOS capacitor will begin to store positive charge at the silicon surface. The
surface has a greater density of holes than Na (the acceptor density), and this
condition is known as surface accumulation. In this condition the mobile charge
on both sides of the oxide can respond rapidly to changes in applied voltage,
and the device looks just like a parallel plate capacitor of thickness tox. Since it
is a pure gate oxide capacitance, we denote its value as Cox.
146
If a positive gate voltage is applied to the gate relative to the silicon, the built-in
positive voltage between the gate and silicon is increased. The silicon surface
becomes further depleted of carriers as more acceptors become exposed at the
surface, resulting in the condition known as surface depletion. In this condition
electrostatic analysis shows that the total MOS capacitance consists of the
series combination of Cox and the capacitance across the surface depletion
region, Cd. Note that Cd depends upon the applied voltage.
If the positive gate voltage is further sufficiently increased, then the energy
bands bend away considerably from their levels in the bulk of the silicon. The
depletion region reaches a maximum width, xdmax, and all of the electron
acceptors within this region are fully ionized. In the surface region generation of
carriers exceeds recombination, and the generated electrons are swept by the
electric field into the oxide-silicon interface where they remain due to the energy
barrier between the conduction bands of the silicon and the oxide. Thus, the
total charge in the silicon consists of the sum of these two charges. Electrostatic
analysis again shows that the total MOS capacitance can be modeled as the
oxide capacitance in series with the parallel combination of the depletion
capacitance and the series combination of surface charge capacitance, Ci, and
the depletion resistance, Rt.
Sample MOSFET parameter calculation
The reason that measurement of the gate to substrate capacitance of a MOSFET
device is so important is that it is the only way to calculate many important
device parameters such as substrate impurity concentration (Nsub) and flat band
voltage (Vfb). It is illustrative to go through a sample parameter calculation to
show how to extract these parameters from a capacitance versus voltage (CV)
curve. All of the following calculations are based upon the (CV) curve shown
below:
Figure 8.2. Capacitance versus voltage (CV) plot.
147
The gate oxide thickness of a MOSFET capacitor (tox) can be calculated from the
standard equation for a parallel plate capacitor:
A10 8 o d
tox = [Angstroms] (Equation 8.1)
Cox
Where: A is the capacitor gate area [cm2]
o is the free space permittivity (8.854