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ZZZ1
PCB
1 1
Compal Confidential
2 2
IFTxx Schematics Document
Intel Merom Processor with Crestline + DDRII + ICH8M
(With nVIDIA MXM/B)
3 2006-11-01 3
REV: 0.1
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
IFTXX M/B LA-3541P Schematic
Date: Wednesday, November 01, 2006 Sheet 1 of 52
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Compal Confidential
Thermal Sensor Clock Generator
Model Name : IFTXX Fan Control Intel Merom Processor
page 4 ADM1032 ICS9LPRS365
page 4 page 16
File Name : LA-3541P uPGA-478 Package
1
page 4,5,6 1
FSB
H_A#(3..35) 667/800MHz H_D#(0..63)
CRT & TV-out
page 19
LVDS Memory BUS(DDRII) 200pin DDRII-SO-DIMM X2
LCD Conn. Video Processor Intel Crestline
page 18 page 18 LVDS SDVO Dual Channel BANK 0, 1, 2, 3 page 14,15
1.8V DDRII 533/667
uFCBGA-1299
PCI-Express
page 7,8,9,10,11,12,13
MXM II VGA/B DMI USB conn x2 USB conn x2
X4 mode Bluetooth CMOS Camera Finger Print
page 17
TO M/B TO I/O/B Conn page Conn page 42
page 33 page 37 33 page 42
2 2
PCI-Express USB
Intel ICH8-M 3.3V 48MHz
3.3V 24.576MHz/48Mhz HD Audio
PCI BUS
3.3V 33 MHz 3.3V ATA-100 IDE
IDSEL:AD20 IDSEL:AD22 BGA-676
(PIRQC#,PIRQD#, (PIRQG#,PIRQH#,
S-ATA port 0
GNT#2, REQ#2) GNT#0, REQ#0) page 20,21,22,23
New Card MINI Card x3 LAN(GbE) CDROM MDC 1.5 HDA Codec
Socket WLAN,
BCM5787M/5906 CardBus Card Reader Conn. 24
page
Conn 42
page
ALC268
page 38
page 33 3G/TV-Tuner
ENE CB1410 R5C833
Robson page 32 page 30 page 26 page 28
S-ATA HDD
Conn.page 24
PCMCIA 13 94 3 in 1 Audio AMP
RJ45 Conn. socket page 39
page 31
Socket 26
page page 28 page 29 LPC BUS
3 3
RTC CKT.
page 21 ENE KB925 SUPER I/O TPMpage 29
page 34
LPC47N217
page 41
Power On/Off CKT. Switch/B Conn.
page 37
page 35
Touch Pad Int.KBD
page 36 page 35
DC/DC Interface CKT.
I/O Conn. G-Sensor BIOS SCREW
page 43 page 40
page 25 page 36
FRONT LCD /B.
Power Circuit DC/DC LID SW
4 4
page 44,45,47,48
49,50,51 page 37
CHARGER Security Classification Compal Secret Data Compal Electronics, Inc.
page 46
Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
IFTXX M/B LA-3541P Schematic
Date: Wednesday, November 01, 2006 Sheet 2 of 52
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1
Voltage Rails 1
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Power Plane Description S1 S3 S5
External PCI Devices
VIN Adapter power supply (19V) N/A N/A N/A
B+ AC or battery power rail for power circuit. N/A N/A N/A
DEVICE IDSEL # REQ/GNT # PIRQ
+CPU_CORE Core voltage for CPU ON OFF OFF CARD BUS CB1410 AD20 2 C,D
+0.9VS 0.9V switched power rail for DDR terminator ON OFF OFF 1394+Cardreader AD22 0 G,H
+1.05VS 1.05V switched power rail ON OFF OFF
+1.25VS 1.25V switched power rail ON OFF OFF
+1.5VS 1.5V switched power rail ON OFF OFF
+1.8V 1.8V power rail for DDR ON ON OFF
+1.8VS 1.8V switched power rail ON OFF OFF
+2.5VS 2.5V switched power rail ON OFF OFF
+3VALW 3.3V always on power rail ON ON ON*
+3VS 3.3V switched power rail ON OFF OFF
+5VALW 5V always on power rail ON ON ON*
2 2
+5VS 5V switched power rail ON OFF OFF
+VSB VSB always on power rail ON ON ON*
EC SM Bus1 address EC SM Bus2 address
+RTCVCC RTC power ON ON ON
Device Address Device Address
Smart Battery 0001 011X b ADI ADM1032 1001 100X b
EEPROM(24C16/02) 1010 000X b NVIDIA NB8X
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
3 ICH8M SM Bus address 3
Device Address
BOARD ID Table
Clock Generator 1101 001Xb
ID1 ID0 TEST (ICS9LPRS325AKLFT_MLF72)
0(R744) 0(R745) DDR DIMM0 1010 000Xb
A-TEST
0(R744) 1(R742) DDR DIMM1 1010 010Xb
B-TEST
1(R741) 0(R745) C-TEST
PANEL ID Table
R Size
Ra (R743) 15W
Rb (R740) 14W
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
IFTXX M/B LA-3541P Schematic
Date: Wednesday, November 01, 2006 Sheet 3 of 52
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5 4 3 2 1
H_A#[3..35]
<7> H_A#[3..35] Place close to CPU within 500mil
H_REQ#[0..4]
<7> H_REQ#[0..4]
JP36A
H_RS#[0..2] H_A#3 J4 H1 +1.05VS
<7> H_RS#[0..2] A[3]# ADS# H_ADS# <7>
ADDR GROUP 0
H_A#4 L5 E2 H_BNR# <7> Checklist recommend 39 Ohm
H_A#5 A[4]# BNR#
L4 A[5]# BPRI# G5 H_BPRI# <7>
H_A#6 K5 H_PREQ# R559 1 2 56_0402_5%
H_A#7 A[6]#
M3 A[7]# DEFER# H5 H_DEFER# <7>
H_A#8 N2 F21 H_IERR# R560 1 2 56_0402_5%
A[8]# DRDY# H_DRDY# <7>
D H_A#9 J1 E1 D
A[9]# DBSY# H_DBSY# <7>
H_A#10 N3 ITP_TMS R562 1 2 56_0402_5%
H_A#11 A[10]#
P5 A[11]# BR0# F1 H_BR0# <7>
H_A#12 P2 ITP_TDI R563 1 2 150_0402_1%
A[12]#
CONTROL
H_A#13 L2 D20 H_IERR#
H_A#14 A[13]# IERR# H_PROCHOT# R565 1 56_0402_5%
P4 A[14]# INIT# B3 H_INIT# <21> 2
H_A#15 P1
H_A#16 A[15]# ITP_TCK R568 1 27.4_0402_1%
R1 A[16]# LOCK# H4 H_LOCK# <7> 2
<7> H_ADSTB#0 M1 ADSTB[0]#
C1 H_RESET# H_RESET# <7> CRB pull 75 Ohm ITP_TRST# R569 1 2 680_0402_5%
H_REQ#0 RESET# H_RS#0
K3 REQ[0]# RS[0]# F3
H_REQ#1 H2 F4 H_RS#1
H_REQ#2 REQ[1]# RS[1]# H_RS#2
K2 REQ[2]# RS[2]# G3
H_REQ#3 J3 G2 H_TRDY# <7>
H_REQ#4 REQ[3]# TRDY#
L1 REQ[4]#
HIT# G6 H_HIT# <7>
H_A#17 Y2 E4
H_A#18
H_A#19
U5
R3
A[17]#
A[18]#
HITM#
AD4
H_HITM# <7>
ADM1032 +3VS
A[19]# BPM[0]#
ADDR GROUP 1
H_A#20 W6 AD3 C687
H_A#21 A[20]# BPM[1]# 0.1U_0402_16V4Z
U4 AD1
XDP/ITP SIGNALS
H_A#22 A[21]# BPM[2]#
Y5 A[22]# BPM[3]# AC4 1 2
H_A#23 U1 AC2
H_A#24 A[23]# PRDY# H_PREQ#
R4 A[24]# PREQ# AC1
H_A#25 T5 AC5 ITP_TCK
H_A#26 A[25]# TCK ITP_TDI
T3 A[26]# TDI AA6
H_A#27 W2 AB3 1 U38
H_A#28 A[27]# TDO ITP_TMS C688
W5 A[28]# TMS AB5 1 VDD SCLK 8 EC_SMB_CK2 <17,34>
H_A#29 Y4 AB6 ITP_TRST#
C H_A#30 A[29]# TRST# ITP_DBRESET# 2200P_0402_50V7K THERMDA C
U2 A[30]# DBR# C20 ITP_DBRESET# <22> 2 D+ SDATA 7 EC_SMB_DA2 <17,34>
H_A#31 2
V4 A[31]#
H_A#32 W3 THERMDC 3 6
H_A#33 A[32]# H_PROCHOT# D- ALERT#
AA4 A[33]# THERMAL H_PROCHOT# <51>
H_A#34 AB2 Connect SB SYS_RESET# or just left NC 4 5
H_A#35 A[34]# THERM# GND
AA3 A[35]# PROCHOT# D21
V1 A24 THERMDA
<7> H_ADSTB#1 ADSTB[1]# THERMDA
B25 THERMDC ADM1032ARMZ_MSOP8
THERMDC
<21> H_A20M# A6 A20M#
ICH
A5 C7 H_THERMTRIP# <8,21> F75383M_MSOP8
<21> H_FERR# FERR# THERMTRIP#
<21> H_IGNNE# C4 IGNNE#
<21> H_STPCLK# D5 STPCLK#
<21> H_INTR C6 LINT0 H CLK
<21> H_NMI B4 LINT1 BCLK[0] A22 CLK_CPU_BCLK <16>
<21> H_SMI# A3 SMI# BCLK[1] A21 CLK_CPU_BCLK# <16>
M4
N5
RSVD[01] FAN1 Conn
RSVD[02]
T2 RSVD[03] H_THERMDA, H_THERMDC routing together,
V3 RSVD[04]
B2 Trace width / Spacing = 10 / 10 mil
RESERVED
RSVD[05]
C3 RSVD[06]
D2 RSVD[07]
D22 RSVD[08]
D3 +5VS
RSVD[09] C28 10U_1206_16V4Z +5VS
F6 RSVD[10]
1 2
1
B B
Merom Ball-out Rev 1a U5 D4
conn@ 1 8
VEN GND 1SS355_SOD323
2 VIN GND 7
+VCC_FAN1 3 6 @ D5
2
EN_FAN1 VO GND @ 1N4148_SOT23
<34> EN_FAN1 4 VSET GND 5
1 2
G993P1UF_SOP8
C29
10U_1206_16V4Z
1 2
+3VS C30
1000P_0402_50V7K
1 2
1
R44
10K_0402_5%
40mil JP6
2
+VCC_FAN1 1 1
<34> FAN_SPEED1 2 2
3 3
1
C31 4
1000P_0402_50V7K GND
5 GND
2
A A
ACES_85205-03001
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Merom (1/3)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
IFTXX M/B LA-3541P Schematic
Date: Wednesday, November 01, 2006 Sheet 4 of 52
5 4 3 2 1
5 4 3 2 1
H_D#[0..63] JP36C
H_D#[0..63] <7>
+CPU_CORE A7 VCC[001] VCC[068] AB20 +CPU_CORE
JP36B A9 AB7
H_D#0 H_D#32 VCC[002] VCC[069]
E22 D[0]# D[32]# Y22 A10 VCC[003] VCC[070] AC7
D H_D#1 F24