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INDEX
INDEX
INDE
1. PRAFACE
1.1 PRAFACE.....................................................................................................................1
1.2 FRANT PENEL& REAR PENEL.....................................................................................2
1.3 REMOTE CONTROL............................................................................. .......................3
2. BLOCK DIAGRAM
2.1 BLOCK DIAGRAM........................................................................................................4.
2.2 SCHEMATIC DIAGRAM.................................................................................................5
3. EXPLODED VIEW......................................................................6
4. PARTS SPECIFICATIONS
4.1 2A265.....................................................................................................................7-10
4.2 CS9800.................................................................................................................11-18
4.3 DRAM 2M*32(EM638165).......................................................................................19-22
4.4 CS4955.................................................................................................................23-25
4.5 CS4360.................................................................................................................26-30
4.6 CS92288...............................................................................................................31-45
4.7 DRAM 1M*16(VT3617161)......................................................................................46-49
4.8 SAA7114H.............................................................................................................50-57
4.9 CS533...................................................................................................................58-59
4.10 PCF8563.............................................................................................................60-62
4.11 TUNER................................................................................................................... .63
4.12 VFD DRIVER PT6312.................................................................... ......................64-65
4.13 SERVO............................................................................................. .......................66
4.14 HDD INFORMATION.............................................................................................67-68
5. SCHEMATIC DIAGRAM
5.1 POWER SCHEMATIC..................................................................... .......................69-70
5.2 MAIN SCHEMATIC......................................................................... .......................71-79
5.3 AV INPUT /OUTPUT SCHEMATIC.................................................... ...................... 80-87
5.4 VFD DRIVER........................................................................................................ 88-89
6. PARTS LIST
6.1 MAIN BOARD........................................................................................................90-92
6.2 VFD DRIVER BOARD.......................................................................... .......................93
6.3 POWER BOARD....................................................................................................94-95
6.4 AV BOARD.................................................................................................................96
1
2
3
BLOCK DIAGRAM
~110~240V
VIDEO OUT VIDIO IN PUT
AUDIO OUT AUDIO IN PUT
+12V TUNER75 IN PUT
S-VIDEO OUT
+5V
CB.CR.YOUT
-12V
POWER COAXIAL OUT
BOARD OPTICAL OUT
+3.3V AV BOARD
+2.5V
+1.8V
DVD LOADER
MAIN BOARD
DRIVE
MPEG VIDEO DECODER&
MPEG-2
AUDIO/ VIDEO CODER
40GB HDD
40GB HDD DRIVE
PT16312
KEY SCANNING &
VFD DISPLAY
4
SAA7114 TO S-VIDEO
P-CTL TO TUNER
CS5331 VIDEO
5VSTB
AUDIO DECOD ER
1.8V AUDIO L3CH CS4955 S-VIDEO
ADC S-VIDEO CS4360
2.5V VIDEO---- D/A
AUDIO TO-TUNER AUDIO COMPOSITE VIDEO
VCC AUDIO R(3CH) ENCODER
L.R CH DACS
3.3V
SCHEMATIC DIAGRAM
CPLD
5
CS92288 SS9800
MPEG-2 MPEG
To front panel DRAM
Host interface A/V CODEC DECODER
2M*32
ATAPI
To front panel
TO DVD LOADER DRIVE
HDD ATAPI I/O CHAN
FLASH
DRAM
16M
1M*16 4PCS TO VFD BOARD
CN104
16
17
EXPLODED VIEW
15
18 NO. ITEM NAME MATERIAL QUANTITY
Mirror bar pc
19
Left decorative bar ABS
Tray door ABS
20 Front panel ABS
14
Left four-key button ABS
13 21
Small light conductor PMMA
12 Big light conductor PMMA
LED stander PS
6
11
VFD driver board
10 Chasis SECC
9 22 Loader mechanism PS
8 DVD loader
23 Iron stand SECC
7
Power board
24
6 Top cover SECC
5 Rear panel SECC
4 AV board
3 Main board
2
Hard disc
Copper column
1
Rubber pad RUBBER
Open/close button ABS
Right four-key button ABS
Right decorative bar ABS
Circuit Diagram: ICE2AXXX for OFF ¨C Line Switch Mode Power Supplies
7
ICE2AXXX for OFF Line Switch Mode Power Supplies
Protection Functions
The block diagram displayed in Fig. 4 shows the interal functions of the protection unit. The
comparators C1, C2, C3 and C4 compare the soft-start and feedback-pin voltages. Logic gates
connected to the comparator outputs ensure the combination of the signals and enables the setting of
the "Error-Latch".
8
ICE2AXXX for OFF Line Switch Mode Power Supplies
Overload and Open-Loop Protection
· Feedback voltage (VFB) exceeds 4.8V and soft start
voltage (VSS) is above 5.3V (soft start is completed) (t1)
· After a 5µs delay the CoolMOS is switched off (t2)
· Voltage at Vcc Pin (VCC) decreases to 8.5V (t2)
· Control logic is switched off (t3)
· Start-up resistor charges Vcc capacitor (t3)
· Operation starts again with soft start after Vcc voltage
has exceeded 13.5V (t4)
t1, t2
VCC
VFB
VSS
t1 t2 t3 t4
Fig. 6
Fig. 7
t4
t3 VCC
t1, t2
VFB
VSS
9
ICE2AXXX for OFF Line Switch Mode Power Supplies
References
[1] Keith Billings,
Switch Mode Power Supply Handbook
[2] Ralph E. Tarter,
Solid-State Power Conversion Handbook
[3] R. D. Middlebrook and Slobodan Cuk,
Advances in Switched-Mode Power Conversion
[4] Herfurth Michael,
Ansteuerschaltungen für getaktete Stromversorgungen mit Erstellung eines linearisierten
Signalflußplans zur Dimensionierung der Regelung
[5] Herfurth Michael,
Topologie, Übertragungsverhalten und Dimensionierung häufig eingesetzter
Regelverstärker
[6] Infineon Technologies, Datasheet,
CoolSET-II
ä
Off Line SMPS Current Mode Controller with 650V/800V CoolMOSä on Board,
[7] Robert W. Erickson,
Fundamentals of Power Electronics
10
CS98000
Internet DVD (iDVD) Chip Solution
Features Description
l Powerful Dual 32-bit RISCs >160MIPS Overall the CS98000 Crystal DVD Processor is targeted
l Software based on popular RTOS, C/C++ as a market specific consumer entertainment processor
empowering new product classes with the inclusion of a
l MPEG video decoder supports DVD, VCD, DVD player as a fundamental feature. This integrated
VCD 3.0, SVCD standards circuit when used with all the other Crystal mixed signal
l Video input with picture-in-picture & zoom data converters, DSPs and high quality factory firmware
l 8-bit multi-region OSD w/vertical flicker filter enables the conception and rapid design of market lead-
ing internet age products like:
l Universal subpicture unit for DVD and SVCD
l PAL<->NTSC Scaling ~ Transcoding · DVD A/V Mini-System
· Home Media Controller
l Supports SDRAM and FLASH memories · Combination DVD Player
l Powerful 32-bit Audio DSP >80 MIPS · Car/SUV Entertainment Unit
l Decodes: 5.1 channel AC-3, MPEG Stereo Future Firmware Enhancements:
l Plays MP-3 CDs (a MP-3 CD =12 albums)
l Karaoke echo mix and pitch shift · Web I/O via AC-Link Input & Built-in Soft Modem
· DVD Audio Navigation
l Optional 3-D Virtual, bass & treble control · MLP Decoder, DTS Decoder, AAC Decoder
l 8-channel dual-zone PCM output · MP-3 Encoder, Ripping Controller
l IEC-60958/61937 Out: AC-3, DTS, MPEG
l Multi-Mode Serial Audio I/O: I2S & AC-Link ORDERING INFORMATION
CS98000-CQ 0° to 70° C 208-pin
l AV Bus or ATAPI interface or DVD/CD/HD CS98010-CQ 0° to 70° C 128-pin
l GPIO support for all common sub-circuits
RISC-1 RISC-2 Memory Controller 32- Bit DSP
I-Cache D-Cache I-Cache D-Cache SDRAM Control I-Cache
MMU MAC MMU MAC X,Y Data
FLASH Control
Memory
Video Input
Clock Manager CPU / MAC
Filter Scaler Subpicture Decode
Scaler
MPEG Decoder Dataflow Engine Audio I/O
VLC Parser IDCT DMA / BitBlit PCM Out
System Controls
RAM MoCo SRAM Buffer PCM In
STC
Video Processor Interrupts XMT958
External I/Os
On-Screen Display Registers
Remote Input A/V Bus
Picture-in-Picture
GPIOs ATAPI-IDE
Video/Graphics Display SDRAM Local Bus
This document contains information for a new product.
Preliminary Product Information Cirrus Logic reserves the right to modify this product without notice.
11
CS98000
6. PIN DESCRIPTION
H_D_[15:0] M_A_[11:0]
H_CS_[3:0] M_BS_L
H_A_[4:0] M_D_[31:0]
H_ALE M_DQM_[3:0]
Host/Loader H_RD M_RAS_L Memory IF
H_WR M_CAS_L
(30) H_CKO M_WE_L (57)
H_RDY M_AP
M_CKE
M_CKO
VIN_D[7:0]
NVR_OE_L
VIN_HSNC
Video In VIN_VSNC
NVR_WR_L
(12) VIN_CLK
VIN_FLD
CS98000 HSYNC
VSYNC Video out
CLK27_O
CDC_DI VDAT_[7:0] (11)
CODEC IF CDC_DO
CDC_RST AUD_BCK DAC Out
(5) CDC_CK AUD_LRCK
CDC_SY AUD_DO_[3:0] (7)
SPDIF_O
XTLCLOCK
MISC. RST_N AIN_BCK ADC In
IR_IN AIN_LRCK
(41) MFG_TST AIN_DATA (3)
GPIO_D[20-0]
GPIO_H[16-14]
GPIO_V10
GPIO_[15-10, 8-7, 4-2, 0]
Table 5 lists the conventions used to identify the pin type and direction in the table that follows.
I Input
IS Input, with schmitt trigger
ID Input, with pull down resistor
IU Input, with pull up resistor
O Output
O4 Output 4mA drive
O8 Output 8mA drive
T4 Tri-State-able Output 4mA drive
B Bi-direction
B4 Bi-direction 4mA drive
B4U Bi-direction 4mA drive, with pull-up
B8U Bi-direction 8mA drive, with pull-up
B4S Bi-direction 4mA drive, with schmitt trigger
B4SU Bi-direction 4mA drive, with pull-up and schmitt trigger
Pwr +2.5V or +3.3V power supply voltage
Gnd Power supply ground
Name_N Low active
Name_L Low active
Table 5. Pin Type legend
12
CS98000
6.1 Pin Assignments pins. For some signal pins, a secondary function
Table 6 lists the pin number, pin name and pin type and direction are also shown. For pins having more
for the 208 pin CS98000 package. The primary than one function, the primary function is chosen
function and pin direction is shown for all signal when the chip is reset.
Pin Name Type Primary Function Dir Secondary Function Dir Note
1 VDD_PLL Pwr PLL Power 2.5V
2 M_A_11 O8 SDRAM Address[11] O ROM/NVRAM Address[11] O
3 M_A_10 O8 SDRAM Address[10] O ROM/NVRAM Address[10] O
4 GPIO_D18 B4U GenioDVD[18] B System Clock PLL Bypass I
5 M_A_9 O8 SDRAM Address[9] O ROM/NVRAM Address[9] O
6 M_A_8 O8 SDRAM Address[8] O ROM/NVRAM Address8] O
7 M_A_7 O8 SDRAM Address[7] O ROM/NVRAM Address[7] O
8 GPIO_D16 B4SU GenioDVD[16] B
9 M_A_6 O8 SDRAM Address[6] O ROM/NVRAM Address[6] O
10 M_A_5 O8 SDRAM Address[5] O ROM/NVRAM Address[5] O
11 M_A_4 O8 SDRAM Address[4] O ROM/NVRAM Address[4] O
12 GPIO_D17 B4U GenioDVD[17] B
13 M_A_3 O8 SDRAM Address[3] O ROM/NVRAM Address[3] O
14 M_A_2 O8 SDRAM Address[2] O ROM/NVRAM Address[2] O
15 M_A_1 O8 SDRAM Address[1] O ROM/NVRAM Address[1] O
16 M_A_0 O8 SDRAM Address[0] O ROM/NVRAM Address[0] O
17 GPIO_D19 B4U GenioDVD[19] B Memory Clock PLL Bypass I
18 VSS_IO Gnd I/O Ground
19 M_CKO O8 SDRAM Clock O
20 VDD_IO Pwr I/O Power 3.3V
21 M_BS_L O8 SDRAM Bank Select O
22 M_CKE B8 SDRAM Clock Enable O GenioMis(7) B
23 M_AP O8 SDRAM Auto Pre-charge O
24 M_RAS_L O8 SDRAM Row Strobe O
25 M_CAS_L O8 SDRAM Column Strobe O
26 GPIO_D20 B4U GenioDVD[20] B
27 M_WE_L O8 SDRAM Write Enable O
28 M_DQM_0 O8 SDRAM DQM[0] O
29 M_DQM_1 O8 SDRAM DQM[1] O
30 GPIO_D0 B4U GenioDVD[0] B
31 M_DQM_2 O8 SDRAM DQM[2] O
32 M_DQM_3 O8 SDRAM DQM[3] O
33 M_D_8 B8U SDRAM Data[8] B ROM/NVRAM Data[8] B
34 GPIO_D1 B4U GenioDVD[1] B
35 VSS_IO Gnd I/O Ground
Table 6. Pin assignments
13
CS98000
36 VSS_CORE Gnd Core Ground
37 M_D_7 B8U SDRAM Data[7] B ROM/NVRAM Data[7] B
38 VDD_IO Pwr I/O Power 3.3V
39 GPIO_D2 B4U GenioDVD[2] B
40 M_D_9 B8U SDRAM Data[9] B ROM/NVRAM Data[9] B
41 VDD_CORE Pwr Core Power 2.5V
42 M_D_6 B8U SDRAM Data[6] B ROM/NVRAM Data[6] B
43 GPIO_D3 B4U GenioDVD[3] B
44 M_D_10 B8U SDRAM Data[10] B ROM/NVRAM Data[10] B
45 M_D_5 B8U SDRAM Data[5] B ROM/NVRAM Data[5] B
46 M_D_11 B8U SDRAM Data[11] B ROM/NVRAM Data[11] B
47 GPIO_D4 B4U GenioDVD[4] B
48 M_D_4 B8U SDRAM Data[4] B ROM/NVRAM Data[4] B
49 M_D_12 B8U SDRAM Data[12] B ROM/NVRAM Data[12] B
50 GPIO_D5 B4U GenioDVD[5] B
51 M_D_3 B8U SDRAM Data[3] B ROM/NVRAM Data[3] B
52 UNUSED may leave unconnected
53 UNUSED may leave unconnected
54 M_D_13 B8U SDRAM Data[13] B ROM/NVRAM Data[13] B
55 M_D_2 B8U SDRAM Data[2] B ROM/NVRAM Data[2] B
56 M_D_14 B8U SDRAM Data[14] B ROM/NVRAM Data[14] B
57 GPIO_D6 B4U GenioDVD[6] B
58 VSS_IO Gnd I/O Ground
59 M_D_1 B8U SDRAM Data[1] B ROM/NVRAM Data[1] B
60 M_D_15 B8U SDRAM Data[15] B ROM/NVRAM Data[15] B
61 GPIO_D7 B4U GenioDVD[7] I B
62 M_D_0 B8U SDRAM Data[0] B ROM/NVRAM Data[0] B
63 VSS_CORE Gnd Core Ground
64 M_D_24 B8U SDRAM Data[24] B ROM/NVRAM Address[20] O
65 GPIO_D11 B4U GenioDVD[11] B
66 VDD_CORE Pwr Core Power 2.5V
67 M_D_23 B8U SDRAM Data[23] B ROM/NVRAM Address[19] O
68 M_D_25 B8U SDRAM Data[23] B ROM/NVRAM Address[21] O
69 GPIO_D10 B4U GenioDVD[10] B
70 M_D_22 B8U SDRAM Data[22] B ROM/NVRAM Address[18] O
71 M_D_26 B8U SDRAM Data[26] B ROM/NVRAM Address[22] O
72 M_D_21 B8U SDRAM Data[21] B ROM/NVRAM Address[17] O
73 GPIO_D9 B4U GenioDVD[9] B
74 M_D_27 B8U SDRAM Data[27] B ROM/NVRAM Address[23] O
75 M_D_20 B8U SDRAM Data[20] B ROM/NVRAM Address[16] O
76 M_D_28 B8U SDRAM Data[28] B
Table 6. Pin assignments (Continued)
14
CS98000
77 GPIO_D8 B4U GenioDVD[8] B
78 M_D_19 B8U SDRAM Data[19] B ROM/NVRAM Address[15] O
79 M_D_29 B8U SDRAM Data[29] B
80 M_D_18 B8U SDRAM Data[18] B ROM/NVRAM Address[14] O
81 NV_WE_L B4U NVRAM Write Enable O GenioMis[8] B
82 VSS_CORE Gnd Core Ground
83 M_D_30 B8U SDRAM Data[30] B ROM/NVRAM Decode Low O
84 VDD_CORE Pwr Core Power 2.5V
85 H_ALE B4U Host Address Latch O GenioHst[13] B
86 M_D_17 B8U SDRAM Data[18] B ROM/NVRAM Address[13] O
87 M_D_31 B8U SDRAM Data[31] B ROM/NVRAM Decode High O
88 M_D_16 B8U SDRAM Data[16] B ROM/NVRAM Address[12] O
89 GPIO_H14 B4U GenioHst[14] B
90 NV_OE_L O4 ROM/NVRAM Output O
Enable
91 VDD_IO Pwr I/O Power 3.3V
92 H_RD B4S Host Read Strobe O DVD Data Strobe I 1
93 H_WR B4 Host Write Strobe O DVD Data Enable I 1
94 GPIO_H15 B4U GenioHst[15] B
95 H_RDY B4 Host Ready I DVD Data Ready O 1
96 VSS_IO Gnd I/O Ground
97 H_A_2 B4 Host Address[2] O GenioHst[10] B 1
98 GPIO_H16 B4U GenioHst[16] B
99 H_A_1 B4 Host Address[1] O GenioHst[9] B 1
100 H_A_0 B4 Host Address[0] O GenioHst[8] B 1
101 H_CS_1 B4 Host Chip Select [1] O DVD Error I 1
102 H_A_4 B4 Host Address[4] O GenioHst[12] B 1
103 VSS_CORE Gnd Core Ground
104 VSS_PLL Gnd PLL Ground
105 VDD_PLL Pwr PLL Power 2.5V
106 H_CS_0 B4 Host Chip Select[0] O DVD Start Sector I 1
107 H_A_3 B4 Host Address[3] O GenioHst[11] B 1
108 VDD_CORE Pwr Core Power 2.5V
109 H_D_15 B4 Host Data[15] B CD Data I 1, 2
110 H_D_14 B4 Host Data[14] B CD Left Right Clock I 1, 2
111 H_CS_3 B4 Host Chip Select[3] O GenioHst[18] B 1
112 H_D_13 B4S Host Data[13] B CD Clock I 1, 2
113 H_D_12 B4 Host Data[12] B CD Error I 1, 2
114 H_D_11 B4 Host Data[11] B DVD Control Data In I 1, 2
115 H_CS_2 B4 Host Chip Select[2] O GenioHst[17] B 1
116 H_D_10 B4 Host Data[10] B DVD Control Data Out O 1, 2
Table 6. Pin assignments (Continued)
15
CS98000
117 H_D_9 B4 Host Data[9] B DVD Control Ready I 1, 2
118 H_D_8 B4 Host Data[8] B DVD Control Clock O 1, 2
119 VSS_IO Gnd I/O Ground
120 H_CKO B4 Host Clock O GenioHst[19] B 1
121 H_D_7 B4 Host Data[7] B DVD Data[7] I 1
122 H_D_6 B4 Host Data[6] B DVD Data[6] I 1
123 H_D_5 B4 Host Data[5] B DVD Data[5] I 1
124 AUD_BCK B4 Audio Out Bit Clock O GenioMis[3] B
125 H_D_4 B4 Host Data[4] B DVD Data[4] I 1
126 VSS_CORE Gnd Core Ground
127 H_D_3 B4 Host Data[3] B DVD Data[3] I 1
128 AUD_LRCK O4 Audio Out LR Clock O
129 VDD_CORE Pwr Core Power 2.5V
130 H_D_2 B4 Host Data[2] B DVD Data[2] I 1
131 VDD_IO Pwr I/O Power 3.3V
132 H_D_1 B4 Host Data[1] B DVD Data[1] I 1
133 AUD_DO_2 B4 Audio Out Data[2] O GenioMis[2] B
134 H_D_0 B4 Host Data[0] B DVD Data[0] I 1
135 AUD_DO_0 O4 Audio Out Data[0] O
136 AUD_DO_1 B4 Audio Out Data[1] O GenioMis[1] B
137 AIN_BCK IU Audio In Bit Clock I
138 VSS_CORE Gnd Core Ground
139 AIN_LRCK IU Audio In LR Clock I
140 AIN_DATA B4U Audio In Data I GenioMis[0] B
141 VDD_CORE Pwr Core Power 2.5V
142 CDC_DI IU Serial CODEC Data In I
143 VSS_IO Gnd I/O Ground
144 CDC_DO T4 Serial CODEC Data Out O
145 VIN_CLK IU Video Input Clock I
146 CDC_RST T4 Serial CODEC Reset O
147 CDC_CK IU Serial CODEC Bit Clock I
148 CDC_SY B4U Serial CODEC Sync B
149 GPIO_V10 B4U GenioMis[26] B
150 GPIO_D15 B4U GenioDvd[15]
151 GPIO_D14 B4U GenioDvd[14]
152 GPIO_D13 B4SU GenioDvd[13]
153 VIN_VSNC B4U Video Input Vsync I GenioMis[25] B
154 CLK27_O B4U Video Output Clock O GenioMis[6] B
155 GPIO_D12 B4U GenioDvd[12]
156 VDD_PLL Pwr PLL Power 2.5V
157 VSS_PLL Gnd PLL Ground
Table 6. Pin assignments (Continued)
16
CS98000
158 VSS_CORE Gnd Core Ground
159 HSYNC B4U Video Output Hsync O GenioMis[4] B
160 VIN_HSYNC B4U Video Input Hsync I GenioMis[24] B
161 VDD_CORE Pwr Core Power 2.5V
162 VSYNC B4U Video Output Vsync O GenioMis[5] B
163 VDAT_0 O4 Video Output Data[0] O
164 VIN_D0 B4U Video Input Data[0] I GenioMis[16] B
165 VDAT_1 O4 Video Output Data[1] O
166 VDAT_2 O4 Video Output Data[2] O
167 VDAT_3 O4 Video Output Data[3] O
168 VIN_D1 B4U Video Input Data[1] I GenioMis[17] B
169 VDAT_4 O4 Video Output Data[4] O
170 VDAT_5 O4 Video Output Data[5] O
171 UNUSED may leave unconnected
172 VDAT_6 O4 Video Output Data[6] O
173 VDAT_7 O4 Video Output Data[7] O
174 GPIO_0 B4U General Purpose IO[0] B Audio PLL Input Bypass I
175 VIN_D2 B4U Video Input Data[2] I GenioMis[18] B
176 VSS_CORE Gnd Core Ground
177 AUD_DO_3 B4U Audio Out Data[3] O General Purpose IO[1] B
178 VDD_CORE Pwr Core Power 2.5V
179 VIN_D3 B4U Video Input Data[3] I GenioMis[19] B
180 VDD_IO Pwr I/O Power 3.3V
181 GPIO_2 B4U General Purpose IO[2] B
182 VSS_IO Gnd I/O Ground
183 GPIO_3 B4U General Purpose IO[3] B
184 VIN_D4 B4U Video Input Data[4] I GenioMis[20] B
185 GPIO_4 B4U General Purpose IO[4] B
186 SCL B4U I2C Clock B General Purpose IO[5] B
2
187 SDA B4U I C Data B General Purpose IO[6] B
188 GPIO_7 B4U General Purpose IO[7] B
189 VIN_D5 B4U Video Input Data[5] I GenioMis[21] B
190 GPIO_8 B4U General Purpose IO[8] B
191 AUD_XCLK B4U Audio 256x/384x Clock B General Purpose IO[9] B
192 GPIO_10 B4U General Purpose IO[10] B
193 VIN_D6 B4U Video Input Data[6] I GenioMis[22] B
194 GPIO_11 B4U General Purpose IO[11] B
195 GPIO_12 B4U General Purpose IO[12] B
196 GPIO_13 B4U General Purpose IO[13] B
197 GPIO_14 B4U General Purpose IO[14] B
198 VIN_D7 B4U Video Input Data[7] I GenioMis[23] B
Table 6. Pin assignments (Continued)
17
CS98000
158 VSS_CORE Gnd Core Ground
159 HSYNC B4U Video Output Hsync O GenioMis[4] B
160 VIN_HSYNC B4U Video Input Hsync I GenioMis[24] B
161 VDD_CORE Pwr Core Power 2.5V
162 VSYNC B4U Video Output Vsync O GenioMis[5] B
163 VDAT_0 O4 Video Output Data[0] O
164 VIN_D0 B4U Video Input Data[0] I GenioMis[16] B
165 VDAT_1 O4 Video Output Data[1] O
166 VDAT_2 O4 Video Output Data[2] O
167 VDAT_3 O4 Video Output Data[3] O
168 VIN_D1 B4U Video Input Data[1] I GenioMis[17] B
169 VDAT_4 O4 Video Output Data[4] O
170 VDAT_5 O4 Video Output Data[5] O
171 UNUSED may leave unconnected
172 VDAT_6 O4 Video Output Data[6] O
173 VDAT_7 O4 Video Output Data[7] O
174 GPIO_0 B4U General Purpose IO[0] B Audio PLL Input Bypass I
175 VIN_D2 B4U Video Input Data[2] I GenioMis[18] B
176 VSS_CORE Gnd Core Ground
177 AUD_DO_3 B4U Audio Out Data[3] O General Purpose IO[1] B
178 VDD_CORE Pwr Core Power 2.5V
179 VIN_D3 B4U Video Input Data[3] I GenioMis[19] B
180 VDD_IO Pwr I/O Power 3.3V
181 GPIO_2 B4U General Purpose IO[2] B
182 VSS_IO Gnd I/O Ground
183 GPIO_3 B4U General Purpose IO[3] B
184 VIN_D4 B4U Video Input Data[4] I GenioMis[20] B
185 GPIO_4 B4U General Purpose IO[4] B
186 SCL B4U I2C Clock B General Purpose IO[5] B
2
187 SDA B4U I C Data B General Purpose IO[6] B
188 GPIO_7 B4U General Purpose IO[7] B
189 VIN_D5 B4U Video Input Data[5] I GenioMis[21] B
190 GPIO_8 B4U General Purpose IO[8] B
191 AUD_XCLK B4U Audio 256x/384x Clock B General Purpose IO[9] B
192 GPIO_10 B4U General Purpose IO[10] B
193 VIN_D6 B4U Video Input Data[6] I GenioMis[22] B
194 GPIO_11 B4U General Purpose IO[11] B
195 GPIO_12 B4U General Purpose IO[12] B
196 GPIO_13 B4U General Purpose IO[13] B
197 GPIO_14 B4U General Purpose IO[14] B
198 VIN_D7 B4U Video Input Data[7] I GenioMis[23] B
Table 6. Pin assignments (Continued)
18
EM638165
Pin Descriptions
Table 1. Pin Details of EM638165
Symbol Type Description
CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal burst
counter and controls the output registers.
CKE Input Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal. If
CKE goes low synchronously with clock(set-up and hold time same as other
inputs), the internal clock is suspended from the next clock cycle and the state
of output and burst address is frozen as long as the CKE remains low. When all
banks are in the idle state, deactivating the clock controls the entry to the Power
Down and Self Refresh modes. CKE is synchronous except after the device
enters Power Down and Self Refresh modes, where CKE becomes
asynchronous until exiting the same mode. The input buffers, including CLK,
are disabled during Power Down and Self Refresh modes, providing low
standby power.
BA0,BA1 Input Bank Select: BA0,BA1 input select the bank for operation.
BA1 BA0 Select Bank
0 0 BANK #A
0 1 BANK #B
1 0 BANK #C
1 1 BANK #D
A0-A11 Input Address Inputs: A0-A11 are sampled during the BankActivate command (row
address A0-A11) and Read/Write command (column address A0-A7 with A10
defining Auto Precharge) to select one location out of the 2M available in the
respective bank. During a Precharge command, A10 is sampled to determine if
all banks are to be precharged (A10 = HIGH). The address inputs also provide
the op-code during a Mode Register Set command.
CS# Input Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the
command decoder. All commands are masked when CS# is sampled HIGH.
CS# provides for external bank selection on systems with multiple banks. It is
considered part of the command code.
RAS# Input Row Address Strobe: The RAS# signal defines the operation commands in
conjunction with the CAS# and WE# signals and is latched at the positive edges
of CLK. When RAS# and CS# are asserted "LOW" and CAS# is asserted
"HIGH," either the BankActivate command or the Precharge command is
selected by the WE# signal. When the WE# is asserted "HIGH," the
BankActivate command is selected and the bank designated by BS is turned on
to the active state. When the WE# is asserted "LOW," the Precharge command
is selected and the bank designated by BS is switched to the idle state after the
precharge operation.
CAS# Input Column Address Strobe: The CAS# signal defines the operation commands in
conjunction with the RAS# and WE# signals and is latched at the positive edges
of CLK. When RAS# is held "HIGH" and CS# is asserted "LOW," the column
access is started by asserting CAS# "LOW." Then, the Read or Write command
is selected by asserting WE# "LOW" or "HIGH."
19
EM638165
Pin Descriptions
Table 1. Pin Details of EM638165
Symbol Type Description
CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal burst
counter and controls the output registers.
CKE Input Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal. If
CKE goes low synchronously with clock(set-up and hold time same as other
inputs), the internal clock is suspended from the next clock cycle and the state
of output and burst address is frozen as long as the CKE remains low. When all
banks are in the idle state, deactivating the clock controls the entry to the Power
Down and Self Refresh modes. CKE is synchronous except after the device
enters Power Down and Self Refresh modes, where CKE becomes
asynchronous until exiting the same mode. The input buffers, including CLK,
are disabled during Power Down and Self Refresh modes, providing low
standby power.
BA0,BA1 Input Bank Select: BA0,BA1 input select the bank for operation.
BA1 BA0 Select Bank
0 0 BANK #A
0 1 BANK #B
1 0 BANK #C
1 1 BANK #D
A0-A11 Input Address Inputs: A0-A11 are sampled during the BankActivate command (row
address A0-A11) and Read/Write command (column address A0-A7 with A10
defining Auto Precharge) to select one location out of the 2M available in the
respective bank. During a Precharge command, A10 is sampled to determine if
all banks are to be precharged (A10 = HIGH). The address inputs also provide
the op-code during a Mode Register Set command.
CS# Input Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the
command decoder. All commands are masked when CS# is sampled HIGH.
CS# provides for external bank selection on systems with multiple banks. It is
considered part of the command code.
RAS# Input Row Address Strobe: The RAS# signal defines the operation commands in
conjunction with the CAS# and WE# signals and is latched at the positive edges
of CLK. When RAS# and CS# are asserted "LOW" and CAS# is asserted
"HIGH," either the BankActivate command or the Precharge command is
selected by the WE# signal. When the WE# is asserted "HIGH," the
BankActivate command is selected and the bank designated by BS is turned on
to the active state. When the WE# is asserted "LOW," the Precharge command
is selected and the bank designated by BS is switched to the idle state after the
precharge operation.
CAS# Input Column Address Strobe: The CAS# signal defines the operation commands in
conjunction with the RAS# and WE# signals and is latched at the positive edges
of CLK. When RAS# is held "HIGH" and CS# is asserted "LOW," the column
access is started by asserting CAS# "LOW." Then, the Read or Write command
is selected by asserting WE# "LOW" or "HIGH."
20
EM638165
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 2 shows the truth table for the operation commands.
Table 2. Truth Table (Note (1), (2) )
Command State CKEn-1 CKEn DQM BA0,1 A10 A0-9,11 CS# RAS# CAS# WE#
BankActivate Idle(3) H X X V Row address L L H H
BankPrecharge Any H X X V L X L L H L
PrechargeAll Any H X X X H X L L H L
Write Active(3) H X X V L Column L H L L
address
Write and AutoPrecharge Active(3) H X X V H (A0 ~ A7) L H L L
Read Active(3) H X X V L Column L H L H
address
Read and Autoprecharge Active(3) H X X V H (A0 ~ A7) L H L H
Mode Register Set Idle H X X OP code L L L L
No-Operation Any H X X X X X L H H H
Burst Stop Active(4) H X X X X X L H H L
Device Deselect Any H X X X X X H X X X
AutoRefresh Idle H H X X X X L L L H
SelfRefresh Entry Idle H L X X X X L L L H
SelfRefresh Exit Idle L H X X X X H X X X
(SelfRefresh) L H H H
Clock Suspend Mode Entry Active H L X X X X X X X X
Power Down Mode Entry Any(5) H L X X X X H X X X
L H H H
Clock Suspend Mode Exit Active L H X X X X X X X X
Power Down Mode Exit Any L H X X X X H X X X
(PowerDown) L H H H
Data Write/Output Enable Active H X L X X X X X X X
Data Mask/Output Disable Active H X H X X X X X X X
Note: 1. V=Valid X=Don't Care L=Low level H=High level
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BS signal.
4. Device state is 1, 2, 4, 8, and full page burst operation.
5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.
21
EM638165
Commands
1 BankActivate
(RAS# = "L", CAS# = "H", WE# = "H", BAs = Bank, A0-A11 = Row Address)
The BankActivate command activates the idle bank designated by the BA0,1 signals. By
latching the row address on A0 to A11 at the time of this command, the selected row access is
initiated. The read or write operation in the same bank can occur after a time delay of tRCD(min.)
from the time of bank activation. A subsequent BankActivate command to a different row in the
same bank can only be issued after the previous active row has been precharged (refer to the
following figure). The minimum time interval between successive BankActivate commands to the
same bank is defined by tRC(min.). The SDRAM has four internal banks on the same chip and
shares part of the internal circuitry to reduce chip area; therefore it restricts the back-to-back
activation of the four banks. tRRD(min.) specifies the minimum time required between activating
different banks. After this command is used, the Write command and the Block Write command
perform the no mask write operation.
T0 T1 T2 T3 Tn+3 Tn+4 Tn+5 Tn+6
CLK ..............
ADDRESS Bank A Bank A .............. Bank B Bank A
Row Addr. Col Addr. Row Addr. Row Addr.
RAS# - CAS# delay (tRCD) RAS# - RAS# delay time (tRRD)
COM MAND Bank A NOP NOP
R/W A with .............. Bank B NOP NOP Bank A
Activate AutoPrecharge Activate Activate
RAS# Cycle time (tRC)
AutoPrecharge
Begin
: "H" or "L"
BankActivate Command Cycle (Burst Length = n, CAS# Latency = 3)
2 BankPrecharge command
(RAS# = "L", CAS# = "H", WE# = "L", BAs = Bank, A10 = "L", A0-A9 and A11 = Don't care)
The BankPrecharge command precharges the bank disignated by BA signal. The precharged
bank is switched from the active state to the idle state. This command can be asserted anytime after
tRAS(min.) is satisfied from the BankActivate command in the desired bank. The maximum time any
bank can be active is specified by tRAS(max.). Therefore, the precharge function must be performed
in any active bank within tRAS(max.). At the end of precharge, the precharged bank is still in the idle
state and is ready to be activated again.
3 PrechargeAll command
(RAS# = "L", CAS# = "H", WE# = "L", BAs = Don't care, A10 = "H", A0 -A9 and A11 = Don't care)
The PrechargeAll command precharges all banks simultaneously and can be issued even if all
banks are not in the active state. All banks are then switched to the idle state.
4 Read command
(RAS# = "H", CAS# = "L", WE# = "H", BAs = Bank, A10 = "L", A0-A7 = Column Address)
The Read command is used to read a burst of data on consecutive clock cycles from an active
row in an active bank. The bank must be active for at least tRCD(min.) before the Read command is
issued. During read bursts, the valid data-out element from the starting column address will be
available following the CAS# latency after the issue of the Read command. Each subsequent data-
out element will be valid by the next positive clock edge (refer to the following figure). The DQs go
into high-impedance at the end of the burst unless other command is initiated. The burst length,
burst sequence, and CAS# latency are determined by the mode register, which is already
programmed. A full-page burst will continue until terminated (at the end of the page it will wrap to
column 0 and continue).
22
23
24
25
26
27
28
29
30
CS92288 MPEG-2 AUDIO/VIDEO CODEC DATA BOOK
IMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet
available. "Advance" product information describes products that are in development and subject to development changes.
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reli-
able. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind
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Preliminary Information - Confidential
An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or
technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported
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exported or taken out of the PRC.
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Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product
names in this document may be trademarks or service marks of their respective owners.
Use of this product in any manner that complies with the MPEG-2 video standard as defined in ISO documents IS 13818-1
(including annexes C, D, F, J, and K), IS 13818-2 (including annexes A, B, C, and D, but excluding scalable extensions), and
IS 13818-4 (only as it is needed to clarify IS 13818-2) is expressly prohibited without a license under applicable patents in the
MPEG-2 patent portfolio, which license is available from MPEG LA, L.L.C. 250 Steele Street, Suite 300, Denver, Colorado
80296.
31
CS92288 MPEG-2 AUDIO/VIDEO CODEC DATA BOOK
Overview
The CS92288 is a real time MPEG-2 audio/video encoder and decoder (CODEC), with system multiplexor/demultiplexor and
on-screen display (OSD). For video coding, the CS92288 fully complies with the ISO/IEC 13818 Main Level @ Main Profile
(ML@MP) or with the ISO/IEC 11172 (MPEG-1) formats. For audio encoding, the CS92288 supports a variety of audio for-
mats, including MPEG-1 or MPEG-2 audio (all Layers) and Dolby Digital (AC-3).
In encode mode, the CS92288 accepts digital video in ITU-R BT.601 (CCIR-601) or ITU-R BT.656 (CCIR-656) formats, and
digital audio in LPCM format. The input video is filtered and then encoded to produce a compressed bitstream in either
MPEG-1 or MPEG-2 ML@MP syntax. The audio is compressed in either MPEG or Dolby Digital formats. The compressed
video and audio streams are multiplexed to produce an MPEG-compliant program bit stream.
In decode mode, the CS92288 accepts an MPEG program bit stream or audio and video elementary streams and produces ITU-
R BT.601 or BT.656 video and LPCM audio outputs.
The CS92288 is designed to provide a high degree of integration and ease of system design. It makes an ideal solution for a
Preliminary Information - Confidential
variety of MPEG-based audio/visual applications, such as PC-based content creation, VCD and DVD-RAM players/recorders,
set-top boxes, and time-shift recording. For example, a single CS92288 is adequate for a complete Super VCD (SVCD) player/
recorder.
For the evaluation of the CS92288, Cirrus Logic provides a PC-based Evaluation Board, window drivers, and application soft-
ware. In addition, Cirrus Logic offers a complete reference design for a stand-alone MPEG-based video recorder/player. This
design allows designers and manufacturers a quick entry to the digital recording markets.
Features
· Single Chip Real Time MPEG-2 Audio/Video CODEC with system Mux/Demux and On-screen Display (OSD)
· Supports MPEG-1 audio/video encoding and decoding
· Supports Dolby Digital audio encoding and decoding
· Programmable system mux/demux supports DVD, VCD, and SVCD encoding and decoding
· 8-bit OSD support (2-b text, 2-b to 8-b graphics)
· Support for Constant Bit Rate (CBR) and one-pass Variable Bit Rate (VBR)
IPB-pictures, CBR (average), VBR (max) up to 15Mbps.
I-pictures only to 30Mbps
· Proprietary High Performance Motion Estimation
· Low external SDRAM memory:
8 Mbytes for D1, 2B picture format
· Supports Multiple Resolutions & Scan Rates
NTSC: (720, 704, 640, 544, 480, 352) x 480 or 352 x 240 (CIF), and 176x112 (QCIF) at 30 or 29.97 Hz
PAL: (720, 704, 640, 544, 480, 352) x 576 or 352 x 288 (CIF), and 176x144 (QCIF) at 25 Hz
· Integrated video pre and post processor
· 108 MHz operating frequency with separate 27 MHz input video clock
· Video Preprocessor
Accepts ITU-R BT.601 4:2:2 and D1 input formats
4:2:2 to 4:2:0 Conversion
Built-in, programmable, pre-processing filters
Half Horizontal Resolution (HHR), SIF decimation filtering, or Two-Thirds Horizontal resolution filtering
Temporal filtering
Automatic inverse telecine
Sync Extraction
· Video Encoder
Real Time Encoding of MPEG-2 Main Level/Main Profile digital video
· ISO/IEC 13818-2 compliant
· SP@ML, MP@LL, MP@ML
· Video Streams up to 13.5Mpels/s (16-bit) and 27Mpel/s (8-bit)
Real Time Encoding of MPEG-1
Support for Full D1, 2/3 D1, 1/2 D1, CIF, and QCIF
32
CS92288 MPEG-2 AUDIO/VIDEO CODEC DATA BOOK
Constant Bit Rate Support: up to 15Mbps (IPB frames) and 30Mbps (I frame only)
Variable Bit Rate Support:
· Real-time one-pass rate control
· User-selectable average bitrate
Proprietary High Performance Motion Estimation Engine
· Half-pel accuracy