Text preview for : tda.pdf part of AKIRA CT 21NI9 user guide, schematic, anything
Back to : tda.pdf | Home
INTEGRATED CIRCUITS
DATA SHEET
TDA9852 I2C-bus controlled BTSC stereo/SAP decoder and audio processor
Preliminary specification Supersedes data of 1996 Feb 28 File under Integrated Circuits, IC02 1997 Mar 11
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
FEATURES · Quasi alignment-free application due to automatic adjustment of channel separation via I2C-bus · High integration level with automatically tuned integrated filters · Input level adjustment I2C-bus controlled · Alignment-free SAP processing · dbx noise reduction circuit · Power supply · I2C-bus transceiver. Stereo decoder · Stereo pilot PLL circuit with ceramic resonator, automatic adjustment procedure for stereo channel separation, two pilot thresholds selectable via I2C-bus. Audio processor · Selector for internal and external signals (line in) · Automatic volume level control (control range +6 to -15 dB) · Interface for external noise reduction circuits · Volume control (control range +16 to -71 dB) · Special loudness characteristic automatically controlled in combination with volume setting (control range 28 dB) · Audio signal zero crossing detection between any volume step switching · Mute control at audio signal zero crossing · Mute control via I2C-bus. ORDERING INFORMATION TYPE NUMBER TDA9852 TDA9852H PACKAGE NAME DESCRIPTION GENERAL DESCRIPTION
TDA9852
The TDA9852 is a bipolar-integrated BTSC stereo decoder with hi-fi audio processor (I2C-bus controlled) for application in TV sets, VCRs and multimedia.
VERSION SOT270-1
SDIP42 plastic shrink dual in-line package; 42 leads (600 mil)
QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 × 10 × 1.75 mm SOT307-2
1997 Mar 11
2
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
LICENSE INFORMATION A license is required for the use of this product. For further information, please contact COMPANY THAT Corporation BRANCH Licensing Operations
TDA9852
ADDRESS 734 Forest St. Marlborough, MA 01752 USA Tel.: (508) 229-2500 Fax: (508) 229-2590 405 Palm House, 1-20-2 Honmachi Shibuya-ku, Tokyo 151 Japan Tel.: (03) 3378-0915 Fax: (03) 3374-5191
Tokyo Office
QUICK REFERENCE DATA SYMBOL VCC ICC VoR,L(rms) GLA cs THDL,R VI, O(rms) AVL GC LB S/N PARAMETER supply voltage supply current CONDITIONS MIN. 8.0 - 100% modulation L + R; fi = 300 Hz - -3.5 fL = 300 Hz; fR = 3 kHz fi = 1 kHz THD < 0.5% 25 - 2 -15 -71 fi = 40 Hz line out (mono); Vo = 0.5 V (RMS) CCIR noise weighting filter (peak value) DIN noise weighting filter (RMS value) S/N signal-to-noise ratio audio section; Vo = 2 V (RMS); gain = 0 dB CCIR noise weighting filter (peak value) DIN noise weighting filter (RMS value) - - 94 107 - - dB dBA - - 60 73 - - dB dBA - TYP. 8.5 75 250 500 - 35 0.2 - - - 17 MAX. 9.0 95 - - +4.0 - - - +6 +16 - UNIT V mA mV mV dB dB % V dB dB dB
Vcomp(rms) input signal voltage (RMS value) input level adjustment control stereo channel separation total harmonic distortion L + R signal handling (RMS value) control range volume control range maximum loudness boost signal-to-noise ratio
output signal voltage (RMS value) 100% modulation L + R; fi = 300 Hz -
1997 Mar 11
3
handbook, full pagewidth
1997 Mar 11
External Input Right (EIR) C3 C2 R1 C4 C5 Q1 CERAMIC RESONATOR MURATA CSB503F58
29 30 (25) (26)
BLOCK DIAGRAM
Philips Semiconductors
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
C11 C16 C20 C7 C6 LOR LIR 31 (27) 32 (28) 33 (29) 36 (32) 34 (30) 35 (31) 5 (44) 37 (33) 38 39 (34) (35) C28 C8 C9 C10
R2
R3
C12 VIR 40 (36) 41 (37) OUT RIGHT
(38) 42 OUTR
26 27 (22) (23)
28 (24)
STEREO DECODER
TDA9852
VOLUME RIGHT LOUDNESS CONTROL
COMP C1
(20) 24
INPUT LEVEL ADJUST
STEREO/ SAP SWITCH
DEMATRIX + LINEOUT SELECT
INPUT SELECT
AUTOMATIC VOLUME AND LEVEL CONTROL
EFFECTS
ZERO CROSSING
4
SAP DEMODULATOR
(14) 19 (13) (12) 18 17
DBX
(10) 15 R6 (11) (9) 16 14
STEREO ADJUST
SUPPLY
(6) (5) 11 10 (2) 7 (4) 9 (3) (19) (21) (1) 8 23 25 6
LOGIC I2C TRANSCEIVER
(17) (18) (43) 4 20 (15) 21 (16) 22
VOLUME LEFT LOUDNESS CONTROL
(42) 3 (41) 2
OUT LEFT
(40) 1 OUTL
(8) 13
(7) 12
(39)
MHA309
LOL
LIL C27 C26 SDA C15 C34 SCL C30 C29
VIL C14
n.c.
C17
C18
C19
R7 C22 C23 C24 C25 C21
R4
C47 C49 VCC External Input Left (EIL)
R5
AGND
DGND
Preliminary specification
TDA9852
The numbers given in parenthesis refer to the TDA9852H version.
Fig.1 Block diagram.
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
TDA9852
Component list Electrolytic capacitors ±20%; foil or ceramic capacitors ±10%; resistors ±5%; unless otherwise specified; see Fig.1. COMPONENTS C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C34 C47 C49 R1 R2 R3 R4 R5 R6 VALUE 10 µF 470 nF 4.7 µF 220 nF 10 µF 2.2 µF 2.2 µF 15 nF 15 nF 2.2 µF 8.2 nF 150 nF 150 nF 100 µF 4.7 µF 4.7 µF 100 nF 10 µF 4.7 µF 47 nF 1 µF 1 µF 10 µF 10 µF 2.2 µF 2.2 µF 4.7 µF 2.2 µF 8.2 nF 100 µF 220 µF 100 nF 2.2 k 20 k 2.2 k 20 k 2.2 k 8.2 k TYPE electrolytic foil electrolytic foil electrolytic electrolytic electrolytic foil foil electrolytic foil or ceramic foil foil electrolytic electrolytic electrolytic foil electrolytic electrolytic foil electrolytic electrolytic electrolytic electrolytic electrolytic electrolytic electrolytic electrolytic foil or ceramic electrolytic electrolytic foil or ceramic - - - - - - ±2% 63 V 63 V ±5% 63 V 63 V 63 V ±10% 63 V ±10% 16 V 63 V 63 V ±10% 16 V ±5% SMD 2220/1206 16 V 25 V SMD 1206 63 V; Ileak < 1.5 µA 16 V 63 V ±5% ±5% 16 V ±5% SMD 2220/1206 ±5% ±5% 16 V 63 V 63 V 63 V REMARK 63 V
1997 Mar 11
5
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
COMPONENTS R7 Q1 VALUE 160 TYPE - CSB503F58 CSB503JF958 PINNING PINS SYMBOL SDIP42 OUTL LDL VIL EOL CAV Vref LIL AVL SOL LOL CTW CTS CW CS VEO VEI CNR CM CDEC GND AGND DGND SDA SCL VCC COMP VCAP CP1 CP2 CPH CADJ CER CMO 1997 Mar 11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 - - 21 22 23 24 25 26 27 28 29 30 31 QFP44 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 - 15 16 17 18 19 20 21 22 23 24 25 26 27 6 output, left channel input loudness, left channel input volume, left channel output effects, left channel automatic volume control capacitor reference voltage 0.5VCC input line control, left channel DESCRIPTION
TDA9852
REMARK ±2% radial leads alternative as SMD
input automatic volume control, left channel output selector, left channel output line control, left channel capacitor timing wideband for dbx capacitor timing spectral for dbx capacitor wideband for dbx capacitor spectral for dbx variable emphasis output for dbx variable emphasis input for dbx capacitor noise reduction for dbx capacitor mute for SAP capacitor DC-decoupling for SAP ground analog ground digital ground serial data input/output (I2C-bus) serial clock input (I2C-bus) supply voltage composite input signal capacitor for electronic filtering of supply capacitor for pilot detector capacitor for pilot detector capacitor for phase detector capacitor for filter adjustment ceramic resonator capacitor DC-decoupling mono
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
PINS SYMBOL SDIP42 CSS LOR SOR AVR LIR CPS2 CPS1 EOR VIR LDR OUTR n.c. 32 33 34 35 36 37 38 39 40 41 42 - QFP44 28 29 30 31 32 33 34 35 36 37 38 39 capacitor DC-decoupling stereo/SAP output line control, right channel output selector, right channel DESCRIPTION
TDA9852
input automatic volume control, right channel input line control, right channel capacitor 2 pseudo function capacitor 1 pseudo function output effects, right channel input volume, right channel input loudness, right channel output, right channel not connected
Vref 1 LIL 2 AVL 3 SOL 4 LOL 5 CTW 6 CTS 7 CW 8 CS 9 VEO 10 VEI 11
34 CPS1
35 EOR
44 CAV
43 EOL
37 LDR
handbook, full pagewidth
38 OUTR
40 OUTL
41 LDL
36 VIR
39 n.c.
42 VIL
33 CPS2 32 LIR 31 AVR 30 SOR 29 LOR
TDA9852H
28 CSS 27 CMO 26 CER 25 CADJ 24 CPH 23 CP2
CNR 12
CM 13
CDEC 14
AGND 15
DGND 16
SDA 17
SCL 18
VCC 19
COMP 20
VCAP 21
CP1 22
MHA696
Fig.2 Pin configuration (QFP-version).
1997 Mar 11
7
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
FUNCTIONAL DESCRIPTION Stereo decoder INPUT LEVEL ADJUSTMENT
TDA9852
handbook, halfpage
OUTL LDL VIL EOL CAV Vref LIL AVL SOL
1 2 3 4 5 6 7 8 9
42 OUTR 41 LDR 40 VIR 39 EOR 38 CPS1 37 CPS2 36 LIR 35 AVR 34 SOR 33 LOR
The composite input signal is fed to the input level adjustment stage. The control range is from -3.5 to +4.0 dB in steps of 0.5 dB. The subaddress control 3 of Tables 5 and 6 and the level adjust setting of Table 21 allows an optimum signal adjustment during the set alignment. The maximum input signal voltage is 2 V (RMS). STEREO DECODER The output signal of the level adjustment stage is coupled to a low-pass filter which suppresses the baseband noise above 125 kHz. The composite signal is then fed into a pilot detector/pilot cancellation circuit and into the MPX demodulator. The main L + R signal passes a 75 µs fixed de-emphasis filter and is fed into the dematrix circuit. The decoded sub-signal L - R is sent to the stereo/SAP switch. To generate the pilot signal the stereo demodulator uses a PLL circuit including a ceramic resonator. The stereo channel separation is adjusted by an automatic procedure to be performed during set production. For a detailed description see Section "Adjustment procedure". The stereo identification can be read by the I2C-bus (see Table 2). Two different pilot thresholds (data STS = 1; STS = 0) can be selected via the I2C-bus (see Table 19). SAP DEMODULATOR The composite signal is fed from the output of the input level adjustment stage to the SAP demodulator circuit through a 5fH (fH = horizontal frequency) band-pass filter. The demodulator level is automatically controlled. The SAP demodulator includes internal noise and field strength detectors that mute the SAP output in the event of insufficient signal conditions. The SAP identification signal can be read by the I2C-bus (see Table 2). SWITCH The stereo/SAP switch feeds either the L - R signal or the SAP demodulator output signal via the internal dbx noise reduction circuit to the dematrix/switching circuit. Table 12 shows the different switch modes provided at the output pins LOR and LOL.
LOL 10 CTW 11 CTS 12 CW 13 CS 14 VEO 15 VEI 16 CNR 17 CM 18 CDEC 19 GND 20 SDA 21
MHA310
TDA9852
32 CSS 31 CMO 30 CER 29 CADJ 28 CPH 27 CP2 26 CP1 25 VCAP 24 COMP 23 VCC 22 SCL
Fig.3 Pin configuration (SDIP-version).
1997 Mar 11
8
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
dbx DECODER The circuit includes all blocks required for the noise reduction system in accordance with the BTSC system specification. The output signal is fed through a 73 µs fixed de-emphasis circuit to the dematrix block. INTEGRATED FILTERS The filter functions necessary for stereo and SAP demodulation and part of the dbx filter circuits are provided on-chip using transconductor circuits. The required filter accuracy is attained by an automatic filter alignment circuit. Audio processor SELECTOR The selector allows selecting either the internal line out signals LOR or LOL (dematrix output) or the external line in signals LIR and LIL and combines the left and right signals in several modes (see Tables 5 and 6 for subaddress and Table 11 for data). The input signal capability of the line inputs (LIR/LIL) is 2 V (RMS). The output of the selector is AC-coupled to the automatic volume level control circuit via pins SOR/SOL and AVR/AVL to avoid offset voltages. AUTOMATIC VOLUME LEVEL CONTROL The automatic volume level stage controls its output voltage to a constant level of typically 200 mV (RMS) from an input voltage range of 0.1 to 1.1 V (RMS). The circuit adjusts variations in modulation during broadcasting and due to changes in the programme material. The function can be switched off. To avoid audible `plops' during the permanent operation of the AVL circuit a soft blending scheme has been applied between the different gain stages. A capacitor (4.7 µF) at pin CAV determines the attack and decay time constants. In addition the ratio of attack and decay time can be changed via I2C-bus (see Table 15). At power on, the discharged 4.7 µF capacitor at CAV must be loaded by the internal decay current. If AVL is chosen, this would result in an attenuated AVL gain for about 10 seconds after power on. This can be speeded up by choosing via I2C-bus an increased charge current (about 10 times higher) for about the first 2 seconds after power on (see Table 6, CCD bit in control 1 and Table 18). VOLUME/LOUDNESS EFFECTS
TDA9852
The audio processor section offers the following mode selections: linear stereo, pseudo stereo, spatial stereo and forced mono.The spatial mode provides an antiphase crosstalk of 30% or 52% (switchable via I2C-bus; see Table 10).
The volume control range is from +16 dB to -71 dB in steps of 1 dB and ends with a mute step (see Table 8). Balance control is achieved by the independent volume control of each channel. The volume control blocks operate in combination with the loudness control. The filter is linear when maximum gain for volume control is selected. The filter characteristic changes automatically over a range of 28 dB down to a setting of -12 dB. At -12 dB volume control the maximum loudness boost is obtained. The filter characteristic is determined by external components. The proposed application provides a maximum boost of 17 dB for bass and 4.5 dB for treble. The loudness may be switched on or off via I2C-bus control (see Table 9). The left and right volume control stages include two independent zero crossing detectors. A change in volume is automatically activated but not executed. The execution is enabled at the next zero crossing of the signal. If a new volume step is activated before the previous one has been processed, the previous value will be executed first, and then the new value will be activated. If no zero crossing occurs the next volume transmission will enforce the last activated volume setting. The zero crossing is realized between adjoining steps and between any steps, but not from any step to mute. In this case the GMU bit is needed to use. In case only one channel has to be muted, two steps are necessary. The first step is a transmission of any step to -71 dB and the second step is the -71 dB step to mute mode. The step of -71 dB to mute mode has no zero crossing but this is not relevant.
1997 Mar 11
9
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
MUTE The mute function can be activated independently with last step of volume control at the left or right output. By setting the general mute bit GMU via the I2C-bus all outputs are muted. All channels include an independent zero cross detector. The zero crossing mute feature can be selected via bit TZCM: TZCM = 0: forced mute with direct execution TZCM = 1: execution in time with signal zero crossing. In the zero cross mode a change in the GMU polarity is activated but not executed. The execution is enabled at the next zero crossing of the signal. To avoid a large delay of mute switching, when very low frequencies are processed, or the output signal amplitude is lower than the DC offset voltage, the following I2C-bus transmissions are needed: a first transmission for mute execution a second transmission about 100 ms later, which must switch the zero crossing mode to forced mute (TZCM = 0) a third transmission to reactivate the zero crossing mode (TZCM = 1). This transmission can take place immediately, but must follow before the next mute execution. Adjustment procedure COMPOSITE INPUT LEVEL ADJUSTMENT Feed in from FM demodulator the composite signal with 100% modulation (25 kHz deviation) L + R; fi = 300 Hz. Set input level control via I2C-bus monitoring line out (500 mV ±20 mV). Store the setting in a non-volatile memory. AUTOMATIC ADJUSTMENT PROCEDURE · Capacitors of external inputs LIL and LIR must be grounded at EIL and EIR · Composite input signal L = 300 Hz, R = 3.1 kHz, 14% modulation for each channel; volume gain +16 dB via I2C-bus · Effects, AVL, loudness off.
TDA9852
· Line out setting bits: STEREO = 1, SAP = 0 (see Table 12) · Selector setting SC0, SC1, SC2 = 0, 0, 0 (see Table 11) · Start adjustment by transmission ADJ = 1 in register ALI3; the decoder will align itself · After 1 second minimum stop alignment by transmitting ADJ = 0 in register ALI3 read the alignment data by an I2C-bus read operation from ALR1 and ALR2 (see Chapter "I2C-bus protocol") and store it in a non-volatile memory; the alignment procedure overwrites the previous data stored in ALI1 and ALI2 · Disconnect the capacitors of external inputs from ground. MANUAL ADJUSTMENT Manual adjustment is necessary when no dual tone generator is available (e.g. for service). · Spectral and wideband data have to be set to 10000 (middle position for adjustment range) · Composite input L = 300 Hz; 14% modulation · Adjust channel separation by varying wideband data · Composite input L = 3 kHz; 14% modulation · Adjust channel separation by varying spectral data · Iterative spectral/wideband operation for optimum adjustment · Store data in non-volatile memory. TIMING CURRENT FOR RELEASE RATE Due to possible internal and external spreading, the timing current can be adjusted via I2C-bus, see Table 20, as recommended by dbx.
1997 Mar 11
10
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
Requirements for the composite input signal to ensure correct system performance SYMBOL PARAMETER CONDITIONS measured at COMP MIN. 162 TYP. 250
TDA9852
MAX. 363
UNIT mV
COMPL+R(rms) composite input level for 100% modulation L + R; 25 kHz deviation; fi = 300 Hz; RMS value COMP composite input level spreading under operating conditions output impedance low frequency roll-off high frequency roll-off total harmonic distortion L + R
Tamb = -20 to +70 °C; aging; power supply influence note 1 25 kHz deviation L + R; -2 dB 25 kHz deviation L + R; -2 dB fi = 1 kHz; 25 kHz deviation fi = 1 kHz; 125 kHz deviation; note 2
-0.5
-
+0.5
dB
Zo flf fhf THDL,R
- - 100 - -
low-ohmic 5 - - - - 5 - 0.5 1.5
k Hz kHz % %
S/N
signal-to-noise ratio L + R/noise
CCIR 468-2 weighted quasi peak; L + R; 25 kHz deviation; fi = 1 kHz; 75 µs de-emphasis critical picture modulation; note 3 with sync only 44 54 - - - - - - dB dB dB
SB
side band suppression mono into unmodulated SAP carrier; SAP carrier/side band spectral spurious attenuation L + R/spurious
mono signal: 25 kHz deviation, 46 fi = 1 kHz; side band: SAP carrier frequency ±1 kHz 50 Hz to 100 kHz; mainly n × fH; no de-emphasis; L + R; 25 kHz deviation, f = 1 kHz as reference n = 1, 5 n = 4, 6 n = 2, 3 35 40 26
SP
- - -
- - -
dB dB dB
Notes 1. Low-ohmic preferred, otherwise the signal loss and spreading at COMP, caused by Zo and the composite input impedance (see Chapter "Characteristics", Section "Input level adjustment control") must be taken into account. 2. In order to prevent clipping at over-modulation (maximum deviation in the BTSC system for 100% modulation is 73 kHz). 3. For example colour bar or flat field white; 100% video modulation.
1997 Mar 11
11
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VCC Vn Tamb Tstg Ves Note supply voltage voltage of all other pins to pin VCC operating ambient temperature storage temperature electrostatic handling; note 1 PARAMETER 0 0 -20 -65 MIN. 9.5 VCC +70 +150 MAX.
TDA9852
UNIT V V °C °C
1. Human body model: C = 100 pF; R = 1.5 k; V = 2 kV; Charge device model: C = 200 pF; R = 0 ; V = 300 V. THERMAL CHARACTERISTICS SYMBOL Rth j-a SOT270-1 SOT307-2 PARAMETER thermal resistance from junction to ambient in free air 43 60 K/W K/W VALUE UNIT
1997 Mar 11
12
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
TDA9852
CHARACTERISTICS All voltages are measured relative to GND; VCC = 8.5 V; Rs = 600 ; RL = 10 k; CL = 2.5 nF; AC-coupled; fi = 1 kHz; Tamb = 25 °C; gain control Gv = 0 dB; balance in mid position; loudness off; see Fig.1; unless otherwise specified. SYMBOL General VCC ICC Vref supply voltage supply current internal reference voltage at pin Vref input level adjustment control step resolution maximum input voltage level (RMS value) input impedance 8.0 - - 8.5 75 4.25 9.0 95 - V mA V PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Input level adjustment control GLA Gstep Vi(rms) Zi -3.5 - 2 29.5 input level adjusted via I2C-bus - (L + R; fi = 300 Hz); monitoring LINE OUT - - 0.5 - 35 +4.0 - - 40.5 - dB dB V k
Stereo decoder MPXL+R(rms) input voltage level for 100% modulation L + R; 25 kHz deviation (RMS value) MPXL-R input voltage level for 100% modulation L - R; 50 kHz deviation (peak value) maximum headroom for L + R, fmod < 15 kHz; THD < 15% L, R 250 mV
707
-
mV
MPX(max)
9 -
- 50 - - - - 2.5 500
- - 35 30 - - - 520
dB mV mV mV mV mV dB mV
MPXpilot(rms) nominal stereo pilot voltage level (RMS value) STon(rms) SToff(rms) Hys OUTL+R pilot threshold voltage stereo on (RMS value) pilot threshold voltage stereo off (RMS value) hysteresis output voltage level for 100% modulation L + R at LINE OUT (L + R; fi = 300 Hz); monitoring LINE OUT stereo channel separation L/R at LINE OUT input level adjusted via I2C-bus data STS = 1 data STS = 0 data STS = 1 data STS = 0
- - 15 10 - 480
cs
aligned with dual tone 14% modulation for each channel; see Section "Adjustment procedure" in Chapter "Functional description" fL = 300 Hz; fR = 3 kHz fL = 300 Hz; fR = 8 kHz fL = 300 Hz; fR = 10 kHz 25 20 15 35 30 25 - - - dB dB dB
1997 Mar 11
13
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
SYMBOL fL, R PARAMETER L, R frequency response CONDITIONS 14% modulation; fref = 300 Hz L or R fi = 50 Hz to 10 kHz fi = 12 kHz THDL,R S/N total harmonic distortion L, R at LINE OUT signal-to-noise ratio modulation L or R 1% to 100%; fi = 1 kHz mono mode; CCIR 468-2 weighted; quasi peak; 500 mV output signal -3 - - 50 - -3 0.2 60 MIN. TYP.
TDA9852
MAX.
UNIT
- - 1.0 -
dB dB % dB
Stereo decoder, oscillator (VCXO); note 1 fo fof fH nominal VCXO output frequency (32fH) spread of free-running frequency capture range frequency (nominal pilot) with nominal ceramic resonator with nominal ceramic resonator - 500.0 ±190 503.5 - ±265 - 507.0 - kHz kHz Hz
SAP demodulator; note 2 SAPi(rms) SAPon(rms) SAPoff(rms) SAPhys SAPLEV nominal SAP carrier input voltage level (RMS value) threshold voltage SAP on (RMS value) threshold voltage SAP off (RMS value) hysteresis SAP output voltage level at LINE OUT frequency response total harmonic distortion mode selector in position SAP/SAP; fmod = 300 Hz; 100% modulation 14% modulation; 50 Hz to 8 kHz; fref = 300 Hz fi = 1 kHz 15 kHz frequency deviation of intercarrier - - 35 - - 150 - - 2 500 - 85 - - - mV mV mV dB mV
fres THD
-3 -
- 0.5
- 2.0
dB %
1997 Mar 11
14
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
SYMBOL PARAMETER CONDITIONS - 9 - 5 - 100% modulation; fi = 1 kHz; 50 L or R; mode selector switched to SAP/SAP 100% modulation; fi = 1 kHz; SAP; mode selector switched to stereo 250 Hz to 6.3 kHz 50 MIN. TYP.
TDA9852
MAX. - - 120 - 2.5 -
UNIT
LINE OUT at pins LOL and LOR Vo(rms) HEADo Zo VO RL CL ct nominal output voltage (RMS value) output headroom output impedance DC output voltage output load resistance output load capacitance crosstalk L, R into SAP 100% modulation 500 - 80 - - 75 mV dB k nF dB
0.45VCC 0.5VCC
0.55VCC V
crosstalk SAP into L, R
70
-
dB
VST-SAP
output voltage difference if switched from L, R to SAP
-
-
3
dB
dbx noise reduction circuit tadj stereo adjustment time see Section "Adjustment procedure" in Chapter "Functional description" Is can be measured at pin CTS via current meter connected to 1/ V 2 CC + 1 V 7 steps via I2C-bus - - 1 s
Is
nominal timing current for nominal release rate of spectral RMS detector spread of timing current timing current range timing current for release rate of wideband RMS detector nominal RMS detector release rate
-
24
-
µA
Is Is range It Relrate
-15 - - nominal timing current and external capacitor values wideband spectral - -
- ±30
1/ 3Is
+15 - -
% % µA
125 381
- -
dB/s dB/s
1997 Mar 11
15
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
SYMBOL PARAMETER CONDITIONS MIN. TYP.
TDA9852
MAX.
UNIT
Circuit section from pins LIL and LIR to pins OUTL and OUTR; note 3 B roll-off frequencies C6, C7, C10, C26, C27 and C29 = 2.2 µF; Zi = Zi(min) low frequency (-3 dB) high frequency (-0.5 dB) THD total harmonic distortion Vi = 1000 mV; Gv = 0 dB; AVL on Vi = 2000 mV; Gv = 0 dB; AVL on Vi = 1000 mV; Gv = 0 dB; AVL off Vi = 2000 mV; Gv = 0 dB; AVL off RR ct Vno ripple rejection crosstalk between bus inputs and signal outputs noise output voltage Vr(rms) < 200 mV; fi = 100 Hz notes 4 and 5 CCIR 468-2 weighted; quasi peak; AVL off; loudness off; Gv = 0 dB measured in dBA; AVL off; loudness off; Gv = 0 dB cs channel separation Vi = 1 V; fi = 1 kHz Vi = 1 V; fi = 12.5 kHz Effect controls spat1 spat2 anti-phase crosstalk by spatial effect phase shift by pseudo-stereo see Fig.4 - - - 52 30 - - - - % % - - 20 - - - - 47 - - - - 0.2 0.2 0.02 0.02 50 110 40 20 - 0.5 0.5 - - - - 80 Hz kHz % % % % dB dB µV
- 75 75
8 - -
- - -
µV dB dB
1997 Mar 11
16
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
SYMBOL PARAMETER CONDITIONS MIN. TYP.
TDA9852
MAX.
UNIT
Automatic volume level control (AVL) Zi Vi(rms) Gv Gstep input impedance maximum input voltage (RMS value) gain, maximum boost maximum attenuation equivalent step width between the input stages (soft switching system) input level at maximum boost (RMS value) input level at maximum attenuation (RMS value) Vo(rms) VDC OFF output level in AVL operation (RMS value) DC offset between different gain steps see Fig.5 voltage at pin CAV 6.50 to 6.33 V or 6.33 to 6.11 V or 6.11 to 5.33 V or 5.33 to 2.60 V; note 6 AT1 = 0; AT2 = 0; note 7 AT1 = 1; AT2 = 0; note 7 AT1 = 0; AT2 = 1; note 7 AT1 = 1; AT2 = 1; note 7 Idec charge current for decay time power-on speed-up; CCD = 1; note 8 Selector from pins LOL, LOR, LIL and LIR to pins SOL and SOR Zi s Vi(rms) VDC OFF input impedance input isolation of one selected source to the other input maximum input voltage (RMS value) DC offset voltage at selector output by selection of any inputs output impedance output load resistance output load capacitance voltage gain, selector Vi = 1 V; fi = 1 kHz Vi = 1 V; fi = 12.5 kHz THD < 0.5% 16 86 80 2 - 20 96 96 2.3 - 24 - - - 25 k dB dB V mV THD < 0.2% 8.8 2 5 14 - 11.0 tbf 6 15 1.5 13.2 - 7 16 - k V dB dB dB
Viop(rms)
- - 160 -
0.1 1.125 200 -
- - 250 6
V V mV mV
Ratt
discharge resistors for attack time constant
340 590 0.96 1.7 -
420 730 1.2 2.1 2.0 tbf
520 910 1.5 2.6 2.4 -
k k µA µA
normal mode; CCD = 0; note 8 1.6
Zo RL CL Gv
- 5 0 -
80 - - 0
120 - 2.5 -
k nF dB
1997 Mar 11
17
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
SYMBOL PARAMETER CONDITIONS MIN. TYP.
TDA9852
MAX.
UNIT
Audio control part; input pins VIL and VIR to pins OUTX and OUTS Zi Zo RL CL Vi(rms) Vno volume input impedance output impedance output load resistance output load capacitance maximum input voltage (RMS value) noise output voltage THD < 0.5% CCIR 468-2 weighted; quasi peak Gv = 16 dB Gv = 0 dB mute position Gc Gstep total continuous control range step resolution step error between adjoining step Ga GL m VDC OFF attenuator set error gain tracking error mute attenuation DC step offset between any adjacent step DC step offset between any step to mute Loudness control part LB maximum loudness boost loudness on; referred to loudness off; boost is determined by external components; see Fig.6 fi = 40 Hz fi = 10 kHz LG VCC-DROP VRESET(STA) loudness control range Muting at power supply drop for OUTR and OUTS supply drop for mute active - - 4.2 5.2 VCAP - 0.7 - - 5 6 2.5 5.8 6.8 V - - -12 17 4.5 - - - +16 dB dB Gv = +16 to 0 dB Gv = 0 to -71 dB Gv = +16 to +1 dB Gv = 0 to -71 dB Gv = +16 to -50 dB Gv = -51 to -71 dB Gv = +16 to -50 dB maximum boost maximum attenuation - - - - - - - - - - 80 - - - - 110 33 10 16 71 1 - - - - - 0.2 - 2 1 220 50 - - - - 0.5 2 3 2 - 10.0 5 15 10 µV µV µV dB dB dB dB dB dB dB dB mV mV mV mV 8.0 - 5 0 2.0 10.0 80 - - 2.15 12.0 120 - 2.5 - k k nF V
Power-on reset; note 9 start of reset voltage increasing supply voltage decreasing supply voltage VRESET(END) end of reset voltage increasing supply voltage V V V
1997 Mar 11
18
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
SYMBOL PARAMETER CONDITIONS MIN. TYP.
TDA9852
MAX.
UNIT
Digital part (I2C-bus pins); note 10 VIH VIL IIH IIL VOL HIGH level input voltage LOW level input voltage HIGH level input current LOW level input current LOW level output voltage IIL = 3 mA 3 -0.3 -10 -10 - - - - - - VCC +1.5 +10 +10 +0.4 V V µA µA V
Notes to the characteristics 1. The oscillator is designed to operate together with MURATA resonator CSB503F58. Change of the resonator supplier is possible, but the resonator specification must be close to CSB503F58. 2. The internal SAP carrier level is determined by the composite input level and the level adjustment gain. 3. Frequency range 20 Hz to 20 kHz; select in to input line control; effects: linear stereo. V bus(p-p) 4. Crosstalk: 20 log -------------------V o(rms) 5. The transmission contains: a) Total initialization with MAD and SAD for volume and 11 DATA words, see also definition of characteristics b) Clock frequency = 50 kHz c) Repetition burst rate = 400 Hz d) Maximum bus signal amplitude = 5 V (p-p). 6. The listed pin voltage corresponds with typical gain steps of +6 dB, +3 dB, 0 dB, -6 dB and -15 dB. 7. Attack time constant = CAV × Ratt.
G2 G1 -------- ---------20 20 C AV × 0.76 V 10 10 Decay time = -----------------------------------------------------------------------------I dec
8.
Example: CAV = 4.7 µF; Idec = 2 µA; G1 = -9 dB; G2 = +6 dB decay time results in 4.14 s. 9. When reset is active the GMU-bit (general mute) and the LMU-bit (LINE OUT mute) is set and the I2C-bus receiver is in the reset position. 10. The AC characteristics are in accordance with the I2C-bus specification. The maximum clock frequency is 100 kHz. Information about the I2C-bus can be found in the brochure "The I2C-bus and how to use it" (order number 9398 393 40011).
1997 Mar 11
19
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
I2C-BUS PROTOCOL I2C-bus format to read (slave transmits data) S Table 1 SLAVE ADDRESS R/W A DATA MA
TDA9852
DATA
P
Explanation of I2C-bus format to read (slave transmits data) NAME DESCRIPTION START condition; generated by the master 101 101 1 1 (read); generated by the master acknowledge; generated by the slave slave transmits an 8-bit data word acknowledge; generated by the master STOP condition; generated by the master Definition of the transmitted bytes after read condition MSB FUNCTION BYTE D7 D6 SAPP SAPP D5 STP STP D4 A14 A24 D3 A13 A23 D2 A12 A22 D1 A11 A21 D0 A10 A20 ALR1 ALR2 Y Y LSB
S Standard SLAVE ADDRESS (MAD) R/W A DATA MA P Table 2
Alignment read 1 Alignment read 2 Table 3
Function of the bits in Table 2 BITS FUNCTION stereo pilot identification (stereo received = 1) SAP pilot identification (SAP received = 1) stereo alignment read data for wideband expander for spectral expander indefinite
STP SAPP A1X to A2X A1X A2X Y
The master generates an acknowledge when it has received the first data word ALR1, then the slave transmits the next data word ALR2. Afterwards the master generates an acknowledge, then the slave begins transmitting the first data word ALR1 etc. until the master generates no acknowledge and transmits a STOP condition.
1997 Mar 11
20
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
I2C-bus format to write (slave receives data) S Table 4 SLAVE ADDRESS R/W A SUBADDRESS A DATA
TDA9852
A
P
Explanation of I2C-bus format to write (slave receives data) NAME DESCRIPTION START condition 101 101 1 0 (write) acknowledge; generated by the slave see Table 5 see Table 6 STOP condition
S Standard SLAVE ADDRESS (MAD) R/W A SUBADDRESS (SAD) DATA P
If more than 1 byte of DATA is transmitted, then auto-increment is performed, starting from the transmitted subaddress and auto-increment of subaddress in accordance with the order of Table 5 is performed. Table 5 Subaddress second byte after MAD MSB FUNCTION Volume right Volume left Control 1 (note 1) Control 2 Control 3 Alignment 1 Alignment 2 Alignment 3 Note 1. In auto-increment mode it is necessary to insert 3 dummy data words between volume left and control 1. Table 6 Definition of third byte, third byte after MAD and SAD MSB FUNCTION Volume right Volume left Control 1 Control 2 Control 3 Alignment 1 Alignment 2 Alignment 3 1997 Mar 11 REGISTER D7 VR VL CON1 CON2 CON3 ALI1 ALI2 ALI3 0 0 GMU SAP 0 0 STS ADJ D6 VR6 VL6 AVLON STEREO 0 0 0 AT1 21 D5 VR5 VL5 LOFF TZCM 0 0 0 AT2 D4 VR4 VL4 CCD 1 0 A14 A24 0 D3 VR3 VL3 0 LMU L3 A13 A23 1 D2 VR2 VL2 SC2 EF2 L2 A12 A22 TC2 D1 VR1 VL1 SC1 EF1 L1 A11 A21 TC1 D0 VR0 VL0 SC0 EF0 L0 A10 A20 TC0 LSB REGISTER D7 VR VL CON1 CON2 CON3 ALI1 ALI2 ALI3 0 0 0 0 0 0 0 0 D6 0 0 0 0 0 0 0 0 D5 0 0 0 0 0 0 0 0 D4 0 0 0 0 0 0 0 0 D3 0 0 0 0 0 1 1 1 D2 0 0 1 1 1 0 0 0 D1 0 0 0 1 1 0 0 1 D0 0 1 1 0 1 0 1 0 LSB
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
Table 7 Function of the bits in Table 6 BITS VR0 to VR6 VL0 to VL6 GMU AVLON CCD LOFF SC0 to SC2 STEREO, SAP TZCM LMU EF0 to EF2 L0 to L3 ADJ A1X to A2X A1X A2X AT1 and AT2 TC0 to TC2 STS Table 8 Volume setting DATA V6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 V5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 V4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 V3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 V2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 V1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 volume control right volume control left mute control for all outputs (generate mute) AVL on/off increased AVL decay current on/off switch loudness on/off selection between line in and line out mode selection for line out FUNCTION
TDA9852
zero cross mode in mute operation (right and left output stage) mute control for line out selection between mono, stereo linear, spatial stereo and pseudo mode input level adjustment stereo adjustment on/off stereo alignment data for wideband expander for spectral expander attack time at AVL timing current alignment data stereo level switch
FUNCTION Gv (dB) 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
V0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
1997 Mar 11
22
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
FUNCTION Gv (dB) 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 -21 -22 -23 -24 -25 -26 -27 -28 -29 -30 -31 -32 -33 -34 -35 -36 -37 -38 DATA V6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 V5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 V4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 V3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 V2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 V1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
TDA9852
V0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
1997 Mar 11
23
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
FUNCTION Gv (dB) -39 -40 -41 -42 -43 -44 -45 -46 -47 -48 -49 -50 -51 -52 -53 -54 -55 -56 -57 -58 -59 -60 -61 -62 -63 -64 -65 -66 -67 -68 -69 -70 -71 Mute DATA V6 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 V5 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 V4 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 V3 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 V2 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 V1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1
TDA9852
V0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
1997 Mar 11
24
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
Table 9 Loudness setting DATA LOFF 0 1 Table 11 Selector setting FUNCTION(1) SC2 Inputs LOR and LOL Inputs LOR and LOR Inputs LOL and LOL DATA FUNCTION EF2 Stereo linear on Pseudo on Spatial stereo; 30% anti-phase crosstalk Spatial stereo; 50% anti-phase crosstalk Forced mono 0 0 0 0 1 EF1 0 0 1 1 1 EF0 0 1 0 1 1 Inputs LOL and LOR Inputs LIR and LIL Inputs LIR and LIR Inputs LIL and LIL Inputs LIL and LIR Note 0 0 0 0 1 1 1 1
TDA9852
CHARACTERISTIC With loudness Linear Table 10 Effects setting
DATA SC1 0 0 1 1 0 0 1 1 SC0 0 1 0 1 0 1 0 1
1. Input connected to outputs SOR and SOL.
Table 12 Switch setting at line out LINE OUT SIGNALS AT LOL SAP Mute Left Mono Mono Mono Mono LOR SAP mute right mono SAP mute mono DATA TRANSMISSION STATUS INTERNAL SWITCH, READABLE BITS: STP, SAPP SAP received no SAP received STEREO received no STEREO received SAP received no SAP received independent SETTING BITS STEREO 1 1 1 1 0 0 0 SAP 1 1 0 0 1 1 0
Table 13 Zero cross detection setting FUNCTION Direct mute control Mute control delayed until the next zero crossing Table 14 Mute setting FUNCTION Forced mute at OUTR, OUTL and OUTS Audio processor controlled outputs DATA GMU 1 0 FUNCTION forced mute at LOR and LOL stereo processor controlled outputs DATA LMU 1 0 DATA TZCM 0 1
1997 Mar 11
25
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
Table 15 AVL attack time DATA FUNCTION AT1 Ratt = 420 Ratt = 730 Ratt = 1200 Ratt = 2100 Table 16 ADJ bit setting FUNCTION Stereo decoder operation mode Auto adjustment of channel separation Table 17 AVLON bit setting FUNCTION Automatic volume control off Automatic volume control on Table 18 CCD bit setting FUNCTION Load current for normal AVL decay time Increased load current Table 19 STS bit setting (pilot threshold stereo on) FUNCTION STon 35 mV STon 30 mV Table 20 Timing current setting FUNCTION IS RANGE +30% +20% +10% Nominal -10% -20% -30% DATA TC2 1 1 1 0 0 0 0 TC1 0 0 1 1 1 0 0 TC0 0 1 0 1 0 1 0 DATA 1 0 DATA 0 1 DATA 0 1 DATA 0 1 0 1 0 1 AT2 0 0 1 1 Table 21 Level adjust setting GL (dB) +4.0 +3.5 +3.0 +2.5 +2.0 +1.5 +1.0 +0.5 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 DATA L3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 L2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
TDA9852
L1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
L0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
1997 Mar 11
26
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
TDA9852
Table 22 Alignment data for expander in read register ALR1 and ALR2 and in write register ALI1 and ALI2 DATA FUNCTION Gain increase D4 AX4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Nominal gain Gain decrease 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D3 AX3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 D2 AX2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 D1 AX1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 D0 AX0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
1997 Mar 11
27
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
TDA9852
MHA311
handbook, full pagewidth
0
phase (degree) -100
(1)
(2) (3)
-200
-300
-400 10
102
103
104
f (Hz)
105
(1) see Table 23. (2) see Table 23. (3) see Table 23.
Fig.4 Pseudo (phase in degrees) as a function of frequency (left output).
Table 23 Explanation of curves in Fig.4 CURVE 1 2 3 CAPACITANCE AT PIN CPS1 (nF) 15 5.6 5.6 CAPACITANCE AT PIN CPS2 (nF) 15 47 68 EFFECT normal intensified more intensified
1997 Mar 11
28
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
TDA9852
MHA312
handbook, full pagewidth
300
7
(1)
Vo(rms) (mV) 250
VCAV (V) 6
(2)
5 200
(3)
4
160 3
2
100 10-2 (1) VCAV (2) Vo max(rms) (3) Vo min(rms)
10-1
1 1 VI(rms) (V) 10
AVL measured at pin EOL/EOR. Y1 axis output level in AVL operation with typically 200 mV. Y2 axis VCAV DC voltage at pin CAV corresponds with typical gain steps in range of +6 to -15 dB.
Fig.5 Automatic level control diagram.
MHA313
handbook, full pagewidth
25
VdB (VQX 0) (dB)
15
16 14 9
5
4 -1
-5
-6 -11 -16
-15
-21 -26
-25
-31 -36
-35 10
102
103
f (Hz)
104
Fig.6 Volume control with loudness (including low roll-off frequency).
1997 Mar 11
29
parameter: volume gain setting (dB)
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
INTERNAL PIN CONFIGURATIONS
+
1 4.25 V
TDA9852
2
4.25 V
80
1.33 k
+
MHA315 MHA314
Fig.7 Pins OUTL, SOL, SOR and OUTR.
Fig.8 Pins LDL and LDR.
3
4.25 V
+
10.58 k 4.8 k
+
4
4.25 V
15 k
6.8 k
MHA317
MHA316
Fig.9 Pins VIL and VIR.
Fig.10 Pins EOL and EOR.
6 5
+
+
3.4 k
3.4 k
MHA318 MHA319
Fig.11 Pin CAV.
Fig.12 Pin Vref.
1997 Mar 11
30
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
TDA9852
8 7 4.25 V
4.25 V 1
+
+
2
3 20 k 20 k
MHA320
1.75 k
8
MHA321
Fig.13 Pins LIL and LIR.
Fig.14 Pins AVL and AVR.
+
10
4.25 V 11
+
5 k
MHA323 MHA322
Fig.15 Pins LOL and LOR.
Fig.16 Pins CTW and CTS.
13
4.25 V 15
+ +
6 k
MHA324
MHA325
Fig.17 Pins CW and CS.
Fig.18 Pin VEO.
1997 Mar 11
31
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
TDA9852
16 17 4.25 V
+ +
600
MHA326
10 k
MHA327
Fig.19 Pin VEI.
Fig.20 Pin CNR.
+
18 19 4.25 V
+
20 k
MHA328
20 k
MHA329
Fig.21 Pin CM.
Fig.22 Pin CDEC.
21 5 V
22
5V
1.8 k
1.8 k
MHA331 MHA330
Fig.23 Pin SDA.
Fig.24 Pin SCL.
1997 Mar 11
32
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
TDA9852
24 4.25 V 23 apply +8.5 V to this pin +
+
MHA332
30 k
MHA333
Fig.25 Pin VCC.
Fig.26 Pin COMP.
+
25
26 4.25 V
+
4.7 k 5 k
MHA334
300 3.5 k
MHA335
Fig.27 Pin VCAP.
Fig.28 Pin CP1.
+
27
4.25 V
28 4.25 V
+
8.5 k
12 k
MHA336
10 k
10 k
MHA337
Fig.29 Pin CP2.
Fig.30 Pin CPH.
1997 Mar 11
33
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
TDA9852
+
29
30
+
3 k
MHA338
MHA339
Fig.31 Pin CADJ.
Fig.32 Pin CER.
38 31 4.25 V
+
+
10 k
10 k
MHA340
15 k
MHA341
Fig.33 Pins CMO and CSS.
Fig.34 Pins CPS1 and CPS2.
1997 Mar 11
34
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
PACKAGE OUTLINES SDIP42: plastic shrink dual in-line package; 42 leads (600 mil)
TDA9852
SOT270-1
seating plane
D
ME
A2
A
L
A1 c Z e b1 w M (e 1) MH b 42 22
pin 1 index E
1
21
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 5.08 A1 min. 0.51 A2 max. 4.0 b 1.3 0.8 b1 0.53 0.40 c 0.32 0.23 D (1) 38.9 38.4 E (1) 14.0 13.7 e 1.778 e1 15.24 L 3.2 2.9 ME 15.80 15.24 MH 17.15 15.90 w 0.18 Z (1) max. 1.73
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT270-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 90-02-13 95-02-04
1997 Mar 11
35
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
TDA9852
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
c
y X
A 33 34 23 22 ZE
e E HE wM bp pin 1 index 44 1 bp D HD wM 11 ZD B v M B v M A 12 detail X A A2 (A 3) Lp L
A1
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.10 A1 0.25 0.05 A2 1.85 1.65 A3 0.25 bp 0.40 0.20 c 0.25 0.14 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.8 HD 12.9 12.3 HE 12.9 12.3 L 1.3 Lp 0.95 0.55 v 0.15 w 0.15 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 10 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT307-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 97-08-01
1997 Mar 11
36
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). SDIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. QFP REFLOW SOLDERING Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9398 510 63011). 1997 Mar 11 37
TDA9852
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary from 50 to 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheat for 45 minutes at 45 °C. WAVE SOLDERING Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: · A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. · The footprint must be at an angle of 45° to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C.
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA9852
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1997 Mar 11
38
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder and audio processor
NOTES
TDA9852
1997 Mar 11
39
Philips Semiconductors a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 1949 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580/xxx France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstraße 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd. Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Rua do Rocio 220, 5th floor, Suite 51, 04552-903 São Paulo, SÃO PAULO - SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 829 1849 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2870, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 © Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA53
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
547047/1200/02/pp40
Date of release: 1997 Mar 11
Document order number:
9397 750 01766