Text preview for : XV-521BK.pdf part of JVC XV-521BK Service manual, User manual, Parts list, Schematic diagram for DVD Player, models: XV-521BK/523GD
XV-525BK/421BK
Back to : XV-521BK.part1.rar | Home
Important Information 1. Main adjustment 2. Check point for each error 3. IC701 (M101C12GHA)
For the above 3 items, a supplementary edition will be issued in early July.
XV-521BK/523GD XV-525BK/421BK
SERVICE MANUAL
DVD PLAYER
XV-521BK/523GD XV-525BK/421BK
J Area Suffix XV-421BK U.S.A Area Suffix XV-525BK/523GD J U.S.A Area Suffix XV-521BK C Canada
Contents
Safety precautions Importance administering point on the safety Dismantling and assembling the traverse unit 1-2 1-3 1-4 Disassembly method Precautions for service Description of major ICs 1-5 1-15 1-16
COPYRIGHT
2000 VICTOR COMPANY OF JAPAN, LTD.
No.20836 Jun. 2000
XV-521BK/523GD/525BK/421BK
Safety Precautions
1. This design of this product contains special hardware and many circuits and components specially for safety purposes. For continued protection, no changes should be made to the original design unless authorized in writing by the manufacturer. Replacement parts must be identical to those used in the original circuits. Services should be performed by qualified personnel only. 2. Alterations of the design or circuitry of the product should not be made. Any design alterations of the product should not be made. Any design alterations or additions will void the manufacturer`s warranty and will further relieve the manufacture of responsibility for personal injury or property damage resulting therefrom. 3. Many electrical and mechanical parts in the products have special safety-related characteristics. These characteristics are often not evident from visual inspection nor can the protection afforded by them necessarily be obtained by using replacement components rated for higher voltage, wattage, etc. Replacement parts which have these special safety characteristics are identified in the Parts List of Service Manual. Electrical components having such features are identified by shading on the schematics and by ( ) on the Parts List in the Service Manual. The use of a substitute replacement which does not have the same safety characteristics as the recommended replacement parts shown in the Parts List of Service Manual may create shock, fire, or other hazards. 4. The leads in the products are routed and dressed with ties, clamps, tubings, barriers and the like to be separated from live parts, high temperature parts, moving parts and/or sharp edges for the prevention of electric shock and fire hazard. When service is required, the original lead routing and dress should be observed, and it should be confirmed that they have been returned to normal, after re-assembling. 5. Leakage currnet check (Electrical shock hazard testing) After re-assembling the product, always perform an isolation check on the exposed metal parts of the product (antenna terminals, knobs, metal cabinet, screw heads, headphone jack, control shafts, etc.) to be sure the product is safe to operate without danger of electrical shock. Do not use a line isolation transformer during this check. Plug the AC line cord directly into the AC outlet. Using a "Leakage Current Tester", measure the leakage current from each exposed metal parts of the cabinet , particularly any exposed metal part having a return path to the chassis, to a known good earth ground. Any leakage current must not exceed 0.5mA AC (r.m.s.) Alternate check method Plug the AC line cord directly into the AC outlet. Use an AC voltmeter having, 1,000 ohms per volt or more sensitivity in the following manner. Connect a 1,500 10W resistor paralleled by a 0.15 F AC-type capacitor between an exposed AC VOLTMETER metal part and a known good earth ground. (Having 1000 Measure the AC voltage across the resistor with the ohms/volts, or more sensitivity) AC voltmeter. Move the resistor connection to eachexposed metal part, particularly any exposed metal part having a 0.15 F AC TYPE return path to the chassis, and meausre the AC Place this voltage across the resistor. Now, reverse the plug in probe on the AC outlet and repeat each measurement. voltage each exposed 1500 10W metal part. measured Any must not exceed 0.75 V AC (r.m.s.). This corresponds to 0.5 mA AC (r.m.s.).
Good earth ground
Warning
1. This equipment has been designed and manufactured to meet international safety standards. 2. It is the legal responsibility of the repairer to ensure that these safety standards are maintained. 3. Repairs must be made in accordance with the relevant safety standards. 4. It is essential that safety critical components are replaced by approved parts. 5. If mains voltage selector is provided, check setting for local voltage. ! CAUTION Burrs formed during molding may be left over on some parts of the chassis. Therefore, pay attention to such burrs in the case of preforming repair of this system. 1-2
XV-521BK/523GD/525BK/421BK
Importance administering point on the safety
F901
For USA and Canada / pour Etats - Unis d' Amerique et Canada
Caution: For continued protection against risk of fire, replace only with same type 1.6A/250V for F901. This symbol specifies type of fast operating fuse. Precaution: Pour eviter risques de feux, remplacez le fusible de surete de comme le meme type que 1.6A/250V pour F901. Ce sont des fusibles suretes qui functionnes rapide.
1-3
XV-521BK/523GD/525BK/421BK
Dismantling and assembling the traverse unit
1. Notice regarding replacement of optical pickup
Electrostatic discharge (ESD), which occurs when static electricity stored in the body, fabric, etc. is discharged, can destroy the laser diode in the traverse unit (optical pickup). Take care to prevent this when performing repairs to the optical pickup or connected devices. (Refer to the section regarding anti-static measures.) 1. Do not touch the area around the laser diode and actuator. 2. Do not check the laser diode using a tester, as the diode may easily be destroyed. 3. It is recommended that you use a grounded soldering iron when shorting or removing the laser diode. Recommended soldering iron: HAKKO ESD-compatible product 4. Solder the land on the optical pickup's flexible cable. Note : Short the land after shorting the terminal on the flexible cable using a clip, etc., when using an ungrounded soldering iron. Note : After shorting the laser diode according to the procedure above, remove the solder according to the text explanation.
Shorting
Shot with the clip
1-4
XV-521BK/523GD/525BK/421BK
Disassembly method
< Main body> Removing the top cover (See Fig.1)
1. Remove the four screws A on both side of the body. 2. Remove the two screws B on the back of the body. 3. Lift up the rear part of the top cover while pulling the lower part of the sides, then detach upward.
Top cover
B
A
2
A
2 Fig.1
Removing the rear panel (See Fig.2)
Prior to performing the following procedure, remove the top cover. 1. Remove the seven screws C body. on the back of the
C
Rear panel
C
C
Fig.2
C
1-5
XV-521BK/523GD/525BK/421BK
Removing the fitting (See Fig.3 to 6)
Prior to performing the following procedure, remove the top cover. ATTENTION: To remove the front panel assembly and the DVD mechanism assembly, remove the fitting in advance. by hand 1. Turn over the body. Insert a screwdriver into the hole of the bottom chassis and turnit. The loading tray will be ejected out of the front panel assembly. 2. Pull the loading tray toward the front. 3. Remove the fitting upward from the loading tray at the joints b. Front panel assembly 4. Push and return the loading tray. Fig.3
Bottom chassis Front panel Hole
(Bottom)
Loading tray
Front panel assembly
Fitting
Joint b Joint b
Front panel assembly
Loading tray
1-6
TRAY OPEN
Fig.4
Loading tray
Fig.5
DVD mechanism assembly
Fig.6
XV-521BK/523GD/525BK/421BK
Removing the front panel assembly (See Fig.7 to 10)
Prior to performing the following procedure, remove the top cover and the fitting. 1. Disconnect the card wire from connector CN703 on the main board. 2. Turn over the body and remove the screw D attaching the front panel assembly.
CN703
DC mechanism assembly Main board AC jack board
3. Release the five joints c on both sides and bottom of the body and remove the front panel assembly toward the front. ATTENTION: The connector CN832 on the front panel assembly and CN971 on the AC jack board will be disconnected at the same time.
CN971 Front panel assembly
Fig.7
Joint c
D
Joint c
Fig.8
Front panel assembly
Fig.9
Front panel assembly
Joint c
Joint c
Fig.10
1-7
XV-521BK/523GD/525BK/421BK
Removing the DVD mechanism assembly (See Fig.11 to 14)
Prior to performing the following procedure, remove the top cover and the front panel assembly. 1. Disconnect the card wire from connector CN101 on the DVD Servo. 2. Disconnect the harness from connector CN031 on the DVD mechanism assembly. 3. Remove the screw E loading tray. on the rear left part of the
E
Loading tray
CN101 DVD Servo
3. From the front side of the DVD mechanism assembly, move the lever d in the direction of the arrow and pull out the loading tray. 4. Remove the two screws F on the upper side of the DVD mechanism assembly. Then release the two joints e and detach the clamper base back-upward. 5. Remove the three screws G mechanism assembly. attaching the DVD
DVD mechanism assembly P031
Fig.11
Loading tray Lever d
P031
DVD mechanism assembly
Fig.12
DVD mechanism assembly
CN101
F
F
Joint e
Clamper base Joint e
Fig.13
G
CN101
G
G
DVD mechanism assembly
Fig.14
1-8
XV-521BK/523GD/525BK/421BK
Removing the AC jack board (See Fig.15 and 16)
Prior to performing the following procedure, remove the top cover and the front panel assembly. 1. Remove the two screws H attaching the AC jack board. 2. Remove the two screws C on the rear panel. 3. Disconnect connector CN951 and CN961 on the AC jack board from CN704 and CN705 on the main board respectively.
AC jack board
CN951 / CN705
Main board
H H
CN961 / CN704
Fig.15
Rear panel
C
Fig.16
Removing the DVD Servo (See Fig.17 and 18)
Prior to performing the following procedure, remove the top cover.
CN501 / CN706
I
1. Remove the screw I attaching the DVD Servo. 2. Pull out the DVD Servo from the fix f while pinching the fix f. 3. Disconnect connector CN501, CN502 and CN503 on the DVD Servo from CN601, CN701 and CN706 on the main board respectively.
CN101 DVD Servo
Fix f
CN502 / CN701 CN503 / CN701
Fig.17
Fix f
DVD Servo
Main board Fig.18
1-9
XV-521BK/523GD/525BK/421BK
Removing the main board (See Fig.19 and 20)
Prior to performing the following procedure, remove the top cover, the front panel assembly, the DVD mechanism assembly, the AC jack board and the DVD Servo. 1. Remove the three screws J board. attaching the main
Main board
J J J
Fig.19
2. Remove the two screws C on the rear panel.
Prior to performing the following procedure, remove the top cover and the front panel assembly.
C
Rear panel
Removing the power switch board (See Fig.21)
1. Unsolder connector FW841 on the power switch board on the back of the front panel assembly. Fig.20 2. Remove the two screws K switch board. attaching the power
3. Push the two tabs g in the direction of the arrow and remove the power switch board.
Front panel assembly
Power switch board
K
Tabs g
Removing the LCD board (See Fig.22)
1. Unsolder connector FW802 and soldering h on the LCD board. 2. Remove the four screws L attaching the LCD board.
K
Removing the search switch board (See Fig.20)
1. Unsolder soldering i on the search switch board.
Search switch board
Fig.21
FW841
Front panel assembly
2. Remove the three screws M. 3. Release the four tabs j in the direction of the arrow and remove the search switch board.
M L M
Tabs j 4
LCD board
FW802
L
i
h
L
L
Fig.22
1-10
XV-521BK/523GD/525BK/421BK
Removing the traverse mechanism unit (See Fig.1 and 2)
1. Remove the screw A and the spring on the upper side of the loading base assembly. 2. Move the rear part of the traverse mechanism unit upward and pull backward to release the two joints a with the base chassis. ATTENTION: When reattaching, engage the two joints a and make sure the front springs and the four insulators of the traverse mechanism unit are correctly attached.
Traverse mechanism unit
A
Spring
Joints a
Fig.1
A
Spring and Insulator Joints a
Spring
Spring and Insulator
Removing the loading motor / loading motor board (See Fig.3 and 4)
1. Move the cam plate on the upper side of the loading base assembly in the direction of the arrow. 2. Remove the belt from the motor pulley. 3. Remove the two screws B motor. attaching the loading
Insulator
Fig.2
Belt
B B
4. Turn over the loading base assembly and release the loading motor board from the three tabs b while spreading them outward. The loading motor board will be detached with the loading motor. 5. Unsolder soldering c on the loading motor board and remove the loading motor. Ref.: To remove the loading motor board only, unsolder soldering c on the loading motor and release the three tabs b.
Cam plate
Fig.3
Loading motor
Tab b
Tab b Tab b c Loading motor board
Fig.4
1-11
XV-521BK/523GD/525BK/421BK Removing the pickup (See Fig.5 to 9)
It is not necessary to remove the traverse mechanism unit. 1. Solder soldering d on the flexible board next to the pickup unit. 2. From the bottom of the traverse mechanism unit, disconnect the flexible wire from CN10 on the pickup board. ATTENTION: Disconnecting the flexible wire without soldering may cause damage to the pickup. 3. Remove the screw C attaching the shaft stopper (R) on the upper side of the traverse mechanism unit. Pull the side of the shaft stopper (R) outward to release the joint e and remove it upward. Remove the skew spring at the same time. 4. Move the shaft in the direction of the arrow to release it from the part f. 5. Release the joint g with the shaft and remove the pickup with the shaft. 6. Pull out the shaft. 7. Remove the screw D attaching the switch actuator.
Pickup unit Pickup unit
Flexible board
d
Fig.5
Pickup board
CN10
Flexible wire
Fig.6
Shaft stopper (R)
C
Shaft
Shaft Joint g
Fig.7
Shaft Pickup
Part f
C
Shaft stopper (R) Shaft stopper (R) Joint e
D
Switch actuator
Skew spring Shaft
Fig.9 1-12
Fig.8
XV-521BK/523GD/525BK/421BK Removing the pickup board (See Fig.5 and 10)
It is not necessary to remove the traverse mechanism unit.
Flexible board
Pickup unit
1. Solder soldering d on the flexible board next to the pickup unit. 2. From the bottom of the traverse mechanism unit, disconnect the flexible wire from CN10 on the pickup board.
d
ATTENTION: Disconnecting the flexible wire without soldering may cause damage to the pickup. 3. Unsolder soldering h, i and j of each harness on the pickup board. 4. Remove the screw E attaching the pickup board and release the two joints k.
Joint k h
Fig.5
Pickup board
E
CN10 Joint k i
Removing the feed motor assembly (See Fig.5, 10 and 11)
Prior to performing the following procedure, remove the traverse mechanism unit.
Feed motor assembly
1. Solder soldering d on the flexible board next to the pickup unit. 2. From the bottom of the traverse mechanism unit, disconnect the flexible wire from CN10 on the pickup board. ATTENTION: Disconnecting the flexible wire without soldering may cause damage to the pickup. 3. Unsolder soldering h of the motor harness on the pickup board. 4. Remove the two screws F attaching the feed motor assembly and remove the thrust spring. Move the feed motor assembly in the direction of the arrow to pull it out from the feed holder.
j
Fig.10
Feed motor assembly
Thrust spring
F
F
Feed holder assembly
Fig.11
1-13
XV-521BK/523GD/525BK/421BK
Removing the turn table assembly (See Fig.5, 10, 12 and 13)
Prior to performing the following procedure, remove the traverse mechanism unit. 1. Solder soldering d on the flexible board next to the pickup unit. 2. From the bottom of the traverse mechanism unit, disconnect the flexible wire from CN10 on the pickup board. ATTENTION: Disconnecting the flexible wire without soldering may cause damage to the pickup. 3. Unsolder soldering i and j of the harness extending from the turning table assembly to the pickup board. 4. Remove the screw G attaching the shaft stopper (F) on the upper side of the traverse mechanism unit. Pull the side of the shaft stopper (F) outward to release the joint l and remove it upward. Remove the spring at the same time. 5. Remove the screw H assembly. attaching the turn table
Joint k Pickup unit
Flexible board
d
Fig.5
h Pickup board
E
CN10 Joint k i
Feed motor assembly
j
Fig.10 6. Move the turn table assembly outward and pull out from the shaft. Then remove it from the base chassis.
Shaft stopper (F)
G
Turn table assembly
H G
Fig.12
G
Shaft stopper (F) Shaft stopper (F)
Joint l
H
Shaft Shaft
Turn table assembly
Fig.13
1-14
XV-521BK/523GD/525BK/421BK
Precautions for Service
Handling of Traverse Unit and Laser Pickup
1. Do not touch any peripheral element of the pickup or the actuator. 2. The traverse unit and the pickup are precision devices and therefore must not be subjected to strong shock. 3. Do not use a tester to examine the laser diode. (The diode can easily be destroyed by the internal power supply of the tester.) 4. To replace the traverse unit, pull out the metal short pin for protection from charging. 5. When replacing the pickup, after mounting a new pickup, remove the solder on the short land which is provided at the center of the flexible wire to open the circuit. 6. Half-fixed resistors for laser power adjustment are adjusted in pairs at shipment to match the characteristics of the optical block. Do not change the setting of these half-fixed resistors for laser power adjustment.
Destruction of Traverse Unit and Laser Pickup by Static Electricity
Laser diodes are easily destroyed by static electricity charged on clothing or the human body. Before repairing peripheral elements of the traverse unit or pickup, be sure to take the following electrostatic protection: 1. Wear an antistatic wrist wrap. 2. With a conductive sheet or a steel plate on the workbench on which the traverse unit or the pick up is to be repaired, ground the sheet or the plate. 3. After removing the flexible wire from the connector (CN101), short-circuit the flexible wire by the metal clip. 4. Short-circuit the laser diode by soldering the land which is provided at the center of the flexible wire for the pickup. After completing the repair, remove the solder to open the circuit.
Shorting
When replacing the Mechanism Unit, turn ON the laser switch that is located at the lower of the pick up after replacement.
1-15
XV-521BK/523GD/525BK/421BK
Description of major ICs
AK93C45AF-W (IC791) : CMOS EEPROM
1.Pin Layout AK93C45AF NC YCC CS SK 1 2 3 4 8 7 6 5 NC GND DO DI
2.Pin Functions Symbol CS SK DI DO Vcc GND NC Function Chip Select Serial Clock Input Serial Data Input Serial Data Output Power Supply Ground Non connection
3.Block Diagram DO
DATA REGISTER
16
R/W AMPS AND AUTO ERASE
16
DI
INSTRUCTION REGISTER INSTRUCTION DECODE. CONTROL AND CLOCK GENERATION ADD. BUFFERS
EEPROM 1024bit 64 X 16
DECODER
CS
VPP SW
SK
VPP
VREF
GENERATOR
1-16
XV-521BK/523GD/525BK/421BK
AK93C65AF-X (IC403) : EEPROM
1.Terminal layout
PE
1
8
NC
VCC
2
7
GND
CS
3
6
DO
SK
4 8 PIN SOP
5
DI
2.Block diagram
DO
DATA REGISTER 16 16
DI
INSTRUCTION REGISTER
R/W AMPS AND AUTO ERASE
INSTRUCTION DECODE, CONTROL AND CLOCK GENERATION
EEPROM 4096bit 256 x 16
ADD. BUFFERS
DECODER
CS VPP SW SK
PE VREF
VPP GENERATOR
3.Pin function Pin no. 1 2 3 4 5 6 7 8 Symbol PE VCC CS SK DI DO GND NC Function Program enable (With built-in pull-up resistor) Power supply Chip selection Cereal clock input Cereal data input Cereal data output Ground No connection (VCC=5V)
NOTE : The pull-up resistor of the PE pin is about 2.5M
1-17
XV-521BK/523GD/525BK/421BK
AN8702FH (IC101) : Front end processor
1.Terminal Layout
HDTYPE VREF1 VIN12 VIN11 VIN10 GND1 VCC1 VIN4 VIN3 VIN2 VIN1 VIN9 VIN8 VIN7 VIN6 50 VIN5 49
64
63
62
61
60
59
58
57
56
55
54
53
52
PC1 PC01 PC2 PC02 TGBAL TBAL FBAL POFLT DTRD IDGT STANDBY SEN SCK STDI RSEL JLINE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
51
48 47 46 45 44 43
RFINN RFINP TESTSG AGCO AGCG PEAK BOTTOM RFENV BDO OFTR DCRF RFC VCC3 RFOUT RFDIFO GND3
AN8702FH
42 41 40 39 38 37 36 35 34 33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 DFLTOP
TEN
TEOUT
ASN
VDD
ASOUT
FEOUT
GND2
FEN
VSS
VREF2
VCC2
VHALF
DFLTON
TG
2.Pin Functions Pin No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Symbol
PC1 PC01 PC2 PC02 TGBAL TBAL FBAL POFLT DTRD IDGT STANDBY SEN SCK STDI RSEL JLINE TEN TEOUT
I/O
Function
I I I O I I I I I I
Tangential phase balance control terminal Tracking balance control terminal Focus balance control terminal Track detection threshold value level terminal Data slice part data read signal input terminal (For RAM) Data slice part address part gate signal input terminal (For RAM) Standby mode control terminal SEN (Serial data input terminal) SCK (Serial data input terminal) STDI (Serial data input terminal)
O
Tracking error signal output terminal
1-18
DSFLT
32
XV-521BK/523GD/525BK/421BK
Pin No.
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Symbol
ASN ASOUT FEN FEOUT VSS TG VDD GND2 VREF2 VCC2 VHALF DFLTON DFLTOP DSFLT GND3 RFDIFO RFOUT VCC3 RFC DCRF OFTR BDO RFENV BOTTOM PEAK AGCG AGCO TESTSG RFINP RFINN VIN5 VIN6 VIN7 VIN8 VIN9 VIN10 VCC1 VREF1 VIN1 VIN2 VIN3 VIN4 GND1 VIN11 VIN12 HDTYPE
I/O
Function
I O O O O
Focus error output amplifier reversing input terminal Focus error signal output terminal Ground Tangential phase error signal output terminal Apply 3V Ground VREF2 voltage output terminal Apply 5V VHALF voltage output terminal
-
Ground
O O O O O O I I I I I I I I I O I I I I I I
Apply 5V All addition amplifier capacitor terminal OFTR output terminal RF envelope output terminal Bottom envelope detection filter terminal Peak envelope detection filter terminal AGC amplifier gain control terminal TEST signal input terminal RF signal positive input terminal RF signal negative input terminal Focus input of external division into two terminal Focus input of external division into two terminal l
Apply 5V VREF1 voltage output terminal External division into four (DVD/CD) RF input terminal1 External division into four (DVD/CD) RF input terminal2 External division into four (DVD/CD) RF input terminal3 External division into four (DVD/CD) RF input terminal4 Ground
1-19
XV-521BK/523GD/525BK/421BK HY57V161610DTC8 or KM416S1120DT-G8 (IC504,IC505) : 16MB SDRAM
1.Block diagram
CLK CKE
Clock Generator
Mode register
Row decoder
Address
Row address buffer & Refresh counter
Bank B Bank A
Command decoder
Sense amplifier
Control logic
CS RAS CAS WE
Data counter
Latch circuit
Input & output buffer
Column address buffer & burst counter
Column decoder & latch circuit
DQM
DQ
2.Pin function Pin No. 1 2,3 4 5,6 7 8,9 10 11,12 13 14 15 16 17 18 19,20 21~24 25 Symbol VCC DQ0,1 VSS DQ2,3 VDD DQ4,5 VSS DQ6,7 VCC LDQM WE CAS RAS CS A11,10 A0~3 VCC Description Power supply Data input/output Connect to GND Data input/output Power supply Data input/output Connect to GND Data input/output Power supply Lower DQ mask enable Write enable Column address strobe Row address strobe Chip enable Address inputs Address inputs Power supply Pin No. 26 27~32 33 34 35 36 37 38 39,40 41 42,43 44 45,46 47 48,49 50 Symbol VSS A4~9 NC CKE CLK UDQM NC VCC DQ8,9 VSS DQ10,11 VDD DQ12,13 VSS DQ14,15 VSS Description Connect to GND Address inputs Non connect Clock enable System clock input Upper DQ mask enable Non connect Power supply Data input/output Connect to GND Data input/output Power supply Data input/output Connect to GND Data input/output Connect to GND
1-20
XV-521BK/523GD/525BK/421BK
Y/G2Vdd
MC44724AVFU (IC554) : VIDEO ENCODER
F/Vsync
64 ~ 1
49 48
16 17 ~ 32
33
ChipA DVdd DVdd DVss DVss DVIN[7:0] TP[8:1] TVIN TP[0]IN
H.V 0
Y cb
EXT
1.Terminal layout
2.Block diagrams
CVBS/Cb/B2Vdd
Hsync
C/Cr/R2Vdd
Sync_ generator
CGMS, wss gen
Copy, protection
bus
CCwss gen
0
off_set
DEMAX
+
0
0 Modulator
0
RGB matrix Clock Reset PAL/NTSC
12C / SPI
TEST
BIAS
DAC
0
DAC
0
DAC
sub carrier gen
BIAS
cr
Output Selector
0
DAC
DAC
+
Y/G1Vdd CVBS/Cb/B1Vdd C/Cr/R1Vdd Y/G1 Y/G1 CVBS/Cb/B1 CVBS/Cb/B1 C/Cr/R1 C/Cr/R1 Vref1 iBIAS1 Y/G2 Y/G2 CVBS/Cb/B2 CVBS/Cb/B2 C/Cr/R2 C/Cr/R2 Vref2 Ibias DAVdd DAVss
~
0
DAC
SDA/SI
SCL/SCK
3.Pin function
No. Symbol
CVBS/Cb/B1 CVBS/Cb/B1 CVBS/Cb/B1Vdd Y/G1 Y/G1 Y/G1/Vdd C/Cr/R1
I/O
Function
No. Symbol
I/O
I Non connect
1 2 3 4 5 6 7
O Analog composite drive signal (+) O Analog composite drive signal (-) - Power supply for CVBS/Cb/B DAC1 O Analog brightness signal/G drive signal (+) O Analog brightness signal/G drive signal (-) - Power supply for Y/G DAC O Analog chroma signal (+) O Analog chroma signal (-) - Power supply for C/Cr/RDAC - Connect to ground for DAC O Standard BIAS for DAC1 - Standard voltage for DAC1 - Power supply for DAC - Standard voltage for DAC2 O Standard BIAS for DAC2 - Non connect O Analog composite drive signal (+) O Analog composite drive signal (-) - Power supply for CVBS/Cb/B DAC2 O Analog brightness signal/G drive signal (+) O Analog brightness signal/G drive signal (-) - Power supply for Y/G DAC O Analog chroma signal (+) O Analog chroma signal (-) - Power supply for C/Cr/RDAC2 - Chip address selection I Connect to test pin - Digital ground I Clock signal input (27MHz) - Power supply for digital circuit I Reset signal input L:ON I Selection NTSC/PAL NTSC:L PAL:H
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
SO SDA/SI
SCL/SCK I I SEL -DVdd -DVss DVIN7 DVIN6 DVIN5 DVIN4 DVIN3 DVIN2 DVIN1 DVIN0 TVIN EXT F/Vsyac Chsyac DATST TP-8 TP7 TP6 TP5 DVss DVdd TP4 TP3 TP2 TP1 TP0 DLVdd DLVss
SPI Mode : Serial data input Serial clock input Power supply for serial data,chip select,digital Power supply for digital circuit Digital ground
8 C/Cr/R1 9 C/Cr/R1Vdd 10 DAVss 11 TBIAS1 12 Vref1 13 DAVdd 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Vref2 TBIAS2 NC CVBS/Cb/B2 CVBS/Cb/B2 CVBS/Cb/B2Vdd Y/G2 Y/G2 Y/GVdd C/Cr/R2 C/Cr/R2 C/Cr/R2Vdd ChipA TEST DVdd CLOCK DVss Reset PAL/NTSC
I/O Y data input / test data I/O I/O Y data input / test data I/O I/O Y data input / test data I/O I/O Y data input / test data I/O I/O Y data input / test data I/O I/O Y data input / test data I/O I/O I/O I I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O Y data input / test data I/O Y data input / test data I/O VIDEO mute on Reset(0:nomal, 1:mute) Frame output / VBI information input Frame / Vertical, synchronous I/O The horizontal, synchronous I/O Data input Multiplex data input Multiplex data input Multiplex data input Multiplex data input Ground for digital circuit Power supply for digital circuit Data input / Test data I/O Data input / Test data I/O Data input / Test data I/O Data input / Test data I/O Data input / Test data I/O Power supply for D/A converter Ground for D/A converter
DLVdd
Function
DLVss
SO
SEL
TEST
~
1-21
XV-521BK/523GD/525BK/421BK
MN102L25GDZ1 (IC401) : UNIT CPU
1.Terminal layout
NMI SDOUT SDIN CPSCK U2SDT S2UDT SCLKO VDD EPDO DPDI EPSK EPCS VSS HSSEEK CIRCEN REQ BUSY SLEEP FEPEN VDD ADSCEN TRS FGIN 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
ADSCIRQ 76 ODCIRQ 77 DECIRQ 78 WAKEUP 79 ODCIRQ2 80 ADSEP 81 RST 82 VDD 83 TEST1 84 TEST2 85 TEST3 86 TEST4 87 TEST5 88 TEST6 89 TEST7 90 TEST8 91 VSS 92 D0 93 D1 94 D2 95 D3 96 D4 97 D5 98 D6 99 D7 100
MN102L25GDZ1
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
TRVSW HMFON CD/DVD /ADPD HAGUP TXSEL A20 VSS A19 A18 A17 A16 A15 A14 A13 A12 VDD A11 A10 A9 A8 A7 A6 A5 A4
1-22
WAIT RE SPMUTE WEN CS0 CS1 CS2 CS3 DRVMUTE SPKICK LSTRST WORD A0 A1 A2 A3 VDD SYSCLK VSS XI XO VDD OSCI OSCO MODE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
XV-521BK/523GD/525BK/421BK
2.Pin function
Pin No.
Symbol I/O 1 I WAIT 2 O RE 3 SPMUTE O 4 O WEN 5 O CS0 6 O CS1 7 O CS2 8 O CS3 9 DRVMUTE O 10 O SPKICK 11 O LSIRST 12 O WORD 13 O A0 14 O A1 15 O A2 16 O A3 17 VDD 18 SYSCLK O 19 VSS 20 XI 21 XO 22 VDD 23 I OSCI 24 O OSCO 25 I MODE 26 O A4 27 O A5 28 O A6 29 O A7 30 O A8 31 O A9 32 O A10 33 O A11 34 VDD 35 O A12 36 O A13 37 O A14 38 O A15 39 O A16 40 O A17 41 O A18 42 O A19 43 VSS 44 O A20 45 O TXSEL 46 O HAGUP 47 /ADPD 48 O CD/DVD 49 HMFON 50 I TRVSW
51 52 53 Write enable 54 Non connect 55 Chip select for ODC 56 Chip select for ZIVA 57 Chip select for outer ROM 58 Driver mute 59 Spin kick (Non connect) 60 LSI reset 61 Bus selection input 62 Address bus 0 for CPU 63 Address bus 1 for CPU 64 Address bus 2 for CPU 65 Address bus 3 for CPU 66 Power supply 67 System clock signal output 68 Ground 69 Not use (Connect to vss) 70 Non connect 71 Power supply 72 Clock signal input(13.5MHz) 73 Clock signal output(13.5MHz) 74 CPU Mode selection input 75 Address bus 4 for CPU 76 Address bus 5 for CPU 77 Address bus 6 for CPU 78 Address bus 7 for CPU 79 Address bus 8 for CPU 80 Address bus 9 for CPU 81 Address bus 10 for CPU 82 Address bus 11 for CPU 83 Power supply 84 Address bus 12 for CPU 85 Address bus 13 for CPU 86 Address bus 14 for CPU 87 Address bus 15 for CPU 88 Address bus 16 for CPU 89 Address bus 17 for CPU 90 Address bus 18 for CPU 91 Address bus 19 for CPU 92 Ground 93 Address bus 20 for CPU 94 TX Select 95 96 97 98 99 Detection switch of traverse 100 inside
Function Micon wait signal input Read enable
Pin No.
Symbol FGIN TRS ADSCEN VDD FEPEN SLEEP BUSY REQ CIRCEN HSSEEK VSS EPCS EPSK DPDI EPDO VDD SCLKO S2UDT U2SDT CPSCK SDIN SDOUT NMI ADSCIRQ ODCIRQ DECIRQ WAKEUP ODCIRQ2 ADSEP RST VDD TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 TEST8 VSS D0 D1 D2 D3 D4 D5 D6 D7
I/O I O O O I O O O O O I O I I O O I O I I I O I I I I I I I I I I I I/O I/O I/O I/O I/O I/O I/O I/O
Function Photo input Serial enable signal for ADSC Power supply Serial enable signal for FEP Standby signal for FEP Communication busy Communication Request CIRC command select Seek select Ground EEPROM chip select EEPROM clock EEPROM data input EEPROM data output Power supply Communication clock Communication input data Communication output data Clock for ADSC serial ADSC serial data input ADSC serial data output Not use Not use Not use Interrupt input of ADSC Interrupt input of ODC Interrupt input of ZIVA Not use Address data selection input Reset input Power supply Test signal 1 input Test signal 2 input Test signal 3 input Test signal 4 input Test signal 5 input Test signal 6 input Test signal 7 input Test signal 8 input Ground Data bus 0 of CPU Data bus 1 of CPU Data bus 2 of CPU Data bus 3 of CPU Data bus 4 of CPU Data bus 5 of CPU Data bus 6 of CPU Data bus 7 of CPU
1-23
XV-521BK/523GD/525BK/421BK MN103S13BDA (IC301) : Optical disc controller
1.Terminal layout
DMARQ NIOWR VSS NIORD IORDY NDMACK VDD INTRQ NIOCS16 DA1 VSS NPDIAG DA0 DA2 VDD NCS1FX NCS3FX NDASP NTRYCL VDD NEJECT VSS MONI0 MONI1 MONI2 MONI3 SDATA SCLOCK VDD DAT0 DAT1 DAT2 DAT3 CHCK40 NCLDCK SUBC HDD15 HDD0 HDD14 VDD HDD1 HDD13 HDD2 VSS HDD12 VDD HDD3 HDD11 HDD4 HDD10 VDD HDD5 HDD9 VSS HDD6 HDD8 HDD7 VDDH NRESET MASTER NINT0 NINT1 WAITDOC NMRST DASPST VDD OSCO2 OSCI2 UATASEL VSS PVSSDRAM PVDDDRAM 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
MN103S13BDA
SBCK VSS P0 P1 PVDD PVSS VDD OSCO1 OSCI1 VSS LRCK BLKCK IPFLAG DACCLK DACLRCK DACDATA NTRON LG JMPINH IDHOLD SBCK/PLLOK CLKOUT2 VDD NRST MMOD VSS CPDET1 CPDET2 BDO IDGT DTRD TEHLD VDD CLKOUT1 CPUDT0 CPUDT1
2.Block diagram
DVD-ROM Formatter CD-PRE
CPUADR17 CPUADR16 VSS CPUADR15 CPUADR14 CPUADR13 CPUADR12 VDD CPUADR11 CPUADR10 CPUADR9 CPUADR8 CPUADR7 CPUADR6 CPUADR5 CPUADR4 CPUADR3 CPUADR2 CPUADR1 VSS CPUADR0 NCS NWR NRD VDD CPUDT7 CPUDT6 PVPPDRAM PTESTDRAM PVDDDRAM PVSSDRAM CPUDT5 CPUDT4 CPUDT3 VSS CPUDT2
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
Formatter i /t
ECC
Host i / f MPEG i / t
High speed IO bus
ATAPI
DMA CGEN Instruction memory (40KB) 32 bit CPU core
BCU MODE DATA MEMORY (6KB) GCAL DRAMC
4Mbit DRAM
General purpose IO bus
WDT
16 bit timer x 2
SYSTEM i / f
INTC
1-24
XV-521BK/523GD/525BK/421BK
3.Pin function Pin NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 Symbol HDD15 HDD0 HDD14 VDD HDD1 HDD13 HDD2 VSS HDD12 VDD HDD3 HDD11 HDD4 HDD10 VDD HDD5 HDD9 VSS HDD6 HDD8 HDD7 VDDH NRESET MASTER NINT0 NINT1 WAITDOC NMRST DASPST VDD OSCO2 OSCI2 UATASEL VSS PVSSDRAM PVDDDRAM CPUADR17 CPUADR16 VSS CPUADR15 CPUADR14 CPUADR13 CPUADR12 VDD CPUADR11 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O O O O O I O I I Function ATAPI data ATAPI data ATAPI data Apply 3V ATAPI data ATAPI data ATAPI data GND ATAPI data Apply 2.7V ATAPI data ATAPI data ATAPI data ATAPI data Apply 3V ATAPI data ATAPI data GND ATAPI data ATAPI data ATAPI data ATAPI reset ATAPI master / slave selection System control interruption 0 System control interruption 1 System control wait control System control reset (Connect to TP302) DASP signal initializing (VSS connected) Apply 3V OPEN (Connect to TP140) OPEN (Connect to TP303) VSS connected GND VSS connected VDD (2.7V) connected System control address System control address GND System control address System control address System control address System control address Apply 2.7V System control address
I I I I I I I
1-25
XV-521BK/523GD/525BK/421BK
Pin NO. 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
Symbol CPUADR10 CPUADR9 CPUADR8 CPUADR7 CPUADR6 CPUADR5 CPUADR4 CPUADR3 CPUADR2 CPUADR1 VSS CPUADR0 NCS NWR NRD VDD CPUDT7 CPUDT6 PVPPDRAM PTESTDRAM PVDDDRAM PVSSDRAM CPUDT5 CPUDT4 CPUDT3 VSS CPUDT2 CPUDT1 CPUDT0 CLKOUT1 VDD TEHLD DTRD IDGT BDO CPDET2 CPDET1 VSS MMOD NRST VDD CLKOUT2 SBCK/PLLOK IDOHOLD JMPINH
I/O I I I I I I I I I I I I I I I/O I/O O I
Function System control address System control address System control address System control address System control address System control address System control address System control address System control address System control address GND System control address System control chip selec System control write System control read Apply 3V System control data System control data VSS connected VSS connected VDD (2.7V) connected VSS connected System control data System control data System control data GND System control data System control data System control data 16.9/11.2/8.45MHz clock Apply 3V Mirror gate (Connect to TP141) Data part frequency control switch (Connect to TP304) Part CAPA switch (Connect to TP305) RF dropout / BCA data of making to binary Outer side CAPA detection Side of surroundings on inside GND VSS connected System reset Apply 3V 16.9MHz clock Frame mark detection ID gate for tracking holding (Connect to TP307) Jump prohibition
I/O I/O I/O I/O I/O I/O O O O O I I I I I O O O O
1-26
XV-521BK/523GD/525BK/421BK
Pin NO. 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132
Symbol LG NTRON DACDATA DACLRCK DACCLK IPFLAG BLKCK LRCK VSS OSCI1 OSCO1 VDD PVSS PVDD P1 P0 VSS SBCK SUBC NCLDCK CHCK40 DAT3 DAT2 DAT1 DAT0 VDD SCLOCK SDATA MONI3 MONI2 MONI1 MONI0 VSS NEJECT VDD NTRYCL NDASP NCS3FX NCS1FX VDD DA2 DA0
I/O O I O O I I I I I O I/O I/O O I I I I I I I/O I/O O O O O I I I/O I I I/O I/O
Function Land / group switch Tracking ON Sereal output (Connect to TP148) L and R identification output (Connect to TP149) Clock for serial output Interpolation flag input Sub-code,Block clock input (VSS connected) L and R identification signal output (VSS connected) GND 16.9MHz oscillation 16.9MHz oscillation Apply 3V GND Apply 3V Terminal MASTER polarity switch input (VDD 3V connected) CIRC-RAM OVER/UNDER Interruption signal input (VDD 3V connected) GND Sub-code, Clock output for serial input (Connect to TP306) Sub-code, Serial input Sub-code, Frame clock input Read clock to DAT3~0 (Output of dividing frequency four from ADSC) Read data from DISC (Parallel output from ADSC)
Apply 3V Debugging serial clock (Not use) (270 pull up) Debugging serial data (Not use) (270 pull up) Internal goods title monitor (Connect to TP150-TP153)
GND Eject detection Apply 2.7V Tray close detection (Not use) ATAPI Drive active/ Slave connection I/O ATAPI host chip selec (Not use) ATAPI host chip selec (Not use) Apply 3V ATAPI host address ATAPI host address (Not use) 1-27
XV-521BK/523GD/525BK/421BK
Pin NO. 133 134 135 136 137 138 139 140 141 142 143 144
Symbol NPDIAG VSS DA1 NIOCS16 INTRQ VDD NDMACK IORDY NIORD VSS NIOWR DMARQ
I/O I/O I/O O O I O I I/O O
Function ATAPI slave master diagnosis input GND ATAPI host address (Not use) ATAPI output of selection of width of host data bus ATAPI host interruption output Apply 3V ATAPI host DMA response (Not use) ATAPI host ready output (Connect to TP157) ATAPI host read (Not use) GND ATAPI host writes ATAPI host DMA request (Connect to TP159)
1-28
XV-521BK/523GD/525BK/421BK
MN67706ZY (IC201) : ADSC
33VDD 33VSS TEST MINTEST NCLDCK/JUMP SUBC IPFLAG DACCLK NTRON DACDATA/LG DACLRCK/JMPINH IDHOLD SBCK/PLLOK BLKCK/CPDET1 LRCK/CPDET2 IDGT/TEMUTE DTRD 25VDD 25VSS TILTN TILT TILTP FG SPDRV TRSDRV 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
CHCK40 DAT3 DAT2 DAT1 DAT0 33VSS 33VDD TX XRESET ENS ENC CPUIRQ CPUCLK CPUDTIN CPUDTOUT MONA MONB MONC NC 25VSS 25VDD LDCUR(AD6) TDOFS(AD5) TG(AD4) RFENV(AD3)
1.Terminal Layout
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
MN67706ZY
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
TSTSG BDO SYSCLK OFTR 33VDD 33VSS FBAL TBAL TGBAL AVSS ROUT LOUT AVDD JLINE DBALO VCOF TRCRS CMPIN LPFOUT LPFIN AVSS HPFOUT HPFIN AVDD VFOSHORT
2.Pin Functions Pin No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Symbol
AS(AD2) TE(AD1) FE(AD0) AVDD FODRV(DA1) TRDRV(DA0) AVSS ARF NARF IREF1 IREF2 DSLF1 DSLF2 AVDD VHALF PLPG PLFG VREFH RVI AVSS PLFLT1 PLFLT2 JITOUT RFDIF CSLFL1
I/O
I I I O O I I I I I/O I/O I I I/O O O I/O I I/O
AS(AD2) TE(AD1) FE(AD0) AVDD FODRV(DA1) TRDRV(DA0) AVSS ARF NARF IREF1 IREF2 DSLF1 DSLF2 AVDD VHALF PLPG PLFG VREFH RVI AVSS PLFLT1 PLFLT2 JITOUT RFDIF CSLFL1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Function
AS : Full adder signal(FEP) Phase difference/3 beam tracking error(FEP) Focus error(FEP) Apply 3.3V(For analog circuit) Focus drive(DRVIC) Tracking drive(DRVIC) Ground(For analog circuit) Equivalence RF+(FEP) Equivalence RF-(FEP) Reference current1(For DBAL) Reference current2(For DBAL) Connect to capacitor1 for DSL Connect to capacitor2 for DSL Apply 3.3V(For analog circuit) Reference voltage 1.65+-0.1V(FEP) Not use(PLL phase gain setting resistor terminal) Not use(PLL frequency gain setting resistor terminal) Reference voltage 2.2V+-0.1V(FEP) Connect to resistor for VREFH reference current source Ground(For analog circuit) Connect to capacitor1 for PLL Connect to capacitor2 for PLL Output for jitter signal monitor Not use Pull-up to VHALF
1-29
XV-521BK/523GD/525BK/421BK
Pin No.
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
Symbol
VFOSHORT AVDD HPFIN HPFOUT AVSS LPFIN LPFOUT CMPIN TRCRS VCOF DBALO JLINE AVDD LOUT ROUT AVSS TGBAL TBAL FBAL 33VSS 33VDD OFTR SYSCLK BDO TSTSG TRSDRV SPDRV FG TILTP TILT TILTN 25VSS 25VDD DTRD IDGT/TEMUTE LRCK/CPDET2 BLKCK/CPDET1 SBCK/PLLOK IDHOLD DACLRCK/JMPINH DACDATA/LG NTRON DACCLK IPFLAG SUBC NCLDCK/JUMP MINTEST TEST 33VSS 33VDD CHCK40 DAT3 DAT2 DAT1 DAT0
I/O
O I O I O I I I/O O O O O O O O I I I O O O I O O O I I O O I I I I O O O O O I I O O O O O
Function
VFO short output Apply 3.3V(For analog circuit) Pull-up to VHALF Connect to TP208 Ground(For analog circuit) Pull-up to VHALF Not use Connect to TP210 Input signal for track cross formation JFVCO control voltage DSL balance adjust output J-line setting output(FEP) Apply 3.3V(For analog circuit) Connect to TP203 (Analog audio left output) Connect to TP204 (Analog audio right output) Ground(For analog circuit) Tangential balance adjust(FEP) Tracking balance adjust(FEP) Focus balance adjust(FEP) Ground(For I/O) Apply 3.3V(For I/O) Off track signal 16.9344MHz system clock input(ODC) Drop out(FEP) Calibration signal(FEP) Traverse drive(DRVIC) Spindle drive output(DRVIC) FG signal input (Spindle motor driver) Connect to TP205 Connect to TP206 Connect to TP207 Ground(For internal core) Apply 2.5V(For internal core) Data read control signal(ODC) Pull-down to Ground LR channel data strobe(ODC)/ CD sub code synchronous signal(ODC)/ CD sub code data shift clock(ODC)/PLL pull-in OK signal input Pull-down to Ground 1bit DAC-LR channel data strobe(ODC)/ CD 1bit DAC channel data(ODC) L : Tracking ON(ODC) 1bit DAC channel data shift clock(ODC) CIRC error flag(ODC) CD sub code(ODC) CD sub code data frame clock(ODC)/DVD JUMP signal(ODC) Pull-down to Ground(For MINTEST) Pull-down to Ground(For TEST) Ground(For I/O) Apply 3.3V(For I/O) Clock for SRDATA(ODC) SRDATA3(ODC) SRDATA2(ODC) SRDATA1(ODC) SRDATA0(ODC)
1-30
XV-521BK/523GD/525BK/421BK
Pin No.
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
Symbol
33VSS 33VDD TX XRESET ENS ENC CPUIRQ CPUCLK CPUDTIN CPUDTOUT MONA MONB MONC NC 25VSS 25VDD LDCUR(AD6) TDOFS(AD5) TG(AD4) RFENV(AD3)
I/O
O I I I O I I O O O O O I I I I
Function
Ground(For I/O) Apply 3.3V(For I/O) Digital audio interface Reset input (System control) Servo DSC serial I/F chip select (System control) CIRC serial I/F chip select (System control) Interrupt request (System control) Syscon serial I/F clock (System control) Syscon serial I/F data input (System control) Syscon serial I/F data output (System control) Connect to TP226 (Monitor terminal A) Connect to TP225 (Monitor terminal A) Connect to TP224 (Monitor terminal A) Connect to TP211 Ground(For internal core) Apply 2.5V(For internal core)
Tangential phase difference(FEP) RF envelope input(FEP)
1-31
XV-521BK/523GD/525BK/421BK
NJM4580D (IC741, IC751) : LPF, Mic and H.phone Amp.
1.Terminal layout
A OUT A -IN
1
8
V+
2 A B
7 6
B OUT
A +IN V-
3
B -IN B +IN
4
5
(TOP VIEW)
2.Block diagram
V +
INPUT
+
OUTPUT
V-
IC-PST9140-T (IC702) : Reset IC
1. Block diagram
VCC
2
OUT
1
CO1 OP1
GND
3
1-32
XV-521BK/523GD/525BK/421BK NJM78M05FA (IC953) : Regulator
1. Terminal layout
2. Block diagram
1-33
XV-521BK/523GD/525BK/421BK
STR-G6651 (IC901) : Switch regulator
4
VIN
D START O.V.P LATCH
DRIVE 2
REG Vth(1) T.S.D O.S.C Comp.1 5
S
O.C.P/F.B Vth(2) Comp.2
3 GND
1-34
XV-521BK/523GD/525BK/421BK TC74VHC00FT-X (IC503) : Wright timing control
1.Terminal layout / Block diagram Vcc 14 4B 13 4A 12 4Y 11 3B 10 3A 9 3Y 8
TC7WH74FU-X (IC374) : Clock buffer
1.Terminal layout
2.Block diagram 1 1A 2 1B 3 1Y 4 2A 5 2B 6 2Y 7 GND
CK D Q GND
1 2 3 4
8 VCC 7 PR 6 CLR 5 Q
TC7SH32FU-X (IC312) : Timing control
1.Terminal layout
TC7SH08FU-X (IC311) : Timing control
IN B IN A 1 2
IN B 1 2 3 4 OUT Y 5 VCC
5 VCC
1.Terminal layout
GND 3
4 OUT Y
IN A GND
1-35
XV-521BK/523GD/525BK/421BK
ZIVA3-PE0 (IC501) : AV Decoder
ZIVA3-PEO (1/5)
Pin No.
1 2 3 4 5 6
Symbol PIO0 HDATA0 HDATA1 HDATA2 VDD-3.3 HDATA3
I/O I/O I/O I/O
7 8 9 10 11 12 13
VSS HDATA4 HDATA5 HDATA6 HDATA7 VDD-2.5 RESET
-
I/O I
Function Programmable I/O pins.Input mode after reset. 8-bit bi-derectional host data bus. writes data to the decoder Code FIFO via HDATA. MSB of the 32-bit word is written first. The host also reads and writes the decoder internal registers and local SDRAM via HDATA. 3.3-V supply voltage for I/O signals. 8-bit bi-derectional host data bus. writes data to the decoder Code FIFO via HDATA. MSB of the 32-bit word is written first. The host also reads and writes the decoder internal registers and local SDRAM via HDATA. Ground for core logic and I/O signals. 8-bit bi-derectional host data bus. writes data to the decoder Code FIFO via HDATA. MSB of the 32-bit word is written first. The host also reads and writes the decoder internal registers and local SDRAM via HDATA. 2.5-V supply voltage for core logic. Hardware reset. An external device asserts RESET(active LOW) to execute a decoder hardware reset. To ensure proper initialization after power is stable,assert RESET for at least 20 ms. Ground for core logic and I/O signals. Transfer not complate / data acknowledge. Active LOW to indicate host initiated transfer is not complate.WAIT is asserted after the falling edge of CS and reasserted when decoder is ready to complate transfer cycle. Open drain signal, must be pulled-up via 1kW to 3.3 volts. Driven high for 10 ns before tristate. Host interrupt. Open drain signal, must be pulled-up via 4.7kW to 3.3 volts. Driven high for 10 ns before tristate. 3.3-V supply voltage for I/O signals. No Connection Ground for core logic and I/O signals. No Connection
14 15
VSS
WAIT/DTACK
O
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
INT VDD-3.3 NC VSS NC PIO11 PIO12 PIO13 PIO14 PIO15 PIO16 VDD-3.3 PIO17 VSS PIO18 PIO19 PIO20 PIO21 PIO22 PIO23 VDD-3.3 PIO24 VSS PIO25 VDD-2.5 PIO26 VSS
O O O
I/O
Programmable I/O pins. Input mode after reset
I/O I/O
3.3-V supply voltage for I/O signals. Programmable I/O pins. Input mode after reset Ground for core logic and I/O signals. Programmable I/O pins. Input mode after reset
I/O
Programmable I/O pins. Output mode after reset
I/O I/O I/O -
3.3-V supply voltage for I/O signals. Programmable I/O pins. Output mode after reset Ground for core logic and I/O signals. Programmable I/O pins. Output mode after reset 2.5-V supply voltage for core logic. Programmable I/O pins. Output mode after reset Ground for core logic and I/O signals.
1-36
XV-521BK/523GD/525BK/421BK
ZIVA3-PEO (2/5)
Pin No. Symbol 44 PIO28 45 PIO29 46 PIO30 47 VDD-3.3 48 PIO31 49 VSS 50 NC 51 52 PIO1 53 MDATA15 54 MDATA0 55 VDD-3.3 56 MDATA14 57 VSS 58 MDATA1 59 MDATA13 60 MDATA2 61 VDD-3.3 62 MDATA12 63 VSS 64 MDATA3 65 VDD-2.5 66 MDATA11 67 VSS 68 MDATA4 69 VDD-3.3 70 MDATA10 71 VSS 72 MDATA5 73 MDATA9 74 MDATA6 75 VDD-3.3 76 MDATA8 77 VSS 78 MDATA7 79 LDQM 80 UDQM 81 VDD-3.3 82 MWE
I/O I/O I/O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O O O O O O
Function Programmable I/O pins. Output mode after reset 3.3-V supply voltage for I/O signals. Programmable I/O pins. Output mode after reset Ground for core logic and I/O signals. No Connection Programmable I/O pins. Input mode after reset Memory data Memory data 3.3-V supply voltage for I/O signals. Memory data. Ground for core logic and I/O signals. Memory data. 3.3-V supply voltage for I/O signals. Memory data. Ground for core logic and I/O signals. Memory data. 2.5-V supply voltage for core logic. Memory data. Ground for core logic and I/O signals. Memory data. 3.3-V supply voltage for I/O signals. Memory data. Ground for core logic and I/O signals. Memory data. 3.3-V supply voltage for I/O signals. Memory data. Ground for core logic and I/O signals. Memory data. SDRAM LDQM. SDRAM UDQM. 3.3-V supply voltage for I/O signals. SDRAM write enable. Decoder asserts active LOW to request a write operation to the SDRAM array. Ground for core logic and I/O signals. SDRAM system clock. Active LOW SDRAM column address. Active LOW SDRAM row address. 3.3-V supply voltage for I/o signals. Active LOW SDRAM bank select. Ground for core logic and I/O signals. Active LOW SDRAM bank select. 2.5-V supply voltage for core logic. No Connection. Ground for core logic and I/O signals. No Connection. 3.3-V supply voltage for I/O signals. Memory address. Ground for core logic and I/O signals. Memory address.
1-37
83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98
VSS SD-CLK SD-CAS SD-RAS VDD-3.3 SD-CS1 VSS SD-CS0 VDD-2.5 NC VSS NC VDD-3.3 MADDR9 VSS MADDR11
XV-521BK/523GD/525BK/421BK
ZIVA3-PEO (3/5)
Pin No.
99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145
Symbol MADDR8 MADDR10 VDD-3.3 MADDR7 VSS MADDR0 MADDR6 MADDR1 VDD-3.3 MADDR5 VSS MADDR2 MADDR4 MADDR3 VDD-3.3 NC VSS NC VDD-2.5 NC VSS NC VDD-3.3 NC VSS NC
I/O O O O O O O O O O O O
Function Memory address. 3.3-V supply voltage for I/O signals. Memory address. Ground for core logic and I/O signals. Memory address. 3.3-V supply voltage for I/O signals. Memory address. Ground for core logic and I/O signals. Memory address. 3.3-V supply voltage for I/O signals. No Connection Ground for core logic and I/O signals. No Connection 2.5-V supply voltage for core logic. No Connection Ground for core logic and I/O signals. No Connection 3.3-V supply voltage for I/O signals. No Connection Ground for core logic and I/O signals. No Connection Open drain signal, must be pulled-up via 4.7kW to 3.3 volts. Programmable I/O pins. Input mode after reset. No Connection Tie to VSS or VDD-3.3 Programmable I/O pins. Input mode after reset. 3.3-V supply voltage for I/O signals. Tie to VSS or VDD-3.3 Ground for core logic and I/O signals. Tie to VSS or VDD-3.3 Programmable I/O pins. Input mode after reset. Tie to VSS or VDD-3.3 Programmable I/O pins.Input mode after reset. Video data bus. Byte serial CbYCrY data synchronous with VCLK. At power-up, the decoder does not drive VDATA. During boot-up, the decoder uses configuration parameters to drive or 3-state VDATA 2.5-V supply voltage for core logic. Video data bus. Byte serial CbYCrY data synchronous with VCLK. At power-up, the decoder does not drive VDATA. During boot-up, the decoder uses configuration parameters to drive or 3-state VDATA Ground for core logic and I/O signals. Programmable I/O pins. Input mode after reset. Video data bus. Byte serial CbYCrY data synchronous with VCLK. At power-up, the decoder does not drive VDATA. During boot-up, the decoder uses configuration parameters to drive or 3-state VDATA
RESERVED O
I/O O RESERVED I PIO2 NC I/O RESERVED I VSS RESERVED I I/O PIO4 RESERVED I PIO3 VDD-3.3 PIO5 VDATA0 VDATA1 VDD-2.5 VDATA2 I/O O
O
146 147 148
VSS PIO6 VDATA3
I/O O
1-38
XV-521BK/523GD/525BK/421BK
ZIVA3-PEO (4/5)
Pin No.
149 150
Symbol VDD-3.3 VDATA4
I/O O
151 152
VSS VDATA5
O
153 154 155 156 157 158
PIO7 VDATA6 VDATA7 PIO8 HSYNC VSYNC
I/O O
I/O I/O I/O
159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185
DA-IEC VDD-3.3 DA-DATA0 VSS DA-DATA1 DA-DATA2 DA-DATA3 DA-LRCK DA-BCK VDD-2.5 DA-XCK VSS DAI-DATA DAI-LRCK DAI-BCK PIO9 CLKSEL A-VDD VCLK SYSCLK A-VSS
DVD-DATA0 /CD-DATA VDD-3.3 DVD-DATA1 /CD-LRCK
O O O
Function 3.3-V supply voltage for I/O signals. Video data buses for byte sequential CbYCrY data. The decoder does not run VDATA during the power up procedure. However, during booting the decoder uses operational configuration parameters or 3-state VDATA. Ground for core logic and I/O signals. Video data buses for byte sequential CbYCrY data. The decoder does not run VDATA during the power up procedure. However, during booting the decoder uses operational configuration parameters or 3-state VDATA. Programmable I/O pin. Input mode after resetting. Video data buses for byte sequential CbYCrY data. The decoder does not run VDATA during the power up procedure. However, during booting the decoder uses operational configuration parameters or 3-state VDATA. Programmable I/O. pins. Input mode after reset. Horizontal sync. The decoder begins outputting pixel data for a new horizontal line after the falling (active) edge of HSYNC. Vertical sync.Bi-directional, the decoder outputs the top border of a new field on the first HSYNC aftre the falling edge of VSYNC. VSYNC can accept vertical synchronization or top/bottom field notification from an external source. (VSYNC HIGH = bottom field. VSYNC LOW = Top field) Bistream data in IEC-1937 or PCM data out in IEC-958 format. 3.3-V supply voltage for I/O signals. PCM data out, eight channels. Serial audio samples relative to DA-BCK clock. Ground for core logic and I/O signals. PCM data out, eight channels. Serial audio samples relative to DA-BCK clock.
O O I/O I I I I/O I I I I I I I PCM left-right clock. Identifies the channel for each audio sample. the polarity is programmable. PCM bit clock. Divided by 8 from DA-XCK can be either 48 or 32 times the sampling clock. 2.5-V supply voltage for core logic. Audio master frequency clock. Used to generate DA-BCK and DA-LRCK. DA-XCK can be eigher 384 or 256 times the sampling frequency. Ground for core logic and I/O signals. PCM input data. two channels. Serial audio samples relative to DAI-BCK clock. PCM input left-right clock. PCM input bit clock. Programmable I/O pins. Input mode after reset. Clock Select: Internal = VDD, External = VSS 3.3-V analog supply voltage. Video clock. Clocks out data on input. VDATA7.Clock is typically 27 MHz. System clock.Decoder requires external 27 MHz TTL oscilator. Drive with the same 27-MHz as VCK. Analog ground for PLL Serial CD data. This pin is shared with DVD compressed data DVD-DATA0. 3.3-V supply voltage for I/O signals. Programmable polarity 16-bit word synchronization to the decoder (right channel HIGH). This pin is shared with DVD compressed data DVD-DATA1. Ground for core logic and I/O signals. CD bit clock. Decoder accept multiple BCK rates. This pin is shared with DVD compressed data DVD-DATA2. Asserted HIGH indicates a corrupted byte.Decoder keeps the previous valid picture on-screen unit the next valid picture is decoded. This pin is shares with DVD compressed data DVD-DATA3.
1-39
VSS
DVD-DATA2 /CD-BCK DVD-DATA3 /CD-C2PO
XV-521BK/523GD/525BK/421BK
ZIVA3-PEO (5/5)
Pin No.
Symbol
I/O
Function
186 187 188 189
190 191 192
193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
DVD-DATA7 I DVD parallel compressed data from DVD DSP. When DVD DSP sends 32-bit words, it must write the MSB first. /CDG-SCLK CDG-SDATA:CD+G (Subcode) Data.Indicates serial subcode data input. DVD-DATA6 CDG-VSFY:CD+G (Subcode)Frame Sync. Indicates frame-start or composite synchronization input. /CDG-SOS1 CDG-SOS1:CD+G (Subcode) Block Sync.Indicates block-start synchronization input. DVD-DATA5 CDG-SCLK: CD+G(Subcode)Clock. Indicates subcode data clock input or output. /CDG-VFSY DVD-DATA4 /CDG-SDATA PIO10 I/O Programmable I/O pins. Input mode after reset. VREQUEST O Video request. Decoder asserts VREQUEST to indicate that the video input buffer has available space.Polarity is programmable. VSTROBE I Video strobe. Programmable dual mode pulse. Asynchronous and synchronous. In Asynchronous mode, an external source pulses VSTROBE to indicate data is ready for transfer. In synchronous mode VSTROBE clock data. VDD-3.3 - 3.3-V supply voltage for I/O signals. NC O No Connection VSS - Ground for core logic and I/O signals. V-DACK I In synchronous mode, Video data acknowledge. Asserted when DVD data is valid.Polarity is programmable. VDD-2.5 - 2.5-V supply voltage for core logic. RESERVED I Tie to VSS or VDD-3.3 VSS - Ground for core logic and I/O signals. ERROR I Error in input data. If ERROR signal is not available from the DSP it must be grounded. HOST8SEL I Always Ttie to VDD-3.3 HADDR0 HADDR1 I Host address bus. 3-bit address bus selects one of eight host interface registers. HADDR2 DTACKSEL I Tie HIGH to select WAIT signal, LOW to select DTACK signal (Motorola 68K mode). CS I Host chip select.Host asserts CS to select the decoder for a read or write operation.The falling edge of this signal triggers the read or write operation. R/W I Read/write strobe in M mode. write strobe in l mode.Host asserts R/W LOW to select write and LOW to select read. RD I Read strobe in I mode. Must be held HIGH in M Mode
1-40
XV-521BK/523GD XV-525BK/421BK
VICTOR COMPANY OF JAPAN, LIMITED OPTICAL DISC BUSINESS DIV. PERSONAL & MOBILE NETWORK BUSINESS UNIT AV & MULTIMEDIA COMPANY 1644, Shimotsuruma, Yamato, Kanagawa 242-8514, Japan
No.20836
Printed in Japan 2000 06 (S)
DVD VIDEO PLAYER
XV-521BK/XV-523GD/XV-525BK XV-421BK
OPEN THEATER /CLOSE 3D-PHONIC POSITION TV POWER DVD POWER SUBTITLE AUDIO ANGLE TV/VIDEO DIGEST STROBE ZOOM
Introduction
1
Preliminary knowledge
4
1
TV 1
2
TV 2
3
TV 3
4
TV 4
5
TV 5
6
TV 6
7
TV 7
8
TV 8
9
TV 9
10
TV RETURN
0
TV 0
+10
TV 100+
Getting started
XV-521BK/XV-523GD/XV-525BK models
DVD PLAYER
OPEN/CLOSE PLAY SHUTTLE POWER STANDBY
12
SLOW
AMP VOL
TV VOL
TV ch
RETURN CHOICE
F.SEARC H
PLAY MODE DISPLAY SHIFT CANCEL TIME
H B.SEARC
B.SKIP
PLAY
F.SKIP
PAUSE
STOP
ENTE
MENU
R
TITLE
0
STOP
#
1
¡
UP LEFT
CURSOR
7
PAUSE
8
RIGHT
DOWN
TITLE CHAP. RESUME THEATER EACH
3D PHONIC
DOLBY
D I G I T A L
SKIP
Basic operations
¢
DVD / VDEO CD / CD
17
4
REMOTE CONTROL
OPEN THEATER /CLOSE 3D-PHONIC POSITION
TV POWER DVD POWER
SUBTITLE
AUDIO
ANGLE
TV/VIDEO
DIGEST
STROBE
ZOOM
Advanced operations
20
1
TV 1
2
TV 2
3
TV 3
4
TV 4
5
TV 5
6
TV 6
7
TV 7
8
TV 8
9
TV 9
10
TV RETURN
0
TV 0
+10
TV 100+
SLOW
AMP VOL
TV VOL
TV ch
RETURN CHOICE
F.SEARC H
PLAY MODE DISPLAY SHIFT CANCEL TIME
XV-421BK model
XV-421 DVD PLAYER
OPEN/CLOSE PLAY POWER STANDBY
H B.SEARC
B.SKIP
PLAY
F.SKIP
PAUSE
STOP
ENTE
MENU
R
TITLE
0
STOP
#
SEARCH
Initial settings
¡
35
UP LEFT
CURSOR
7
PAUSE
8
1
RIGHT
DOWN
TITLE CHAP. EACH RESUME THEATER
3D PHONIC
DOLBY
D I G I T A L
SKIP
4
¢
DVD / VDEO CD / CD
RM-SXV521J REMOTE CONTROL
'
INSTRUCTIONS
Additional information
41
For Customer Use: Enter below the Model No. and Serial No. which are located on the rear, bottom or side of the cabinet. Retain this information for future reference. Model No. Serial No.
LVT0435-001A [J]
Warnings, Cautions and Others Mises en garde, précautions et indications diverses
CAUTION
RISK OF ELECTRIC SHOCK DO NOT OPEN
CAUTION To reduce the risk of electrical shocks, fire, etc.: 1. Do not remove screws, covers or cabinet. 2. Do not expose this appliance to rain or moisture. ATTENTION Afin d'éviter tout risque d'électrocution, d'incendie, etc.: 1. Ne pas enlever les vis ni les panneaux et ne pas ouvrir le coffret de l'appareil. 2. Ne pas exposer l'appareil à la pluie ni à l'humidité. Caution POWER switch! Disconnect the mains plug to shut the power off completely. The POWER switch in any position does not disconnect the mains line. The power can be remote controlled. Attention Commutateur POWER! Déconnecter la fiche de secteur pour couper complètement le courant. Le commutateur POWER ne coupe jamais complètement la ligne de secteur, quelle que soit sa position. Le courant peut être télécommandé.
TO REDUCE THE RISK OF ELECTRIC SHOCK. DO NOT REMOVE COVER (OR BACK) NO USER SERVICEABLE PARTS INSIDE. REFER SERVICING TO QUALIFIED SERVICE PERSONNEL.
CAUTION:
The lightning flash with arrowhead symbol, within an equilateral triangle is intended to alert the user to the presence of uninsulated "dangerous voltage" within the product's enclosure that may be of sufficient magnitude to constitute a risk of electric shock to persons. The exclamation point within an equilateral triangle is intended to alert the user to the presence of important operating and maintenance (servicing) instructions in the literature accompanying the appliance.
For U.S.A.
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: Reorient or relocate the receiving antenna. Increase the separation between the equipment and receiver. Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. Consult the dealer or an experienced radio/TV technician for help.
IMPORTANT FOR LASER PRODUCTS IMPORTANT POUR LES PRODUITS LASER
1. CLASS 1 LASER PRODUCT 2. DANGER: Visible laser radiation when open and interlock failed or defeated. Avoid direct exposure to beam. 3. CAUTION: Do not open the top cover. There are no user serviceable parts inside the Unit; leave all servicing to qualified service personnel. 1. PRODUIT LASER CLASSE 1 2. ATTENTION: Radiation laser visible quand l'appareil est ouvert ou que le verrouillage est en panne ou désactivé. Eviter une exposition directe au rayon. 3. ATTENTION: Ne pas ouvrir le couvercle du dessus. Il n'y a aucune pièce utilisable à l'intérieur. Laisser à un personnel qualifié le soin de réparer votre appareil.
WARNING: TO REDUCE THE RISK OF FIRE OR ELECTRIC SHOCK, DO NOT EXPOSE THIS APPLIANCE TO RAIN OR MOISTURE.
For Canada/pour le Canada
CAUTION: TO PREVENT ELECTRIC SHOCK, MATCH WIDE BLADE OF PLUG TO WIDE SLOT, FULLY INSERT ATTENTION: POUR EVITER LES CHOCS ELECTRIQUES, INTRODUIRE LA LAME LA PLUS LARGE DE LA FICHE DANS LA BORNE CORRESPONDANTE DE LA PRISE ET POUSSER JUSQUAU FOND
For Canada/pour le Canada
THIS DIGITAL APPARATUS DOES NOT EXCEED THE CLASS B LIMITS FOR RADIO NOISE EMISSIONS FROM DIGITAL APPARATUS AS SET OUT IN THE INTERFERENCE-CAUSING EQUIPMENT STANDARD ENTITLED "DIGITAL APPARATUS", ICES-003 OF THE DEPARTMENT OF COMMUNICATIONS. CET APPAREIL NUMERIQUE RESPECTE LES LIMITES DE BRUITS RADIOELECTRIQUES APPLICABLES AUX APPAREILS NUMERIQUES DE CLASSE B PRESCRITES DANS LA NORME SUR LE MATERIEL BROUILLEUR: "APPAREILS NUMERIQUES", NMB-003 EDICTEE PAR LE MINISTRE DES COMMUNICATIONS.
Introduction
Table of contents
Introduction
Page 1
Features .................................................................... 1 Supplied accessories ............................................... 1 About this instruction manual ............................... 2 Notes on handling ................................................... 3
To locate a desired selection using 4 or ¢ ...... 21 To locate a desired scene by specifying the chapter number [CHAP. SEARCH] ....................................... 22 To locate a desired position in the current title or track [TIME SEARCH] .............................................. 22 To locate a desired scene from the digest display [DIGEST] .................................................................. 23
Preliminary knowledge
Names of parts and controls
Page 4 4 5 7 7
Special picture playback
To advance a still picture frame-by-frame .............. 24 To display still pictures [STROBE] ........................... 24 To playback in slow-motion [SLOW] ....................... 25 To zoom a scene [ZOOM] ......................................... 26
Front panel ................................................................... Remote control unit .................................................... Display window ........................................................... Rear panel ....................................................................
Changing the playback order
To playback in the desired order [PROGRAM] ....... 26 To playback in random order [RANDOM] ............... 27
Operational Principles
On-screen displays ...................................................... 8 To prevent the monitor from burning out [SCREEN SAVER] ...................................................... 9 On-screen guide icons .............................................. 10 How to use numeric buttons .................................... 10
Repeat playback
To repeat the current selection or all disc contents [REPEAT] ................................ 28 To repeat a desired part [A-B REPEAT] ................... 29
Selecting a scene angle of DVD VIDEO
To select a scene angle from the normal screen [ANGLE] ................................................................... 30 To select a scene angle from the angle list display [ANGLE] ................................................................... 30
About discs
Playable disc types .................................................... 11 Disc structure ............................................................. 11
Getting started
Connections
Page 12
Changing the language and sound
To select the subtitle language [SUBTITLE] ........... 31 To change the audio language or sound [AUDIO] . 31
Before making any connections .............................. 12 To