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INTEGRATED CIRCUITS

DATA SHEET
For a complete data sheet, please also download:
· The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC · The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC

HEF4520B MSI Dual binary counter
Product specification File under Integrated Circuits, IC04 January 1995

Philips Semiconductors

Product specification

Dual binary counter
DESCRIPTION The HEF4520B is a dual 4-bit internally synchronous binary counter. The counter has an active HIGH clock input (CP0) and an active LOW clock input (CP1), buffered outputs from all four bit positions (O0 to O3) and an active HIGH overriding asynchronous master reset input (MR). The counter advances on either the LOW to HIGH transition of the CP0 input if CP1 is HIGH or the HIGH to

HEF4520B MSI
LOW transition of the CP1 input if CP0 is low. Either CP0 or CP1 may be used as the clock input to the counter and the other clock input may be used as a clock enable input. A HIGH on MR resets the counter (O0 to O3 = LOW) independent of CP0, CP1. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

Fig.2 Pinning diagram.

HEF4520BP(N): HEF4520BD(F): HEF4520BT(D):

16-lead DIL; plastic (SOT38-1) 16-lead DIL; ceramic (cerdip) (SOT74) 16-lead SO; plastic (SOT109-1) (SOT109-1)

Fig.1 Functional diagram.

( ): Package Designator North America

PINNING CP0A, CP0B CP1A, CP1B MRA, MRB O0A to O3A O0B to O3B clock inputs (L to H triggered) clock inputs (H to L triggered) master reset inputs outputs outputs

FAMILY DATA, IDD LIMITS category MSI See Family Specifications

January 1995

2

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Dual binary counter HEF4520B MSI

Philips Semiconductors

Product specification

Dual binary counter
AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times 20 ns VDD V Propagation delays CP0 , CP1 On HIGH to LOW 5 10 15 5 LOW to HIGH MR On HIGH to LOW Output transition times HIGH to LOW 5 10 15 5 LOW to HIGH Minimum CP0 pulse width; LOW Minimum CP1 pulse width; HIGH Minimum MR pulse width; HIGH Recovery time for MR Set-up times CP0 CP1 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 CP1 CP0 Maximum clock pulse frequency 10 15 5 10 15 January 1995 fmax tsu tsu tRMR tWMRH tWCPH tWCPL 60 30 20 60 30 20 30 20 16 50 30 20 50 30 20 50 30 20 8 15 20 4 tTLH tTHL 60 30 20 60 30 20 30 15 10 30 15 10 15 10 8 25 15 10 25 15 10 25 15 10 16 30 40 120 60 40 120 60 40 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz 10 15 5 10 15 tPHL tPLH tPHL 110 50 40 110 50 40 75 35 25 220 100 80 220 100 80 150 70 50 ns ns ns ns ns ns ns ns ns SYMBOL MIN. TYP. MAX.

HEF4520B MSI

TYPICAL EXTRAPOLATION FORMULA 83 ns + (0,55 ns/pF) CL 39 ns + (0,23 ns/pF) CL 32 ns + (0,16 ns/pF) CL 83 ns + (0,55 ns/pF) CL 39 ns + (0,23 ns/pF) CL 32 ns + (0,16 ns/pF) CL 48 ns + (0,55 ns/pF) CL 24 ns + (0,23 ns/pF) CL 17 ns + (0,16 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL

see also waveforms Figs 4 and 5

Philips Semiconductors

Product specification

Dual binary counter
AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; input transition times 20 ns VDD V Dynamic power dissipation per package (P) 5 10 15 TYPICAL FORMULA FOR P (µW) 850 fi + (foCL) × VDD2 3 800 fi + (foCL) × VDD
2

HEF4520B MSI

where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) (foCL) = sum of outputs VDD = supply voltage (V)

10 200 fi + (foCL) × VDD2

Fig.4 Waveforms showing recovery time for MR; minimum CP0, CP1 and MR pulse widths.

January 1995

5

Philips Semiconductors

Product specification

Dual binary counter

HEF4520B MSI

Fig.5 Waveforms showing set-up times for CP0 to CP1 and CP1 to CP0, and propagation delays.

January 1995

6

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Dual binary counter HEF4520B MSI