Text preview for : 4555.pdf part of Philips 4555 Dual 1-of-4 decoder/demultiplexer
Back to : 4555.pdf | Home
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
· The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC · The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC
HEF4555B MSI Dual 1-of-4 decoder/demultiplexer
Product specification File under Integrated Circuits, IC04 January 1995
Philips Semiconductors
Product specification
Dual 1-of-4 decoder/demultiplexer
DESCRIPTION The HEF4555B is a dual 1-of-4 decoder/demultiplexer. Each has two address inputs (A0 and A1), an active LOW enable input (E) and four mutually exclusive outputs which are active HIGH (O0 to O3). When used as a decoder, E when HIGH, forces O0 to O3 LOW. When used as a demultiplexer, the appropriate output is selected by the information on A0 and A1 with E as data input. All unselected outputs are LOW.
HEF4555B MSI
Fig.2 Pinning diagram.
HEF4555BP(N): 16-lead DIL; plastic (SOT38-1) HEF4555BD(F): 16-lead DIL; ceramic (cerdip) (SOT74) HEF4555BT(D): 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America PINNING E A0 and A1 O0 to O3 enable inputs (active LOW) address inputs outputs (active HIGH)
FAMILY DATA, IDD LIMITS category MSI See Family Specifications
Fig.1 Functional diagram.
January 1995
2
Philips Semiconductors
Product specification
Dual 1-of-4 decoder/demultiplexer
HEF4555B MSI
Fig.3 Logic diagram (one decoder/multiplexer).
TRUTH TABLE INPUTS E L L L L H Notes 1. H = HIGH state (the more positive voltage) 2. L = LOW state (the less positive voltage) 3. X = state is immaterial A0 L H L H X A1 L L H H X O0 H L L L L OUTPUTS O1 L H L L L O2 L L H L L O3 L L L H L
January 1995
3
Philips Semiconductors
Product specification
Dual 1-of-4 decoder/demultiplexer
AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times 20 ns VDD V Propagation delays An On HIGH to LOW 5 10 15 5 LOW to HIGH En On HIGH to LOW 10 15 5 10 15 5 LOW to HIGH Output transition times HIGH to LOW 10 15 5 10 15 5 LOW to HIGH 10 15 tTLH tTHL tPLH tPHL tPLH tPHL 115 45 30 140 55 40 125 50 30 150 55 40 60 30 20 60 30 20 230 ns 90 ns 65 ns 280 ns 105 ns 75 ns 250 ns 95 ns 65 ns 295 ns 110 ns 75 ns 120 ns 60 ns 40 ns 120 ns 60 ns 40 ns SYMBOL MIN. TYP. MAX.
HEF4555B MSI
TYPICAL EXTRAPOLATION FORMULA 88 ns + (0,55 ns/pF) CL 34 ns + (0,23 ns/pF) CL 22 ns + (0,16 ns/pF) CL 113 ns + (0,55 ns/pF) CL 44 ns + (0,23 ns/pF) CL 32 ns + (0,16 ns/pF) CL 98 ns + (0,55 ns/pF) CL 39 ns + (0,23 ns/pF) CL 22 ns + (0,16 ns/pF) CL 123 ns + (0,55 ns/pF) CL 44 ns + (0,23 ns/pF) CL 32 ns + (0,16 ns/pF) CL 10 ns + ((1,0 ns/pF) CL 9 ns + 6 ns + 10 ns + 9 ns + 6 ns + (0,42 ns/pF) CL (0,28 ns/pF) CL (1,0 ns/pF) CL (0,42 ns/pF) CL (0,28 ns/pF) CL
VDD V Dynamic power dissipation per package (P) 5 10 15
TYPICAL FORMULA FOR P (µW) 4500 fi + (foCL) × VDD2 18 800 fi + (foCL) × 45 700 fi + (foCL) × VDD2 VDD2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) (foCL) = sum of outputs VDD = supply voltage (V)
APPLICATION INFORMATION Some examples of applications for the HEF4555B are: · Code conversion. · Address decoding. · Demultiplexing: when using the enable input as data input.
January 1995
4