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Chassis M35&36 Service Manual
SERVICE MANUAL FOR M35&36 CHASSIS
PART I. Servicing Precautions
When working, the unit is with ultra high voltage about 25KV inside. So, to avoid the risk of electric shock, be careful to adjust the chassis! 1. Only qualified personnel should perform service procedures. 2. All specification must be met over line voltage ranger of 160V AC to 240V AC 50Hz/60Hz. 3. Do not operate in WET/DAMP conditions. 4. Portions of the power supply board are hot ground. The remaining boards are cold ground. 5. Discharge of CRT anode should be done only to CRT ground strap. 6. When fuse blow, ensure to replace a fuse with the same type and specification. 7. Keep the wires away from the components with high temperature or high voltage. 8. When replacing the resister with high power, keep it over the PCB about 10mm. 9. The CRT anode high voltage has been adjusted and set in the factory. When repairing the chassis, do not make the high voltage exceed 27.5KV (The beam current is 0uA). Generally, the high voltage is set on 25.5KV 1.5KV (The beam current is 700uA). * The values of parameters above are for information only. 10. Before return the fixed unit, do check all the covering of wires to ensure that not fold or not short with any metal components. Check the entire protection units, such as control knobs, rear cabinet & front panel, insulation resister & capacitor, mechanical insulators and so on. 11. There are some mechanical and electrical parts associating with safety (EMC) features (Generally related to high voltage or high temperature or electric shock), these features cannot be found out from the outside. When replace these components, perhaps the voltage and power suit the requirements, but efficient X-ray protection may not be provided. All these components are marked with in the schematic diagram. When replace these, you'd better look up the components listed in this manual. If the component you replaced not has the same safety (EMC) performance, harmful X-ray may be produced.
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Part -Product Specification
1. Ambient conditions: 1.1 Ambient temperatures: ~ +40 a. Operating: -10 b. Storage: -15 ~ +45 1.2 Humidity a. Operation: < 80% b. Storage: < 90% 1.3 Air pressure: 86kpa ~ 106kpa 2. Chassis Specification 2.1 MCU/Video/Teletext IC: VCT 3831A Super one chip IC
Chassis M35&36 Service Manual
2.2 System [ M35:PAL-DK.1 M36:PAL-DK/BG ] SECAM DK/BG Receiving channels CATV 470MHz Scanning lines and frequencies 525/625 lines 15.625kHz/15.75kHz 50/60Hz Color sub-carrier 4.433MHz/3.579MHz 2.3 IF:picture 38.9MHz sound 5.5MHz/6.0MHz/6.5MHz 2.4 Power Consumption:120W (M36 ) 2.5 Power Supply: AC 220V 45-55Hz 2.6 Audio Output Power(7%THD): 29" >6W+6W (M36) 2.7 Aerial Input Impedance:75 Unbalanced Din Jack Ant.Input 21" 3W+3W (M35) 70W (M35)
2.8 Product Safety Requirement: CE 2.9 Product EMC/EMI Requirement: CE 3. Basic Feature of Controller 3.1 Channel Tuning Method: Voltage Synthesizer 3.2 Presettable Program:100 Programs 3.3 Tuning for VHF and UHF Bands: Auto/Manual/Fine Tuning 3.4 Picture and Sound Adjustment Bright, Contrast, Color and Volume Control; Tint Control(NTSC);
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[Treble, Bass, Balance Control (M36 have these, but M35 haven't)] Sharpness Control
Chassis M35&36 Service Manual
3.5 OSD General Features(Volume, Brightness, Contrast, Color, Program, Band, Auto Search, Manual, Tune, Muting, AV And Sleep Timer) Stereo Dual Language Four Sound Effect Indicator 3.6 Sleep Timer:15MIN 3.7 Remote Effective Distance:8m 3.8 Construction of Front Panel Main Power Switch Remote Sensor Menu Select TV/AV Select Standby Indicator Program Volume UP/DOWN RCA Socket (Side) 3.9 Construction of Rear Panel 75 Aerial Terminal RCA Socket (AV Input Only) Scart Socket S.VHS Input Specification Video input 75 Audio input 10k (R+L) Video output 75 Audio output 1k (R+L) RGB input 75 Audio line output 1k
Scart 1Vp-p
0.5Vrms
1Vp-p 0.5Vrms 0.7Vp-p 1Vp-p
RCA 1Vp-p 0.5Vrms 1Vp-p 0.5Vrms
Design and specifications are subject to change without prior notice for the purpose of performance improvement. This specification is only for your reference.
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Part
RF IN
Chassis M35&36 Service Manual
-Brief Introduction On Chassis
TUNE R Z101(Z102) SAWFILTER IF AMP M52760 IF
X-TAL 20.25MHz
Key Sensor
IC 201 VCT3831A
I2C B US SCART 24C016 E2PROM
Video AMP And Sense IC301 V-OUTPUT TDA8172 Q401,Q402 H DRIVE IC601 TDA7057 T802 POWER TRANS IS TOR B+, 16V 33V 9V,5V,3.3V
Hi-POT
AV2 IN I2C B US IC1001 MSP3415G AC220V
H-OUTP UT FBT(T401)
DT801
IC801 MC44608
Q801
M35 and M36 use a high-quality singlechip IC VCT3831A as TV processors . It is a combo IC with TV process unit and CPU inside. The follows are the operation theory with example of M35. 1. Tuning section This section mainly consists of tuner and its accessory circuits. VCT3831A will control the band switching via Pin7 and Pin 10. (See table 1) VCT3831A sends out a 5Vp-p VT signal with pulse-width PIN 7 PIN 10 BAND modulation from Pin6. This signal is amplified with phase High level Low level VHF-L Low level High level VHF-H inversion by Q210, and changed to a 33Vp-p pulse signal with High level High level UHF pulse-width modulation. R255, C242, R256, C101, R101 and C102 compose a triple integral circuit, which is in charge of changing the 33Vp-p PWM signal to a DC tuning voltage which is variable from 0V to 33V. The tuner will select the corresponding channel according to the tuning voltage. If the sync signal and AFT signal cannot be inputted to the control section of VCT3831A, the auto tuning function will be invalidated. During the auto tuning process, the CVBS out from IC101, which is in charge of IF amplifying and demodulation, enter VCT3831A from Pin19. This CVBS will be treated by sync separation circuit inside VCT3831A and sends out a H-sync signal to the control unit of VCT3831A. If the H sync is detected by the control unit of VCT3831A, CPU will consider that a channel will be locked soon. So the tuning speed will slower automatically. On the other hand, an AFT signal out from Pin2 of IC101 enter VCT3831A from Pin9 of it. The control unit of VCT3831A will detect the accuracy of tuning according to the voltage of AFT signal. Bythis way, tuning with high accuracy can be achieved. And the corresponding tuning data will be stored in memory IC. Then the auto tuning process will go on and auto stop at the end (VFH-L VFH-H UHF) . 2. VIF section The tuner sends out IF signal from Pin IF. This signal is amplified about 20db by Q101. Having passed the
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Chassis M35&36 Service Manual
SAWZ101 and Z101A, the IF signal is inputted into IC101 from Pin4-5 (VIF input) and Pin7 (SIF input). The VIF signal pass the video amplifier and video detector and is changed to CVBS. And IC101 sends out CVBS from Pin18 of itself. Having passed Q104 and Q105 and the trapper network consisted by L102, Z104 and Z105, CVBS is divide into two way. One enter IC201 from Pin19. And another pass Q903 and arrive the video output terminal of TV. IC101 sends out QIF signal from Pin13 of itself. QIF signal enters the sound process circuit which is mainly consisted by IC1001. A 38.9MHz VCO coil is connected with Pin 15 and 16 of IC101. By adjusting the magnetic core of T101, the AFT curve can match the standard. IF AGC delay signal comes out from Pin1 of IC101, and goes to tuner for high frequency signal amplifying with auto-gain control. 3. Sound process section M35/36 chassis adopts MSP3415G made by Micronas also as sound process IC. This IC can process the stereo signal and NICAM signal. The QIF signal pass a high pass filter network consisted by C1024, C1024A and L1102, and enter IC1001 from Pin47. This QIF signal is changed to sound signal via amplitude-limit amplifier and frequency discrimination circuit and sound deemphasis circuit inside the sound process IC. On the other hand, the two way audio signals from audio input terminal enter IC1001 from Pin42/44 and Pin39/40, they and the TV sound signal will be switched by IC1001. IC1001 selects one way sound signal from these three ways and divide it into two ways: One way is from Pin 24/25 to the audio amplifier circuit which is mainly consisted by TDA7057AQ and to drive the speakers. Another way is from Pin30/31 to audio out terminal of TV. VCT3831A sends out the volume control signal via Pin64 to control the speakers volume. 4. Video signal process section The video signal from sound IF filter circuit enter IC201 via Pin19, and pass a video amplifier inside of IC. Then the video signal is splitted into two ways, one way to the sync-separation circuit, another one to the clamp circuit, black strength circuit, luminance delay line, sharpness improvement circuit. Then this signal is done with matrix operation with the C signal, which is from the chroma process unit, in the matrix circuit. The finally result is IC201 output R/G/B signal to CRT board from Pin42/43/44 and to drive the CRT. Another video signal which come from video input terminal of TV, is switched by electrical switch inside IC201 and out from pin11 of IC201 as the video output signal to video output terminal. 5. Chroma process section The chroma signal is separated from the video signal, which is from pin19 or pin20 or 21 (video input or TV video signal), after having passed a band/ high pass filter. Then the chroma signal is amplified by ACC circuit and splitted into two ways. One way goes to the demodulation unit and another way goes to the APC circuit to make the chroma subcarrier oscillator to generate reference subcarrier signal which is needed for sync demodulation, and to sent it to the demodulation unit. The R-Y and B-Y signal demodulated from chroma signal are sent to color system recognition circuit. Having passed the system recognition switch circuit, it goes to 1H delay line and other control circuit. Finally it goes to matrix circuit. The Y signal from luminance process unit will be done with matrix operation with R-Y and B-Y signal via matrix circuit. If the color system is NTSC, the TINT circuit is enabled. This TINT circuit is a phase shift circuit. It can change the phase of the reference subcarrier which is sent to APC circuit and to shift the APC output voltage, therefore , to change the oscillator frequency (phase) of chroma VCO. So the chroma will be changeable.
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6. Vertical output section IC VCT3831A outputs vertical saw-tooth waveform from Pin33. It comes to pin1 of TDA8172 with DC coupling. And it is amplified by inner difference amplifier. Pin7 of TDA8172 is the same phase input terminal. R302 is DC offset resistances. In application to M35, pin7 of TDA8172 is connected with Pin34 vert0. The amplified saw tooth-wave comes out from pin5 and make the deflect coil to generate the deflect current. R307 and C305 filtrate the inductive interference from the horizontal deflect coil. C307 is used to eliminate spurious oscillation generated by the deflect coil and distributed capacitance resonance. R312, R320 and accessory circuit are in charge of draw AC saw tooth wave out, and feedback to the input terminal of TDA8172 (pin1) to correct the linearity of horizontal scan. D302 and C301 make up of a voltage pump up circuit. TDA8172 output a vertical kickback impulse from pin6 to locate the OSD characters. 7. Horizontal Output And FBT Section The processor outputs horizontal drive impulse from pin24 H-OUT. The drive impulse is done with voltage division by R268 and D401, and then comes to the base of the drive triode (Q401). C401 is used to eliminate the noise in the H drive impulse. T402 is a horizontal drive transformer. Q402 is a horizontal output triode with a damper inside. The deflect coil and the horizontal output triode have some resistance R while they are ducting. The resistance R will cause the non-linear distortion, which means that the right direction scanning speed of the electron beam becomes slower, and the right of the raster is compressed to generate distortion. We use a horizontal linear adjuster to compensate this kind of distortion. We use L402 as the H linear adjuster in horizontal scanning section of M35 chassis. R409, which is parallel connected with L402 and L401, is a despiking resistance for preventing the oscillation by compensating inductor and the stray capacitance. The linear adjuster is a transductor coil with a magnetic core inside. If the current, which pass the linear adjuster coil, increase to a certain value, the magnetic core becomes saturated to decrease the inductance of the linear adjustment inductor. If the +B is steady, the increase speed of Iy is faster to compensate the reducing of deflecting current by the resistance R mention above. We can adjust the magnetic core to change the inductance of the linear compensate inductor to adjust the H linearity.
M36 Block Diagram
RF IN
(Consult above M35 part for Brief Introduction on Chassis)
IF AMP M52760 IF Key Sensor
TUNER
Z101(Z102) SAWFILTER
X-TAL 20.25MHz
IC 201 VCT3831A
I2C BUS
Video AMP And Sense IC301 V-OUTPUT TDA8172 Q401,Q402 H DRIVE IC602 TDA8944 T802 POWER TRANSISTOR B+, 18V 33V 9V,5V,3.3V
Hi-POT
SCART
24C16 E2PROM
I2C BUS
AV2 IN
H-OUTPUT FBT(T401)
IC901 MSP3415G/MSP346CG AC220V
DT801
IC801 MC44608
Q801
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PART IV. IC Pin Description 1. MC44608-High Voltage PWM Controller
Pin 1 Name Demag
Chassis M35&36 Service Manual
2
Isense
3 4 5 6 7
Control Input Ground Driver VCC
Description The Demag pin offers 3 different functions: Zero voltage crossing detection (50mV), 24 A current detection and 120 A current detection. The 24 A level is used to detect the secondary reconfiguration status and the 120 A level to detect an Over Voltage status called Quick OVP. The Current Sense pin senses the voltage developed on the series resistor inserted in the source of the power MOSFET. When Isense reaches 1V, the Driver output (pin 5) is disabled. This is known as the Over Current Protection function. A 200 A current source is flowing out of the pin 3 during the startup phase and during the switching phase in case of the Pulsed Mode of operation. A resistor can be inserted between the sense resistor and the pin 3, thus a programmable peak current detection can be performed during the SMPS standby mode. A feedback current from the secondary side of the SMPS via the optocoupler is injected into this pin. A resistor can be connected between this pin and GND to allow the programming of the Burst duty cycle during the Standby mode. This pin is the ground of the primary side of the SMPS. The current and slew rate capability of this pin are suited to drive Power MOSFETs. This pin is the positive supply of the IC. The driver output gets disabled when the voltage becomes higher than 15V and the operating range is between 6.6V and 13V. An intermediate voltage level of 10V creates a disabling condition called Latched Off phase. This pin is to provide isolation between the Vi pin 8 and the VCC pin 6. This pin can be directly connected to a 500V voltage source for startup function of the IC. During the Startup phase a 9 mA current source is internally delivered to the VCC pin 6 allowing a rapid charge of the VCC capacitor. As soon as the IC startsup, this current source is disabled.
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Vi
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OPERATING DESCRIPTION
Chassis M35&36 Service Manual
Regulation The pin 3 senses the feedback current provided by the opto-coupler. During the switching phase the switch S2 is closed and the shunt regulator is accessible by the pin 3. The shunt regulator voltage is typically 5V. The dynamic resistance of the shunt regulator represented by the zener diode is 20 . The gain of the Control input is given on Figure 10 which shows the duty cycle as a function of the current injected into the pin 3. The maximum current sense threshold is fixed at 1V. The peak A 4KHz filter network is inserted between the shunt regulator and the PWM comparator to cancel the high frequency residual noise. The switch S3 is closed in Standby mode during the Latched Off Phase while the switch S2 remains open. (See section PULSED MODE DUTY CYCLE CONTROL). The resistor Rdpulsed (Rduty cycle burst) has no effect on the regulation process. This resistor is used to determine the burst duty cycle. PWM Latch The MC44608 works in voltage mode. The ontime is controlled by the PWM comparator that compares the oscillator sawtooth with the regulation block output. The PWM latch is initialized by the oscillator and is reset by the PWM comparator or by the current sense comparator in case of an over current. This configuration ensures that only a single pulse appears at the circuit output during an oscillator cycle. Current Sense The inductor current is converted to a positive voltage by inserting a ground reference sense resistor RSense in series with the power switch.
The maximum current sense threshold is fixed at 1V. The peak current is given by the following equation: Ipkmax = 1/Rsense( ) (A) In standby mode, this current can be lowered as due to the activation of a 200 A current source: IpkMAX-STBY The current sense input consists of a filter (6k , 4pF) and of a leading edge blanking. Thanks to that, this pin is not sensitive to the power switch turn on noise and spikes and practically in most applications, no filtering network is required to sense the current. Finally, this pin is used:
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as a protection against over currents (Isense > I) as a reduction of the peak current during a Pulsed Mode switching phase. The overcurrent propagation delay is reduced by producing a sharp output turn off (high slew rate). This results in an abrupt output turn off in the event of an over current and in the majority of the pulsed mode switching sequence. Demagnetization Section The MC44608 demagnetization detection consists of a comparator designed to compare the VCC winding voltage to a reference that is typically equal to 50mV. This reference is chosen low to increase effectiveness of the demagnetization detection even during startup. A latch is incorporated to turn the demagnetization block output into a low level as soon as a voltage less than 50 mV is detected, and to keep it in this state until a new pulse is generated on the output. This avoids any ringing on the input signal which may alter the demagnetization detection.
For a higher safety, the demagnetization block output is also directly connected to the
output, which is disabled during the demagnetization phase. The demagnetization pin is also used for the quick programmable OVP. In fact, the demagnetization input current is sensed so that the circuit output is latched off when this current is detected as higher than 120 A. This function can be inhibited by grounding it but in this case, the quick and programmable OVP is also disabled. Oscillator The MC44608 contains a fixed frequency oscillator. It is built around a fixed value capacitor CT succesively charged and discharged by two distinct current sources ICH and IDCH. The window comparator senses the CT voltage value and activates the sources when the voltage is reaching the 2.4V/4V levels.
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The complete demagnetization status DMG is used to inhibit the recharge of the CT capacitor. Thus in case of incomplete transformer demagnetization the next switching cycle is postpone until the DMG signal appears. The oscillator remains at 2.4V corresponding to the sawtooth valley voltage. In this way the SMPS is working in the so called SOPS mode (Self Oscillating Power Supply). In that case the effective switching frequency is variable and no longer depends on the oscillator timing but on the external working conditions (Refer to DMG signal in the Figure 5). The OSC and Clock signals are provided according to the Figure 5. The Clock signals correspond to the CT capacitor discharge. The bottom curve represents the current flowing in the sense resistor Rcs. It starts from zero and stops when the sawtooth value is equal to the control voltage Vcont. In this way the SMPS is regulated with a voltage mode control. Overvoltage Protection
The MC44608 offers two OVP functions: a fixed function that detects when VCC is higher than 15.4V a programmable function that uses the demag pin. The current flowing into the demag pin is mirrored and compared to the reference current Iovp (120 A). Thus this OVP is quicker as it is not impacted by the VCC inertia and is called QOVP. In both cases, once an OVP condition is detected, the output is latched off until a new circuit STARTUP.
Startup Management
The Vi pin 8 is directly connected to the HV DC rail Vin. This high voltage current source is
internally connected to the VCC pin and thus is used to charge the VCC capacitor. The VCC capacitor charge period corresponds to the Startup phase. When the VCC voltage reaches 13V, the high voltage 9mA current source is disabled and the device starts working. The device enters into the switching phase. It is to be noticed that the maximum rating of the Vi pin 8 is 700V. ESD protection circuitry is not currently added to this pin due to size limitations and technology constraints. Protection is limited by the drainsubstrate junction in avalanche breakdown. To help increase the application safety against high
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Chassis M35&36 Service Manual
voltage spike on that pin it is possible to insert a small wattage 1k series resistor between the Vin rail and pin 8. The Figure 6 shows the VCC voltage evolution in case of no external current source providing current into the VCC pin during the switching phase. This case can be encountered in SMPS when the self supply through an auxiliary winding is not present (strong overload on the SMPS output for example). The Figure16 also depicts this working configuration. In case of the hiccup mode, the duty cycle of the switching phase is in the range of 10%. Mode Transition The LW latch Figure 7 is the memory of the working status at the end of every switching sequence. Two different cases must be considered for the logic at the termination of the SWITCHING PHASE: 1.No Over Current was observed 2.An Over Current was observed These 2 cases are corresponding to the signal labeled NOC in case of "No Over Current" and "OC" in case of Over Current. So the effective working status at the end of the ON time memorized in LW corresponds to Q=1 for no over current and Q=0 for over current. This sequence is repeated during the Switching phase. Several events can occur: 1. SMPS switch OFF 2. SMPS output overload 3. Transition from Normal to Pulsed Mode 4. Transition from Pulsed Mode to Normal Mode 1. SMPS SWITCH OFF When the mains is switched OFF, so long as the bulk electrolithic bulk capacitor provides energy to the SMPS, the controller remains in the switching phase. Then the peak current reaches its maximum peak value, the switching frequency decreases and all the secondary voltages are reduced. The VCC voltage is also reduced. When VCC is equal to 10V, the SMPS stops working. 2. Overload In the hiccup mode the 3 distinct phases are described as follows (refer to Figure 6): The SWITCHING PHASE: The SMPS output is low and the regulation block reacts by increasing the ON time (dmax = 80%). The OC is reached at the end of every switching cycle. The LW latch (Figure 7) is reset before the VPWM signal appears. The SMPS output voltage is low. The VCC voltage cannot be maintained at a normal level as the auxiliary winding provides a voltage which is also reduced in a ratio similar to the one on the output (i.e. Vout nominal / Vout shortcircuit). Consequently the VCC voltage is reduced at an operating rate given by the combination VCC capacitor value together with the ICC working consumption (3.2mA) according to the equation 2. When VCC crosses 10V the WORKING PHASE gets
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Chassis M35&36 Service Manual
terminated. The LW latch remains in the reset status. The LATCHEDOFF PHASE: The VCC capacitor voltage continues to drop. When it reaches 6.5V this phase is terminated. Its duration is governed by equation 3. The STARTUP PHASE is reinitiated. The high voltage startup current source (ICC1 = 9mA) is activated and the MODE latch is reset. The VCC voltage ramps up according to the equation 1. When it reaches 13V, the IC enters into the SWITCHING PHASE. The NEXT SWITCHING PHASE: The high voltage current source is inhibited, the MODE latch (Q=0) activates the NORMAL mode of operation. Figure 2 shows that no current is injected out pin 2. The over current sense level corresponds to 1V. As long as the overload is present, this sequence repeats. The SWITCHING PHASE duty cycle is in the range of 10%. 3. Transition from Normal to Pulsed Mode In this sequence the secondary side is reconfigured (refer to the typical application schematic). The high voltage output value becomes lower than the NORMAL mode regulated value. The TL431 shunt regulator is fully OFF. In the SMPS standby mode all the SMPS outputs are lowered except for the low voltage output that supply the wakeup circuit located at the isolated side of the power supply. In that mode the secondary regulation is performed by the zener diode connected in parallel to the TL431. The secondary reconfiguration status can be detected on the SMPS primary side by measuring the voltage level present on the auxiliary winding Laux. (Refer to the Demagnetization Section). In the reconfigured status, the Laux voltage is also reduced. The VCC selfpowering is no longer possible thus the SMPS enters in a hiccup mode similar to the one described under the Overload condition. In the SMPS standby mode the 3 distinct phases are: The SWITCHING PHASE: Similar to the Overload mode. The current sense clamping level is reduced according to the equation of the current sense section. The C.S. clamping level depends on the power to be delivered to the load during the SMPS standby mode. Every switching sequence ON/OFF is terminated by an OC as long as the secondary Zener diode voltage has not been reached. When the Zener voltage is reached the ON cycle is terminated by a true PWM action. The proper SWITCHING PHASE termination must correspond to a NOC condition. The LW latch stores this NOC status. The LATCHED OFF PHASE: The MODE latch is set. The STARTUP PHASE is similar to the Overload Mode. The MODE latch remains in its set status (Q=1). The SWITCHING PHASE: The Standby signal is validated and the 200 A is sourced out of the Current Sense pin 2. 4. Transition from Standby to Normal The secondary reconfiguration is removed. The regulation on the low voltage secondary rail can no longer be achieved, thus at the end of the SWITCHING PHASE, no PWM condition can be encountered. The LW latch is reset. At the next WORKING PHASE a NORMAL mode status takes place. In order to become independent of the recovery time SWITCHING PHASE constant on the secondary side of the SMPS an additional reset input R2 is provided on the MODE latch. The condition Idemag<24 A corresponds to the activation of the secondary reconfiguration status. The R2 reset insures a return into the NORMAL mode following the first corresponds to 1V. STARTUP PHASE.
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Chassis M35&36 Service Manual
Pulsed Mode Duty Cycle Control During the sleep mode of the SMPS the switch S3 is closed and the control input pin 3 is connected to a 4.6V voltage source thru a 500 resistor. The discharge rate of the VCC capacitor is given by ICClatch (device consumption during the LATCHED OFF phase) in addition to the current drawn out of the pin 3. Connecting a resistor between the Pin 3 and GND (RDPULSED) a programmable current is drawn from the VCC through pin 3. The duration of the LATCHED OFF phase is impacted by the presence of the resistor RDPULSED. The equation 3 shows the relation to the pin 3 current. Pulsed Mode Phases Equations 1 through 8 define and predict the effective behavior during the PULSED MODE operation. The equations 6, 7, and 8 contain K, Y, and D factors. These factors are combinations of measured parameters. They appear in the parameter section "K factors for pulsed mode operation". In equations 3 through 8 the pin 3 current is the current defined in the above section "Pulsed Mode Duty Cycle Control".
2. TDA8172
TV Vertical Deflection Output Circuit
General Description The TDA8172 is a monolithic integrated circuit. It is a high efficiency power booster for direct driving of vertical windings of TV yokes. It is intended for use in Color and B&W television. Pin Connections (top view)
Block Diagram
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3. TDA8944 2
Chassis M35&36 Service Manual
7W stereo Bridge Tied Load (BTL) Audio Amplifier
General Description The TDA8944 is a dual-channel audio power amplifier with an output power of 2 7W at an 8 load and a 12V supply. The circuit contains two Bridge Tied Load (BTL) amplifiers with an all-NPN output stage and standby/mute logic. The TDA8944 comes in a 17-pins DIL-bent-SIL (DBS) power package. Features Few external components Fixed gain Standby and mute mode No on/off switching plops Low standby current High supply voltage ripple rejection Outputs short-circuit protected to ground, supply and across the load Thermally protected Printed-circuit board compatible. Block Diagram and Pin Configuration
Pin Description No. Symbol
1 2 3 4 5 6 7 OUT1- GND1 VCC1 OUT1+ n.c. IN1+ n.c.
Pin
1 2 3 4 5 6 7 negative loudspeaker terminal 1 ground channel 1 supply voltage channel 1 positive loudspeaker terminal 1 not connected positive input 1 not connected
Description
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No.
8 9 10 11 12 13 14 15 16 17
Chassis M35&36 Service Manual Symbol
IN1- IN2- MODE SVR IN2+ n.c. OUT2- GND2 VCC2 OUT2+
Pin
8 9 10 11 12 13 14 15 16 17
Description
negative input 1 negative input 2 mode selection input (standby, mute, operating) half supply voltage decoupling (ripple rejection) positive input 2 not connected negative loudspeaker terminal 2 ground channel 2 supply voltage channel 2 positive loudspeaker terminal 2
Functional Description
The TDA8944J is a stereo BTL audio power amplifier capable of delivering 2 × 7 W output power to an 8 load at THD = 10%, using a 12 V power supply and an external heat sink. The voltage gain is fixed at 32 dB. With the three-level MODE input the device can be switched from `standby' to `mute' and to `operating' mode. The TDA8944J outputs are protected by an internal thermal shutdown protection mechanism and a short-circuit protection.
1 Input configuration The TDA8944J inputs can be driven symmetrical (floating) as well as asymmetrical. In the asymmetrical mode one input pin is connected via a capacitor to the signal ground which should be as close as possible to the SVR (electrolytic) capacitor ground. Note that the DC level of the input pins is half of the supply voltage VCC, so coupling capacitors for both pins are necessary. 2 Power amplifier The power amplifier is a Bridge Tied Load (BTL) amplifier with an all-NPN output stage, capable of delivering a peak output current of 2 A. The BTL principle offers the following advantages:
· Lower peak value of the supply current · The ripple frequency on the supply voltage is twice the signal frequency · No expensive DC-blocking capacitor · Good low frequency performance.
3 Mode selection The TDA8944J has three functional modes, which can be selected by applying the proper DC voltage to pin MODE. Standby - In this mode the current consumption is very low and the outputs are floating. The device is in
standby mode when (VCC - 0.5 V) < VMODE < VCC, or when the MODE pin is left floating (high impedance). The power consumption of the TDA8944J will be reduced to <0.18 mW. Mute - In this mode the amplifier is DC-biased but not operational (no audio output); the DC level of the input and output pins remain on half the supply voltage. This allows the input coupling and Supply Voltage Ripple Rejection (SVRR) capacitors to be charged to avoid pop-noise. The device is in mute mode when 3 V < VMODE < (VCC - 1.5 V). Operating - In this mode the amplifier is operating normally. The operating mode is activated at VMODE < 0.5 V.
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Internal Circuitry
No. Pin Symbol
Chassis M35&36 Service Manual
Equivalent Circuit
6 and 8 1 12 and 9
IN1+ and IN1-
IN2+ and IN2-
1 and 4 2 14 and 17
OUT1- and OUT1+
OUT2- and OUT2+
3
10
MODE
4
11
SVR
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Application Information
Chassis M35&36 Service Manual
Application diagram.
4. TDA8945
15 W mono Bridge Tied Load (BTL) audio amplifier
General description
The TDA8945S is a single-channel audio power amplifier with an output power of 15 W at an 8 load and an 18 V supply. The circuit contains a Bridge Tied Load (BTL) amplifier with an all-NPN output stage and standby/mute logic. The TDA8945S comes in a 9-lead single in-line (SIL) power package.
c
c
Features The same as TDA8944.
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Block Diagram and Pin Configuration
Chassis M35&36 Service Manual
Pin Description No. Symbol
1 2 3 4 5 6 7 8 9 OUT- VCC OUT+ IN+ IN- SVR MODE GND n.c.
Pin
1 2 3 4 5 6 7 8 9
Description
negative loudspeaker terminal supply voltage positive loudspeaker terminal positive input 5negative input 6half supply voltage decoupling (ripple rejection) mode selection input (standby, mute, operating) ground not connected
Functional Description
The TDA8945S is a mono BTL audio power amplifier capable of delivering 15 Woutput power to an 8 load at THD = 10%, using an 18 V power supply and an external heatsink. The voltage gain is fixed at 32 dB. With the three-level MODE input the device can be switched from `standby' to `mute' and to `operating' mode. The TDA8945S outputs are protected by an internal thermal shutdown protection mechanism and a short-circuit protection.
1 Input configuration The TDA8945S inputs can be driven symmetrical (floating) as well as asymmetrical. In the asymmetrical mode one input pin is connected via a capacitor to the signal ground which should be as close as possible to the SVR (electrolytic) capacitor ground. Note that the DC level of the input pins is half of the supply voltage VCC, so coupling capacitors for both pins are necessary. 2 Power amplifier The power amplifier is a Bridge Tied Load (BTL) amplifier with an all-NPN output stage, capable of delivering a peak output current of 2 A. The BTL principle offers the following advantages: Lower peak value of the supply current The ripple frequency on the supply voltage is twice the signal frequency
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No expensive DC-blocking capacitor Good low frequency performance.
Chassis M35&36 Service Manual
3 Mode selection The TDA8945S has three functional modes, which can be selected by applying the proper DC voltage to pin MODE. Standby- In this mode the current consumption is very low and the outputs are floating. The device is in
standby mode when (VCC - 0.5 V) < VMODE < VCC, or when the MODE pin is left floating (high impedance). The power consumption of the TDA8945S will be reduced to <0.18 mW. Mute- In this mode the amplifier is DC-biased but not operational (no audio output); the DC level of the input and output pins remain on half the supply voltage. This allows the input coupling and Supply Voltage Ripple Rejection (SVRR) capacitors to be charged to avoid pop-noise. The device is in mute mode when 3 V < VMODE < (VCC - 1.5 V). Operating- In this mode the amplifier is operating normally. The operating mode is activated at VMODE < 0.5 V.
Internal Circuitry
No. Pin Symbol Equivalent Circuit
1
4 and 5
IN+ and IN-
2
1 and 3
OUT- and OUT+
3
7
MODE
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No. Pin Symbol
Chassis M35&36 Service Manual
Equivalent Circuit
4
6
SVR
Application Information
Application diagram.
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6. TDA7057AQ Audio Output Amplifier
Chassis M35&36 Service Manual
GENERAL DESCRIPTION 1. The TDA7057AQ is a stereo BTL output amplifier with DC volume control. The device is designed for use in TVs and monitors.
2. Missing Current Limiter (MCL)
A MCL protection circuit is built-in. The MCL circuit is activated when the difference in current between the output terminal of each amplifier exceeds 100 mA (typical 300 mA). This level of 100 mA allows for single-ended headphone applications. FEATURES · DC volume control · Few external components · Mute mode · Thermal protection · Short-circuit proof · No switch-on and switch-off clicks · Good overall stability · Low power consumption · Low HF radiation · ESD protected on all pins.
FUNCTIONAL DESCRIPTION The TDA7057AQ is a stereo output amplifier with two DC volume control stages. The device is designed for TVs and monitors. In conventional DC volume control circuits the control or input stage is AC-coupled to the output stage via external capacitors to keep the offset voltage low. In the TDA7057AQ the two DC volume control stages are integrated into the input stages so that no coupling capacitors are required and a low offset voltage is still maintained. The minimum supply voltage also remains low. The BTL principle offers the following advantages: · Lower peak value of the supply current · The frequency of the ripple on the supply voltage is twice the signal frequency. Consequently, a reduced power supply with smaller capacitors can be used which results in cost reductions. For portable applications there is a trend to decrease the supply voltage, resulting in a reduction of output power at conventional output stages. Using the BTL principle increases the output power. The maximum gain of the amplifier is fixed at 40.5 dB. The DC volume control stages have a logarithmic control characteristic. Therefore, the total gain can be controlled from +40.5 dB to -33 dB. If the DC volume control voltage falls below 0.4 V, the device will switch to the mute mode. The amplifier is a short-circuit protected to ground, VP and across the load. A thermal protection circuit is also implemented. If the crystal temperature rises above +150 °C the gain will be reduced, thereby reducing the output power. Special attention is given to switch-on and switch-off clicks, low HF radiation and a good overall stability.
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BLOCK DIAGRAM
Chassis M35&36 Service Manual
PINNING
Pin configuration
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APPLICATION DIAGRAM
Chassis M35&36 Service Manual
Remark for "(1)"&"(2)": (1) This capacitor can be omitted if the 220 µF electrolytic capacitor is connected close to pin 5. (2) RL = 16 .
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6. M52760SP PLL-SPLIT VIF/SIF IC
General Description
Chassis M35&36 Service Manual
The M52760SP is IF signal-processing IC for VCRs and TVs. It enable the PLL detection system despite size as small as that of conventional quasi-synchronous VIF/SIF detector, IF/RF AGC, SIF limiter, FM detector and EQ AMP.
Features Video detection output is 2VP-P, It has built-in EQ AMP. The package is a 20-pin shrink-DIP, suitable for space saving. The video detector uses PLL for full synchronous detection circuit. It produces excellent characteristics of DG, DP, 920kHz beat, and cross color. Dynamic AGC realizes high speed response with only single filter. Video IF and sound IF signal processings are separated from each other. VCO output is used to obtain intercarrier. This PLL-SPLIT method provide good sound sensitivity and reduces buzz. As AFT output voltage uses the APC output voltage, VCO coil is not used. Audio FM demodulation uses PLL system, so it has wide frequency range with no external parts and no adjustment. QIF AMP has a fixed gain, and good characteristic for NICAM. Block Diagram
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7. MSP3415G
Introduction
Chassis M35&36 Service Manual
Multistandard Sound Processor
The MSP 3415G family of single-chip Multistandard Sound Processors covers the sound processing of all analog TV standards worldwide, as well as the NICAM digital sound standards. The full TV sound processing, starting with analog sound IF signal-in, down to processed analog AF-out, is performed in a single chip. These TV sound processing ICs include versions for processing the multichannel television sound (MTS) signal conforming to the standard recommended by the Broadcast Television Systems Committee (BTSC). The DBX noise reduction, or alternatively, Micronas Noise Reduction (MNR) is performed alignment free. Other processed standards are the Japanese FM-FM multiplex standard (EIA-J) and the FM-Stereo-Radio standard. Current ICs have to perform adjustment procedures in order to achieve good stereo separation for BTSC and EIA-J. The MSP 34x5G has optimum stereo performance without any adjustments. The MSP 3415G has built-in automatic functions: The IC is able to detect the actual sound standard automatically(Automatic Standard Detection). Furthermore, pilot levels and identification signals can be evaluated internally with subsequent switching between mono/stereo/bilingual; no I2C interaction is necessary (Automatic Sound Selection). The MSP 34x5G can handle very high FM deviations even in conjunction with NICAM processing. This is especially important for the introduction of NICAM in China.
Simplified functional block diagram
Features Standard Selection with single I2C transmission Automatic Standard Detection of terrestrial TV standards Automatic Sound Selection (mono/stereo/bilingual), new registers MODUS, STATUS Automatic Carrier Mute function Interrupt output programmable (indicating status change)
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AVC: Automatic Volume Correction Spatial effect for loudspeaker channel
Chassis M35&36 Service Manual
Loudspeaker channel with volume, balance, bass, treble, loudness
Two Stereo SCART (line) inputs, one Mono input; one Stereo SCART outputs Complete SCART in/out switching matrix Two I2S inputs; one I2S output All analog Mono sound carriers including AM-SECAM L All analog FM-Stereo A2 and satellite standards All NICAM standards Simultaneous demodulation of (very) high-deviation FM-Mono and NICAM Adaptive deemphasis for satellite (Wegener-Panda, acc. to ASTRA specification) ASTRA Digital Radio (ADR) together with DRP 3510A Korean FM-Stereo A2 standard
Application Fields As below table provides an overview of TV sound standards that can be processed by the MSP 3415G.
TV-System B/G L I Position of Carrier/MHz
5.5/5.7421875 5.5/5.85 6.5/5.85 6.0/6.552 6.5/6.2578125
Sound
Sound Modulation
FM-Stereo (A2) FM-Mono/NICAM AM-Mono/NICAM FM-Mono/NICAM FM-Stereo (A2, D/K1) FM-Stereo (A2, D/K2) FM-Stereo (A2, D/K3) FM-Mono/NICAM (D/K, NICAM) FM-Mono FM-Stereo ASTRA Digital Radio (ADR) with DRP 3510A FM-Stereo (A2)
Color System
PAL PAL SECAM-L PAL SECAM-East. PAL SECAM-East PAL
Broadcast e.g. in:
Germany Scandinavia, Spain France UK, Hong Kong Slovak. Rep currently no broadcast Poland China, Hungary Europe Sat. ASTRA Korea
D/K
6.5/6.7421875 6.5/5.7421875 6.5/5.85 6.5 7.02/7.2 7.38/7.56 etc. 4.5/4.724212
Satellite M/N
PAL
NTSC
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Chassis M35&36 Service Manual
Signal flow block diagram (input and output names correspond to pin names).
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Functional Description
1.1. Sound IF Processing 1.1.1. Analog Sound IF Input
Chassis M35&36 Service Manual
The input pins ANA_IN1+ and ANA_IN. offer the possibility to connect sound IF (SIF) sources to the MSP 34x5G. The analog-to-digital conversion of the sound IF signal is done by an A/D-converter. An analog automatic gain circuit (AGC) allows a wide range of input levels. The high-pass filter formed by the coupling capacitor at pin ANA_IN1+ is sufficient in most cases to suppress video components. Some combinations of SAW filters and sound IF mixer ICs, however, show large picture components on their outputs. In this case, further filtering is recommended. 1.2.2. Demodulator: Standards and Features The MSP 3415G is able to demodulate all TV sound standards worldwide including the digital NICAM system. Depending on the MSP 3415G version, the following demodulation modes can be performed: A2-Systems: Detection and demodulation of two separate FM carriers (FM1 and FM2), demodulation and evaluation of the identification signal of carrier FM2. NICAM-Systems: Demodulation and decoding of the NICAM carrier, detection and demodulation of the analog (FM or AM) carrier. For D/K-NICAM, the FM carrier may have a maximum deviation of 384 kHz. Very high deviation FM-Mono: Detection and robust demodulation of one FM carrier with a maximum deviation of 540 kHz. BTSC-Stereo: Detection and FM demodulation of the aural carrier resulting in the MTS/MPX signal. Detection and evaluation of the pilot carrier, AM demodulation of the (L-R)-carrier and detection of the SAP subcarrier. Processing of the DBX noise reduction or Micronas Noise Reduction (MNR). BTSC-Mono + SAP: Detection and FM demodulation of the aural carrier resulting in the MTS/MPX signal. Detection and evaluation of the pilot carrier, detection and FM demodulation of the SAP-subcarrier. Processing of the DBX noise reduction or Micronas Noise Reduction (MNR). Japan Stereo: Detection and FM demodulation of the aural carrier resulting in the MPX signal. Demodulation and evaluation of the identification signal and FM demodulation of the (L-R)-carrier. FM-Satellite Sound: Demodulation of one or two FM carriers. Processing of high-deviation mono or narrow bandwidth mono, stereo, or bilingual satellite sound according to the ASTRA specification. FM-Stereo-Radio: Detection and FM demodulation of the aural carrier resulting in the MPX signal. Detection and evaluation of the pilot carrier and AM demodulation of the (L-R)-carrier. The demodulator blocks of MSP 3415G versions have identical user interfaces. Even completely different systems like the BTSC and NICAM systems are controlled the same way. Standards are selected by means of MSP Standard Codes. Automatic processes handle standard detection and identification without controller interaction. The key features of the MSP 34x5G demodulator blocks are Standard Selection: The controlling of the demodulator is minimized: All parameters, such as tuning frequencies or filter bandwidth, are adjusted automatically by transmitting one single value to the STANDARD SELECT register. For all standards, specific MSP standard codes are defined. Automatic Standard Detection: If the TV sound standard is unknown, the MSP 34x5G can automatically detect the actual standard, switch to that standard, and respond the actual MSP standard code. Automatic Carrier Mute: To prevent noise effects or FM identification problems in the absence of an FM carrier, the MSP 34x5G offers a configurable carrier mute feature, which is activated automatically if the TV sound standard is selected by means of the STANDARD SELECT register. If no FM carrier is detected at one of the two MSP demodulator channels, the corresponding demodulator output is muted. This is indicated in the STATUS register. 1.2.3. Preprocessing of Demodulator Signals
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Chassis M35&36 Service Manual
The NICAM signals must be processed by a deemphasis filter and adjusted in level. The analog demodulated signals must be processed by a deemphasis filter, adjusted in level, and dematrixed. The correct deemphasis filters are already selected by setting the standard in the STANDARD SELECT register. The level adjustment has to be done by means of the FM/AM and NICAM prescale registers. The necessary dematrix function depends on the selected sound standard and the actual broadcasted sound mode (mono, stereo, or bilingual). It can be manually set by the FM Matrix Mode register or automatically by the Automatic Sound Selection. 1.2.4. Automatic Sound Select In the Automatic Sound Select mode, the dematrixfunction is automatically selected based on the identification information in the STATUS register. No I2C interaction is necessary when the broadcasted sound mode changes (e.g. from mono to stereo). The demodulator supports the identification check by switching between mono-compatible standards (standards that have the same FM-Mono carrier) automatically and non-audible. If B/G-FM or B/G-NICAM is selected, the MSP will switch between these standards. The same action is performed for the standards:D/K1-FM, D/K2-FM, D/K3-FM and D/K-NICAM. Switching is only done in the absence of any stereo or bilingual identification. If identification is found, the MSP keeps the detected standard. In case of high bit-error rates, the MSP 3415G automatically falls back from digital NICAM sound to analog FM or AM mono. "FM/AM" channel: Analog mono sound, stereo if available. In case of NICAM, analog mono only (FM or AM mono). "Stereo or A/B" channel: Analog or digital mono sound, stereo if available. In case of bilingual broadcast, it contains both languages A (left) and B(right). "Stereo or A" channel: Analog or digital mono sound, stereo if available. In case of bilingual broadcast, it contains language A (on left and right). "Stereo or B" channel: Analog or digital mono sound, stereo if available. In case of bilingual broadcast, it contains language B (on left and right). Note: The analog primary input channel contains the signal of the mono FM/AM carrier or the L+R signal of the MPX carrier. The secondary input channel contains the signal of the 2nd FM carrier, the L-R signal of the MPX carrier, or the SAP signal
Fig.: Source channel assignment of demodulated signals in Automatic Sound Select Mode
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1.2.5. Manual Mode
Chassis M35&36 Service Manual
Below Fig. shows the source channel assignment of demodulated signals in case of manual mode.
1.3. Preprocessing for SCART and I2S Input Signals The SCART and I2S inputs need only be adjusted in level by means of the SCART and I2S prescale registers. 1.4. Source Selection and Output Channel Matrix The Source Selector makes it possible to distribute all source signals (one of the demodulator source channels or SCART) to the desired output channels (loudspeaker, etc.). All input and output signals can be processed simultaneously. Each source channel is identified by a unique source address. For each output channel, the sound mode can be set to sound A, sound B, stereo, or mono by means of the output channel matrix. If Automatic Sound Select is on, the output channel matrix can stay fixed to stereo (transparent) for demodulated signals. 1.5. Audio Baseband Processing 1.5.1. Automatic Volume Correction (AVC) Different sound sources (e.g. terrestrial channels, SAT channels, or SCART) fairly often do not have the same volume level. Advertisements during movies usually have a higher volume level than the movie itself. This results in annoying volume changes. The AVC solves this problem by equalizing the volume level. To prevent clipping, the AVC's gain decreases quickly in dynamic boost conditions. To suppress oscillation effects, the gain increases rather slowly for low level inputs. The decay time is programmable by means of the AVC register . For input signals ranging from .24 dBr to 0 dBr, the AVC maintains a fixed output level of .18 dBr. Below Fig. shows the AVC output level versus its input level. For prescale and volume registers set to 0 dB, a level of 0 dBr corresponds to full scale input/output. This is SCART input/output 0 dBr = 2.0 Vrms Loudspeaker output 0 dBr = 1.4 Vrms 1.5.2. Loudspeaker Outputs The following baseband features are implemented in the loudspeaker output channels: bass/treble, loudness, balance, and volume. A square wave beeper can be added to the loudspeaker channel. 1.5.3. Quasi-Peak Detector is based on following filter time constants: attack time: 1.3 ms
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Simplified AVC characteristics
The quasi-peak readout register can be used to readout the quasi-peak level of any input source. The feature
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decay time: 37 ms 1.6. SCART Signal Routing 1.6.1. SCART DSP In and SCART Out Select
Chassis M35&36 Service Manual
The SCART DSP Input Select and SCART Output Select blocks include full matrix switching facilities. To design a TV set with two pairs of SCART-inputs and one pair of SCART-outputs, no external switching hardware is required. The switches are controlled by the ACB user register. 1.6.2. Stand-by Mode If the MSP 34x5G is switched off by first pulling STANDBYQ low and then (after >1s delay) switching off DVSUP and AVSUP, but keeping AHVSUP (`Stand-by'-mode), the SCART switches maintain their position and function. This allows the copying from selected SCART-inputs to SCART-outputs in the TV set's stand-by mode. In case of power on or starting from stand-by (switching on the DVSUP and AVSUP, RESETQ going high 2 ms later), all internal registers except the ACB register are reset to the default configuration .The reset position of the ACB register becomes active after the first I2C transmission into the Baseband Processing part. By transmitting the ACB register first, the reset state can be redefined. Pin Connections and Short Descriptions NC = not connected; leave vacant LV = if not used, leave vacant DVSS: if not used, connect to DVSS X = obligatory; connect as described in circuit diagram AHVSS: connect to AHVSS No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Pin Name
TP NC D_CTR_I/O_1 D_CTR_I/O_0 ADR_SEL STANDBYQ I2C_CL I2C_DA I2C_CL I2C_WS I2C_DA_OUT I2C_DA_IN1 ADR_DA ADR_WS ADR_CL DVSUP DVSS I2C_DA_IN2 NC RESETQ NC NC VREF2 DACM_R DACM_L NC NC NC
Pin No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Type
Connection (if not used)
LV LV LV LV X X X X LV LV LV LV LV LV LV X X LV LV X LV LV X LV LV LV LV LV
31
Short Description
Test pin Not connected D_CTR_I/O_1 D_CTR_I/O_0 I2C Bus address select Standby (low-active) I2C clock I2C data I2C clock I2C word strobe I2C data output I2C data input ADR data output ADR word strobe ADR clock Digital power supply +5V Digital ground I2C2-data input Not connected Power-on-reset Not connected Not connected Reference ground 2 high-voltage part Loudspeaker out, right Loudspeaker out, left Not connected Not connected Not connected
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IN/OUT IN/OUT IN IN IN/OUT IN/OUT
IN
OUT OUT
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No.
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
Chassis M35&36 Service Manual
Pin Name
VREF1 SC1_OUT_R SC1_OUT_L NC AHVSUP CAPL_M AHVSS AGNDC NC NC SC2_IN_L SC2_IN_R SC1_IN_L SC1_IN_R VREFTOP MONO_IN AVSS AVSUP ANA_IN1+ ANA_INNC TESTEN XTAL_IN XTAL_OUT
Pin No.
29 30 31 32 33 34 35 36 37 37 39 40 41 42 43 44 45 46 47 48 49 50 51 52
Type
Connection (if not used)
X LV LV LV X X X X LV LV LV LV LV LV X
Short Description
Reference ground 1 high-voltage part SCART 1 output, right SCART 1 output, left Not connected Analog power supply 8.0V Volume capacitor MAIN Analog ground Analog reference voltage high-voltage part Not connected Not connected SCART 2 input, left SCART 2 input, right SCART 1 input, left SCART 1 input, right Reference voltage IF A/D converter Mono input Analog ground Analog power supply +5V IF input 1 IF common Not connected Test pin Crystal oscillator Crystal oscillator
OUT OUT
IN IN IN IN
IN
LV X X
IN IN IN IN OUT
LV LV LV X X X
Pin Description
Pin 1, TP Test pin Pins 2, NC Pins not connected Pins 3, 4, D_CTR_I/O_1/0 Digital Control Input/ Output Pins (Fig. 9) General purpose input/output pins. Pin D_CTR_I/O_1 can be used as an interrupt request pin to the controller. Pin 5, ADR_SEL I C Bus Address Select (Fig. 6) By means of this pin, one of 3 device addresses for the MSP can be selected. The pin can be connected to ground (I C device addresses 80/81hex), to +5V supply (84/85hex) or left open (88/89hex). Pin 6, STANDBYQ Standby In normal operation, this pin must be high. If the MSP 3415G is switched off by first pulling STANDBYQ
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2 2
low and then (after >1s delay) switching off DVSUP and AVSUP, but keeping AHVSUP (`Standby'-mode), the SCART switches maintain their position and function. Pin 7, I2C_CL I2C Clock Input/Output (Fig. 8) Via this pin the I2C bus clock signal has to be supplied. The signal can be pulled down by the MSP in case of wait conditions. Pin 8, I2C_DA I2C Data Input/Output (Fig. 8) Via this pin the I2C bus data is written to or read from the MSP. Pin 9, I2S_CL I2S Clock Input/Output (Fig. 9) Clock line for the I2S bus. In master mode, this line is driven by the MSP; in slave mode, an external I2S clock has to be supplied. Pin 10, I2S_WS I2S Word Strobe Input/Output
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(Fig. 9) Word strobe line for the I S bus. In master mode, this line is driven by the MSP; in slave mode, an external I2S word strobe has to be supplied.
2
Chassis M35&36 Service Manual
clean ground and should be used as the reference for analog connections to the loudspeaker and headphone outputs. Pins 24, 25, DACM_R/L Loudspeaker Outputs
Pin 11, I2S_DA_OUT I S Data Output (Fig. 13) Output of digital serial sound data of the MSP on the I S bus. Pin 12, I2S_DA_IN1 I S Data Input 1 (Fig. 7) First input of digital serial sound data to the MSP via the I2S bus. Pin 13, ADR_DA ADR Bus Data Output (Fig. 13) Output of digital serial data to the DRP 3510A via the ADR bus. Pin 14, ADR_WS ADR Bus Word Strobe Output (Fig. 13) Word strobe output for the ADR bus.
2 2
2
(Fig. 11) Output of the loudspeaker signal. A 1nF capacitor to AHVSS must be connected to these pins. The DC offset on these pins depends on the selected loudspeaker volume. Pins 26, 27, 28, NC Pins not connected Pin 29, VREF1 Reference Ground 1 Reference analog ground. This pin must be connected separately to ground (AHVSS). VREF1 serves as a clean ground and should be used as the reference for analog connections to the SCART outputs. Pins 30, 31, SC1_OUT_R/L SCART1 Outputs
Pin 15, ADR_CL ADR Bus Clock Output (Fig. 13) Clock line for the ADR bus. Pins 16, DVSUP* Digital Supply Voltage Power supply for the digital circuitry of the MSP. Must be connected to a +5-V power supply. Pins 17, DVSS* Digital Ground Ground connection for the digital circuitry of the MSP Pin 18, I2S_DA_IN2 I S Data Input 2 (Fig. 7) Second input of digital serial sound data to the MSP via the I2S bus. Pins 19, NC Pins not connected Pin 20, RESETQ Reset Input (Fig. 1) In the steady state, high level is required. A low level resets the MSP 34x0G. Pins 21, 22 NC Pins not connected Pin 23, VREF2 Reference Ground 2 Reference analog ground. This pin must be connected separately to ground (AHVSS). VREF2 serves as a MSP (except IF input).
33
2
(Fig. 12) Output of the SCART1 signal. Connections to these pins must use a 100 ohm series resistor and are intended to be AC coupled. Pin 32, NC Pin not connected Pin 33, AHVSUP* Analog Power Supply High Voltage Power is supplied via this pin for the analog circuitry of the MSP (except IF input). This pin must be connected to the +8V supply. Pin 34, CAPLM Volume Capacitor Loudspeakers (Fig. 14) A 10F capacitor to AHVSUP must be connected to this pin. It serves as smoothing filter for loudspEaker volume changes in order to suppress audible plops. The value of the capacitor can be lowered to 1F if faster response is required. The area encircled by the trace lines should be minimized, keep traces as short as possible. This input is sensitive for magnetic induction. Pins 35, AHVSS* Ground for Analog Power Supply High Voltage Ground connection for the analog circuitry of the
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Pins 36, AGNDC Internal Analog Reference Voltage This pin serves as the internal ground connection for the analog circuitry (except IF input). It must be connected to the VREF pins with a 3.3 F and a 100 nF capacitor in parallel. This pins shows a DC level of typically 3.73 V.
Chassis M35&36 Service Manual
Pin 48, ANA_IN. IF Common (Fig. 5) This pin serves as a common reference for ANA_ IN1/2+ inputs. Pin 49, NC Pin not connected Pin 50, TESTEN Test Enable Pin (Fig. 2)
Pin 37, 38, NC Pins not connected. Pins 39, 40, SC2_IN_L/R SCART2 Inputs (Fig. 4) The analog input signal for SCART2 is fed to this pin. Analog input connection must be AC coupled. Pins 41, 42, SC1_IN_L/R SCART1 Inputs (Fig. 4) The analog input signal for SCART1 is fed to this pin. Analog input connection must be AC coupled. Pin 43, VREFTOP Reference Voltage IF AD Converter (Fig. 5) Via this pin, the reference voltage for the IF AD converter is decoupled. It must be connected to AVSS pins with a 10F and a 100nF capacitor in parallel. Traces must be kept short. Pin 44, MONO_IN Mono Input (Fig. 4) The analog mono input signal is fed to this pin. Analog input connection must be AC coupled. Pins 45, AVSS* Ground for Analog Power Supply Voltage Ground connection for the analog IF input circuitry of the MSP. Pins 46, AVSUP* Analog Power Supply Voltage Power is supplied via this pin for the analog IF input circuitry of the MSP. This pin must be connected to the +5 V supply. Pin 47, ANA_IN1+ IF Input 1 (Fig. 5) The analog sound if signal is supplied to this pin. Inputs must be AC coupled. This pin is designed as symmetrical input: ANA_IN1+ is internally connected to one input of a symmetrical op amp, ANA_IN. to the other.
This pin enables factory test modes. For normal operation it must be connected to ground. Pins51, 52, XTAL_IN XTAL_OUT Crystal Input and Output Pins (Fig. 10) These pins are connected to an 18.432 MHz crystal oscillator which is digitally tuned by integrated shunt capacitances. An external clock can be fed into XTAL_IN. The audio clock output signal AUD_ CL_OUT is derived form the oscillator. External capacitors at each crystal pin to ground (AVSS) are required. It should be verified by layout, that no supply current for the digital circuitry is flowing through the ground connection point. * Application Note: All ground pins should be connected to one lowResistive ground plane. All supply pins should be connected separately with short and low-resistive lines to the power supply. Decoupling capacitors from DVSUP to DVSS, AVSUP to AVSS, and AHVSUP to AHVSS are recommended as closely as possible to these pins. Decoupling of DVSUP and DVSS is most important. We recommend using more than one capacitor. By choosing different values, the frequency range of active decoupling can be extended. In our application boards we use: 220 pF, 470 pF, 1.5 nF, and 10 F. The capacitor with the lowest value should be placed nearest to the DVSUP and DVSS pins.
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Pin Circuits Pin No. Pin Name Type Fig. 1
Chassis M35&36 Service Manual
Pin Circuit
20
RESETQ
Input Pin
Fig. 2 50 TESTEN Input Pin
Fig. 3 44 MONO_IN Input Pin
Fig. 4 39 40 41 42 SC2_IN_L SC2_IN_R SC1_IN_L SC1_IN_R Input Pin
Fig. 5
43 47 48
VREFTOP ANA_IN1+ ANA_IN. Input Pin
Fig. 6
5
ADR_SEL
Input Pin
Fig. 7 12 18 6 I2S_DA_IN1 I2S_DA_IN2 STANDBYQ Input Pin
35
03.Mar.2003
TCL
Pin No. 7 8 Pin Name I2C_CL I2C_DA Type Fig. 8 Input/Output Pin
Chassis M35&36 Service Manual
Pin Circuit
Fig. 9 9 10 3 4 I2S_CL I2S_WS D_CTR_I/O_1 D_CTR_I/O_0 Input/Output Pin
Fig. 10
51 52
XTAL_IN XTAL_OUT
Input/Output Pin
Fig. 11
24 25
DACM_R Output Pin DACM_L
Fig. 12
30 31
SC1_OUT_R Output Pin SC1_OUT_L
Fig. 13 11 13 14 15 I2S_DA_OUT ADR_DA ADR_WS ADR_CL
Output Pin
36
03.Mar.2003
TCL
Pin No. Pin Name Type Fig. 14
Chassis M35&36 Service Manual
Pin Circuit
34
CAPL_M
Capacitor Pin
Fig. 15
36
AGNDC
Pin
Pin Configuration
37
03.Mar.2003
TCL
7. VCT3831A
Introduction
Chassis M35&36 Service Manual
Video/Controller/Teletext IC
The VCT 3831A is a high-quality singlechip TV processors. Modular design and a submicron technology allow the economic integration of features in all classes of TV sets. VCT 3831A contains the entire video, display and deflection processing for 4:3 and 16:9 50/60-Hz TV sets. The integrated microcontroller is supported by a powerful OSD generator with integrated teletext acquisition which can be upgraded with onchip page memory. With volume control and audio input select the basic audio features for mono TV sets are integrated. Features 1. Video Features four composite video inputs, two S-VHS inputs analog YCrCb input composite video monitor multistandard color decoder (1 crystal) multistandard sync decoder black-line detector adaptive 2H comb filter Y/C separator horizontal scaling (0.25 to 4) Panoramavision black-level expander dynamic peaking soft limiter (gamma correction) color transient improvement programmable RGB matrix analog RGB/Fastblank input half-contrast switch picture frame generator scan velocity modulation output high-performance H/V deflection angle and bow correction separate ADC for tube measurements EHT compensation 2. Microcontroller Features 8-bit, 10-MHz CPU (65C02) 96 kB program ROM on chip 1 kB program RAM on chip memory banking 16-input, 16-level interrupt controller patch modul for 10 ROM locations two 16-bit reloadable timers capture compare modul watchdog timer 14-bit PWM for voltage synthesis four 8-bit PWMs 10-bit ADC with 15:1 input MUX I2C bus master interface 24 programmable I/O ports 3. OSD Features 3 kB OSD RAM on chip WST level 1.5 compliant WST level 2 parallel attributes 32 foreground/background colors programmable color look-up table 1024 mask programmable characters 24 national languages (Latin, Cyrillic, Greek, Arabic, Farsi, Hebrew) character matrix 8x8,