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MP3 PLAYER
MP-200
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MP3 PLAYER
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CONTENTS 1. Exploded Views and Parts List 2. Electrical Parts List 3. Block Diagrams 4. PCB Diagrams 5. Wiring Diagram 6. Schematic Diagrams 7. IC Internal Diagram 8. Reference Information
SERVICE
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Manual
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© Samsung Electronics Co.,Ltd. SEP. 2000 Printed in Korea Code no. AH68-00036G
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ELECTRONICS
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1. Exploded View and Parts List
1-1 Total Exploded
15 3 A 11 12 A A A 21 13 20 25 18 17 16 14
23
24 10 9 1 A 5 4 A 6 A A
Samsung Electronics
8 7 B
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22 19
1-1
1-1-1 Parts List
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 A B Code No. AH64-00698A AH61-00416A AH64-00699A AH64-00700A AH64-00695A AH63-00159A AH64-00694A AH64-00691A AH64-00686A AH61-00415A AH64-00688A AH67-00072B AH64-00687A AH64-00696A AH64-00693A AH64-00690A AH64-00697A AH61-00440A AH61-00417A AH61-00418A AH61-00419A AH61-00420A AH69-00241A AH69-00242A AH64-00689A 6003-001162 6003-001152 Description Specification Remarks 1 1 1 1 1 1 1 1 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 16 2
1-2
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CABINET-TOP ; A1050 T0.8,SILVER FRAME-MIDDLE ; ABS D/GRAY,SPRAY SF CLEAR CABINET-BOTTOM ; ABS L/GRAY,SPRAY SILVER BADGE-MP3 ; ÀüÁÖ,11.9X7.35 DECO-TOP ; ABS NATURAL,Cr-P,'«±¤ COVER-EXTERNAL ; ABS L/GRAY,SPRAY SILVER DECO-LCD ; ABS NATURAL,Cr-P WINDOW-LCD ; ACRYL SMOKE BUTTON-FUNCTION ; ABS NATURAL,Cr-P HOLDER-FUNCTION ; ABS L/GRAY,SPRAY SILVER BUTTON-VOLUME ; ABS NATURAL,Cr-P CAP-ECP ; SILICON RUBBER,GREEN BUTTON-PRESET ; ABS NATURAL,Cr-P WINDOW-SMART ; ACRYL SMOKE DECO-BOTTOM ; ABS NATURAL,Cr-P KNOB-SMART ; ABS L/GRAY,SPRAY SILVER LID-BATTERY ; ABS L/GRAY,SPRAY SILVER SHAFT-CARRYING ; SUS303,1.0 XL11.8 SPRING-RECHARGER ; SUS304,0.5,Au-P SPRING-BATTERY(A) ; SUS304,0.5,Au-P SPRING-BATTERY(B) ; SUS304,0.5,Au-P SPRING-BATTERY(C) ; SUS304,0.5,Au-P CUSHION-LCD,A ; PORON T0.3,BLK CUSHION-LCD,B ; EVA T1.0,BLK KNOB-HOLD ; POM,D/GRAY SCREW TAP TITE ; 1.4X4 Cr-P SCREW TAP TITE ; 1.4X3 Ni-P
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Samsung Electronics
*S.N.A. : Service Not Available
2. Electrical Parts List
Location no. Code no. Description Specifiation Remarks Location no.
IC1 R19 R4 R21 R22 R23 R24 R53 R2 R1 R20 R10 R33 R39 R14 R15 R16 R25 R49 R50 R52 R7 R11 R17 R26 R8 R70 R12 R3 R6 R30 R31 R32 R36 R37 R38 R9 C0 C101 C102 C13 C14 C17 C20 C21 C22 C24 C25 C26 C3 C4 C5 C6 C100 C15 C16 C12 C9 C23 C2 C10 C11 C7 C8 TC1 TC14 TC2 TC3 TC4 TC8 TC10 TC13 TC9 L4 L5 L6 X1 B1-6 SW2 SW7 SW8 SW1 SW3 SW4 SW6 CN2 CN3
Code no.
Description Specifiation
MAS3507D-QG-F10,QFP,44P,5.5V 200OHM,5%,1/10W,DA,TP,2012 200OHM,5%,1/10W,DA,TP,2012 39ohm,5%,1/10W,DA,TP,2012 39ohm,5%,1/10W,DA,TP,2012 39ohm,5%,1/10W,DA,TP,2012 39ohm,5%,1/10W,DA,TP,2012 560ohm,5%,1/10W,DA,TP,2012 1.8Kohm,5%,1/10W,DA,TP,2012 100Kohm,5%,1/10W,DA,TP,2012 100Kohm,5%,1/10W,DA,TP,2012 12Kohm,5%,1/10W,DA,TP,2012 15Kohm,5%,1/10W,DA,TP,2012 15Kohm,5%,1/10W,DA,TP,2012 1Kohm,5%,1/10W,DA,TP,2012 1Kohm,5%,1/10W,DA,TP,2012 1Kohm,5%,1/10W,DA,TP,2012 1Kohm,5%,1/10W,DA,TP,2012 1Kohm,5%,1/10W,DA,TP,2012 1Kohm,5%,1/10W,DA,TP,2012 1Mohm,5%,1/10W,DA,TP,2012 2.2Kohm,5%,1/10W,DA,TP,2012 220Kohm,5%,1/10W,DA,TP,2012 22Kohm,5%,1/10W,DA,TP,2012 270Kohm,5%,1/10W,DA,TP,2012 4.7Kohm,5%,1/10W,DA,TP,2012 4.7Kohm,5%,1/10W,DA,TP,2012 470ohm,5%,1/10W,DA,TP,2012 47Kohm,5%,1/10W,DA,TP,2012 47Kohm,5%,1/10W,DA,TP,2012 680ohm,5%,1/10W,DA,TP,2012 7.5KOHM,5%,1/10W,DA,TP,2012 7.5KOHM,5%,1/10W,DA,TP,2012 7.5KOHM,5%,1/10W,DA,TP,2012 7.5KOHM,5%,1/10W,DA,TP,2012 7.5KOHM,5%,1/10W,DA,TP,2012 7.5KOHM,5%,1/10W,DA,TP,2012 7.5KOHM,5%,1/10W,DA,TP,2012 100nF,10%,50V,X7R,2012,-,TP 100nF,10%,50V,X7R,2012,-,TP 100nF,10%,50V,X7R,2012,-,TP 100nF,10%,50V,X7R,2012,-,TP 100nF,10%,50V,X7R,2012,-,TP 100nF,10%,50V,X7R,2012,-,TP 100nF,10%,50V,X7R,2012,-,TP 100nF,10%,50V,X7R,2012,-,TP 100nF,10%,50V,X7R,2012,-,TP 100nF,10%,50V,X7R,2012,-,TP 100nF,10%,50V,X7R,2012,-,TP 100nF,10%,50V,X7R,2012,-,TP 100nF,10%,50V,X7R,2012,-,TP 100nF,10%,50V,X7R,2012,-,TP 100nF,10%,50V,X7R,2012,-,TP 100nF,10%,50V,X7R,2012,-,TP 10nF,10%,50V,X7R,2012,-,TP 10pF,5%,50V,NPO,2012,-,TP 10pF,5%,50V,NPO,2012,-,TP 120pF,5%,50V,NPO,2012,-,TP 120pF,5%,50V,NPO,2012,-,TP 1uF,+80-20%,16V,Y5V,2012,-,TP 22nF,10%,50V,X7R,2012,-,TP 1.5nF,10%,50V,X7R,2012,-,TP 1.5nF,10%,50V,X7R,2012,-,TP 1.5nF,10%,50V,X7R,2012,-,TP 1.5nF,10%,50V,X7R,2012,-,TP 100UF,20%,6.3V,LZ,TP,4028 100UF,20%,6.3V,LZ,TP,4028 100UF,20%,6.3V,LZ,TP,4028 100UF,20%,6.3V,LZ,TP,4028 100UF,20%,6.3V,LZ,TP,4028 3.3UF,20%,16V,GP,TP,3216 47UF,10%,6.3V,GP,TP,3528 47UF,10%,6.3V,GP,TP,3528 47UF,10%,6.3V,GP,TP,3528 10uH,10%,2.5x3.2x2mm 47UH,20%,7*7*3.2MM 33UH,20%,MLF2012C330KT 14.72MHZ,CSACV14.72MXJ040-TC20 BLM21A121SP,AB 2.0*1.25*0.9MM 50MA,160GF,4*6*1.8MM 50MA,160GF,4*6*1.8MM 50MA,160GF,4*6*1.8MM SKQRAAE,G4162462M SKQRAAE,G4162462M SKQRAAE,G4162462M SKQRAAE,G4162462M 40P,2R,0.5MM,SMD-S-AUF -,WD-S3602V-1YNNA,MY-MP20,-
Remarks
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AH60-00022C AH59-00035H AH64-00718B 1109-001159 4302-001109 AH97-00427A
MP200 Parts List ****
ABS,MY-MP200 HS-S10BE,MY-MP250 MYMP200 ,PLASTIC,0TO*55C,50UA,CMOS,TR HR-4U,700MAH, MY-MP200
CLIP-JACK EARPHONE-ASSY CASE-SMC IC-MEMORY CARD BATTER-NIH(2ND) ASSY-MODEL GROUP
AH92-00589A ASSY-PCB-MAIN
SIC1 SIC5 SCN1 JACK-PHC SD1 SQ4 SIC2 SIC7 SIC7 SIC3 SIC4 SR11 SR17 SR21 SR7 SR34 SR1 SR32 SR5 SR8 SR10 SR12 SR14 SR15 SR19 SR20 SR22 SR31 SR9 SR6 SR18 SR16 SR23 SR24 SR25 SR26 SR27 SR28 SR29 SR30 SC10 SC13 SC14 SC15 SC17 SC18 SC19 SC7 SC8 SC9 SC11 SC12 SC6 SC7 SC16 SL8 X2 SB2 SB3 HOLD-S/W SCN2 SCN3 AH09-00050A AH13-00004A AH37-00014A AH37-00015A 0401-000008 0506-000119 0801-002345 0801-002432 0801-002516 1103-001176 1203-001369 2007-000282 2007-000290 2007-000300 2007-000300 2007-000409 2007-000468 2007-000468 2007-000477 2007-000477 2007-000565 2007-000565 2007-000565 2007-000565 2007-000565 2007-000565 2007-000565 2007-000565 2007-000565 2007-000586 2007-000766 2007-000781 2011-000475 2011-000475 2011-000475 2011-000475 2011-000475 2011-000475 2011-000475 2011-000475 2203-000206 2203-000206 2203-000206 2203-000206 2203-000206 2203-000206 2203-000206 2203-000206 2203-000206 2203-000206 2203-000295 2203-000295 2404-001134 2404-001134 2404-001158 2703-000125 2802-001115 3301-000353 3301-000353 3408-001038 3709-001139 3711-004522
MY-MP200
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IC MICOM-MP3 MSM66573-O11TB,MY-MP200,12MHZ IC ASIC NO,KSA-ECC48,QFP,48,JACK -,PCMCIA F S/F 18POS,-,18P,ECP JACK-PHONE -,-,-,-,MY-MP200 DIODE-SWITCHING DAN217,80V,100MA,SOT-23,TP TR-ARRAY FMS1,PNP,2,-50V,-40V,100MA,300 IC-CMOS LOGIC NC7S04-P5X,INVERTER SOP,5P,TP IC-CMOS LOGIC 74LVC244APW,BUFFER/DRIVER20P IC-CMOS LOGIC 74LVC245APW,BUFFERS TSSOP 20P IC-EPROM ,PLASTIC,-40TO+85C,10UA,CMOS,S IC-VOL,DETEVCTOR 61AN1902,SOT-23,3P,63MIL,PLAST R-CHIP 100Kohm,5%,1/10W,DA,TP,2012 R-CHIP 100ohm,5%,1/10W,DA,TP,2012 R-CHIP 10Kohm,5%,1/10W,DA,TP,2012 R-CHIP 10Kohm,5%,1/10W,DA,TP,2012 R-CHIP 15Kohm,5%,1/10W,DA,TP,2012 R-CHIP 1Kohm,5%,1/10W,DA,TP,2012 R-CHIP 1Kohm,5%,1/10W,DA,TP,2012 R-CHIP 1Mohm,5%,1/10W,DA,TP,2012 R-CHIP 1Mohm,5%,1/10W,DA,TP,2012 R-CHIP 220Kohm,5%,1/10W,DA,TP,2012 R-CHIP 220Kohm,5%,1/10W,DA,TP,2012 R-CHIP 220Kohm,5%,1/10W,DA,TP,2012 R-CHIP 220Kohm,5%,1/10W,DA,TP,2012 R-CHIP 220Kohm,5%,1/10W,DA,TP,2012 R-CHIP 220Kohm,5%,1/10W,DA,TP,2012 R-CHIP 220Kohm,5%,1/10W,DA,TP,2012 R-CHIP 220Kohm,5%,1/10W,DA,TP,2012 R-CHIP 220Kohm,5%,1/10W,DA,TP,2012 R-CHIP 22Kohm,5%,1/10W,DA,TP,2012 R-CHIP 330ohm,5%,1/10W,DA,TP,2012 R-CHIP 33 OHM 5%,1/10W,DA,TP,2012 R-NETWORK 33OHM,5%,63MW,L,CHIP,8P R-NETWORK 33OHM,5%,63MW,L,CHIP,8P R-NETWORK 33OHM,5%,63MW,L,CHIP,8P R-NETWORK 33OHM,5%,63MW,L,CHIP,8P R-NETWORK 33OHM,5%,63MW,L,CHIP,8P R-NETWORK 33OHM,5%,63MW,L,CHIP,8P R-NETWORK 33OHM,5%,63MW,L,CHIP,8P R-NETWORK 33OHM,5%,63MW,L,CHIP,8P C-CERAMIC,CHIP 100nF,10%,50V,X7R,2012,-,TP C-CERAMIC,CHIP 100nF,10%,50V,X7R,2012,-,TP C-CERAMIC,CHIP 100nF,10%,50V,X7R,2012,-,TP C-CERAMIC,CHIP 100nF,10%,50V,X7R,2012,-,TP C-CERAMIC,CHIP 100nF,10%,50V,X7R,2012,-,TP C-CERAMIC,CHIP 100nF,10%,50V,X7R,2012,-,TP C-CERAMIC,CHIP 100nF,10%,50V,X7R,2012,-,TP C-CERAMIC,CHIP 100nF,10%,50V,X7R,2012,-,TP C-CERAMIC,CHIP 100nF,10%,50V,X7R,2012,-,TP C-CERAMIC,CHIP 100nF,10%,50V,X7R,2012,-,TP C-CERAMIC,CHIP 10pF,5%,50V,NPO,2012,-,TP C-CERAMIC,CHIP 10pF,5%,50V,NPO,2012,-,TP C-TA,CHIP 100UF,20%,6.3V,LZ,TP,4028 C-TA,CHIP 100UF,20%,6.3V,LZ,TP,4028 C-TA,CHIP 47UF,10%,6.3V,GP,TP,3528 INDUCTIOR-SMD 10UH,10%,1.25*2.0*1.25MM RESONATOR-CERAMIC 12MHZ,0.5%,CSACV12.0MTJ-TC20 CORE FERRITE BEAD BLM21A121SP,AB 2.0*1.25*0.9MM CORE FERRITE BEAD BLM21A121SP,AB 2.0*1.25*0.9MM SWITCH-SLIDE 4V,300MA,SPST,ON-ON,1 CONNECTOR-CARD EDGE CN015R-3123-0(SMC) CONNECTOR-HEADER BOX,40P,2R,0.5MM,SMD-S,AUF
AH92-00590A ASSY-PCB-DISPLAY
DIODE-SCHOTTKY DIODE-SCHOTTKY DIODE-SCHOTTKY DIODE-SCHOTTKY TR-SMALL SIGNAL TR-SMALL SIGNAL TR-SMALL SIGNAL TR-SMALL SIGNAL TR-DIGITAL TR-DIGITAL FET-SILICON IC-D/A CONVERTER IC-DC/DC CONVERTER
MY-MP20
D1 D2 D3 D4 Q11 Q10 Q5 Q6 Q4 Q7 Q8 IC2 IC4
0404-001032 0404-001032 0404-001032 0404-001032 0501-000233 0501-000632 0501-000632 0501-000632 0504-000127 0504-000127 0505-001426 1002-001174 1203-001597
RB501-,NPN,200MW,10K/10K,SOT-2 RB501-,NPN,200MW,10K/10K,SOT-2 RB501-,NPN,200MW,10K/10K,SOT-2 RB501-,NPN,200MW,10K/10K,SOT-2 2SD1781K,NPN,200MW,SOT-23,TP-1 2SB1197K,PNP,200MW,SOT-23,TP,8 2SB1197K,PNP,200MW,SOT-23,TP,8 2SB1197K,PNP,200MW,SOT-23,TP,8 KSR1102,NPN 200MW 10KOHM SOT23 KSR1102,NPN 200MW 10KOHM SOT23 IRLML6401,P,-12V,-4.3A,0.05OHM DAC3550A-C2 ,PLASITC,5.25V, MAX1676EUB-T,SOP,10P,
1204-001554 2007-000026 2007-000026 2007-000028 2007-000028 2007-000028 2007-000028 2007-000030 2007-000267 2007-000282 2007-000282 2007-000355 2007-000409 2007-000409 2007-000468 2007-000468 2007-000468 2007-000468 2007-000468 2007-000468 2007-000477 2007-000493 2007-000565 2007-000586 2007-000635 2007-000872 2007-000872 2007-000931 2007-000941 2007-000941 2007-001118 2007-001141 2007-001141 2007-001141 2007-001141 2007-001141 2007-001141 2007-001141 2203-000206 2203-000206 2203-000206 2203-000206 2203-000206 2203-000206 2203-000206 2203-000206 2203-000206 2203-000206 2203-000206 2203-000206 2203-000206 2203-000206 2203-000206 2203-000206 2203-000260 2203-000295 2203-000295 2203-000316 2203-000316 2203-000477 2203-000609 2203-001551 2203-001551 2203-001551 2203-001551 2404-001134 2404-001134 2404-001134 2404-001134 2404-001134 2404-001136 2404-001158 2404-001158 2404-001158 2703-000001 2703-001020 2703-001802 2802-001108 3301-000353 3404-000141 3404-000141 3404-000141 3404-001121 3404-001121 3404-001121 3404-001121 3710-001601 AH07-00025A
IC-DECODER R-CHIP R-CHIP R-CHIP R-CHIP R-CHIP R-CHIP R-CHIP R-CHIP R-CHIP R-CHIP R-CHIP R-CHIP R-CHIP R-CHIP R-CHIP R-CHIP R-CHIP R-CHIP R-CHIP R-CHIP R-CHIP R-CHIP R-CHIP R-CHIP R-CHIP R-CHIP R-CHIP R-CHIP R-CHIP R-CHIP R-CHIP R-CHIP R-CHIP R-CHIP R-CHIP R-CHIP R-CHIP C-CERAMIC,CHIP C-CERAMIC,CHIP C-CERAMIC,CHIP C-CERAMIC,CHIP C-CERAMIC,CHIP C-CERAMIC,CHIP C-CERAMIC,CHIP C-CERAMIC,CHIP C-CERAMIC,CHIP C-CERAMIC,CHIP C-CERAMIC,CHIP C-CERAMIC,CHIP C-CERAMIC,CHIP C-CERAMIC,CHIP C-CERAMIC,CHIP C-CERAMIC,CHIP C-CERAMIC,CHIP C-CERAMIC,CHIP C-CERAMIC,CHIP C-CERAMIC,CHIP C-CERAMIC,CHIP C-CERAMIC,CHIP C-CERAMIC,CHIP C-CERAMIC,CHIP C-CERAMIC,CHIP C-CERAMIC,CHIP C-CERAMIC,CHIP C-TA,CHIP C-TA,CHIP C-TA,CHIP C-TA,CHIP C-TA,CHIP C-TA,CHIP C-TA,CHIP C-TA,CHIP C-TA,CHIP INDUCTOR-SMD INDUCTOR-SMD INDUCTOR-SMD RESONATOR-CERAMIC CORE FERRITE BEAD SWITCH-TACT SWITCH-TACT SWITCH-TACT SWITCH-TACT SWITCH-TACT SWITCH-TACT SWITCH-TACT CONNECTOR-SOCKET DISPLAY LCD
Samsung Electronics
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2-1
3. Block Diagram
3-1 Main
Samsung Electronics
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3-1
4. Printed Circuit Board Diagram
4-1 LCD
Top View Bottom View
4-2 SMC
Top View Bottom View
Samsung Electronics
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4-1
5. Wiring Diagram
Samsung Electronics
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5-1
6. Schematic Diagram
6-1 LCD
Samsung Electronics
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6-1
6-2 SMC
6-2
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Samsung Electronics
IC Internal Diagram
7. IC Internal Diagram
7-1 74LV245 ; SIC6
Philips Semiconductors Product specification
Octal bus transceiver (3-State)
74LV245
FEATURES
· Wide operating voltage: 1.0 to 5.5 V · Optimized for low voltage applications: 1.0 to 3.6 V · Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V · Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, · Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, · Output capability: bus driver · ICC category: MSI
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr = tf 2.5 ns SYMBOL tPHL/tPLH CI CI/O CPD PARAMETER Propagation delay An to Bn; Bn to An Input capacitance Input/output capacitance Power dissipation capacitance per buffer Tamb = 25°C Tamb = 25°C
DESCRIPTION
The 74LV245 is an octal transceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directions. The 74LV245 features an output enable (OE) input for easy cascading and a send/receive (DIR) input for direction control. OE controls the outputs so that the buses are effectively isolated.
CONDITIONS CL = 15 pF; VCC = 3.3 V
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TYPICAL 7.0 3.5 10 VCC = 3.3 V VI = GND to VCC, note 1 40 UNIT ns pF pF pF
NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in µW) VCC2 fi ) (CL VCC2 fo) where: PD = CPD fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; VCC2 fo) = sum of the outputs. (CL
ORDERING INFORMATION
20-Pin Plastic DIL 20-Pin Plastic SO 20-Pin Plastic SSOP Type II 20-Pin Plastic TSSOP Type I
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40°C to +125°C 40°C to +125°C 40°C to +125°C 40°C to +125°C FUNCTION Direction Data inputs/outputs Ground (0 V) Data inputs/outputs
PACKAGES
TEMPERATURE RANGE
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OUTSIDE NORTH AMERICA 74LV245 N 74LV245 D 74LV245 DB 74LV245 PW NORTH AMERICA 74LV245 N 74LV245 D 74LV245 DB 74LV245PW DH PKG. DWG. # SOT146-1 SOT163-1 SOT339-1 SOT360-1
PIN DESCRIPTION
PIN NUMBER 1 2, 3, 4, 5, 6, 7, 8, 9 10 18, 17, 16, 15, 14, 13, 12, 11 19 20 DIR
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SYMBOL
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FUNCTION TABLE
INPUTS OE L L DIR L H X H NOTES: H = HIGH voltage level L = LOW voltage level X = don't care Z = high impedance OFF-state
A0 to A7 GND B0 to B7 OE VCC
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Output enable input (active LOW) Positive supply voltage
1998 Apr 20
2
Samsung Electronics
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INPUTS/OUTPUT An A=B Inputs Z Bn Inputs B=A Z 8531931 19258
The 74LV245 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT245.
7-1
IC Internal Diagram
Philips Semiconductors
Product specification
Octal bus transceiver (3-State)
74LV245
PIN CONFIGURATION
DIR A0 A1 A2 A3 A4 A5 A6 A7 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC OE B0 B1 B2 B3
LOGIC SYMBOL
1 DIR OE A0 19
3
A1
4 B4 B5 B6 B7 6 5
A2 B2 A3 16
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A4 A5 A6 A7
SV00624
7
LOGIC SYMBOL (IEEE/IEC)
19 1 G3 3EN1 3EN2
8
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9 18 2 17 16 15 14 13
1 2
3 4 5 6 7 8 9
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SV00626
1998 Apr 20
7-2
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B0 18 B1 17 B3 15 B4 14 B5 13 B6 12 B7 11
2
SV00625
Samsung Electronics
IC Internal Diagram
7-2 74LV244 ; SIC7
Philips Semiconductors
Product specification
Octal buffer/line driver (3-State)
74LV244
FEATURES
· Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, · Output capability: bus driver · ICC category: MSI
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr = tf 2.5 ns SYMBOL tPHL/tPLH CI CPD PARAMETER Propagation delay 1An to 1Yn; 2An to 2Yn Input capacitance Power dissipation capacitance per buffer Tamb = 25°C
Tamb = 25°C
CONDITIONS
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TYPICAL 8.0 3.5 35 UNIT ns pF pF VCC = 3.3 V VI = GND to VCC1 TEMPERATURE RANGE
ORDERING INFORMATION
PACKAGES 20-Pin Plastic DIL 20-Pin Plastic SO 20-Pin Plastic SSOP Type II 20-Pin Plastic TSSOP Type I OUTSIDE NORTH AMERICA 74LV244 N 74LV244 D 74LV244 DB 74LV244 PW NORTH AMERICA 74LV244 N 74LV244 D 74LV244 DB 74LV244PW DH PKG. DWG. # SOT146-1 SOT163-1 SOT339-1 SOT360-1
PIN CONFIGURATION
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40°C to +125°C 40°C to +125°C 40°C to +125°C
20 VCC 2OE 1Y0 2A0 1Y1 2A1 1Y2 2A2 1Y3 2A3 19 18 17 16 15 14 13 12 11
40°C to +125°C
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LOGIC SYMBOL
2 1A0 17 2A0 4 1A1 15 2A1 6 1A2 13 2A2 8 1A3 11 2A3 1 1OE 19 2OE 1Y0 18 2Y0 3 1Y1 16 2Y1 5 1Y2 14 2Y2 7 1Y3 12 2Y3 9
NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in µW) VCC2 fi ) (CL VCC2 fo) where: PD = CPD fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; VCC2 fo) = sum of the outputs. (CL
1OE 1A0 2Y0 1A1 2Y1
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2
3 4 5 6 7 8 9 10
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1A2 2Y2 1A3 2Y3
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CL = 15 pF; VCC = 3.3 V
GND
SV00620
1998 May 20
2
Samsung Electronics
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SV00621
· Wide operating voltage: 1.0 to 5.5 V · Optimized for low voltage applications: 1.0 to 3.6 V · Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V · Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V,
DESCRIPTION
The 74LV244 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT244. The 74LV244 is an octal non-inverting buffer/line driver with 3-State outputs. The 3-State outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH on nOE causes the outputs to assume a high impedance OFF-state. The 74LV244 is identical to the 74LV240 but has non-inverting outputs.
8531924 19420
7-3
IC Internal Diagram
Philips Semiconductors
Product specification
Octal buffer/line driver (3-State)
74LV244
PIN DESCRIPTION
PIN NUMBER 1 2, 4, 6, 8 3, 5, 7, 9 10 17, 15, 13, 11 18, 16, 14, 12 19 20 SYMBOL 1OE 1A0 to 1A3 2Y0 to 2Y3 GND 2A0 to 2A3 1Y0 to 1Y3 2OE VCC FUNCTION Output enable input (active LOW) Data inputs Bus outputs
FUNCTIONAL DIAGRAM
2 4 6 8 1A0 1A1 1A2 1A3 1OE 2A0 2A1 2A2 2A3 2OE 2Y0 2Y1 2Y2 2Y3 3 5 7 9 1Y0 1Y1 1Y2 1Y3 18 16 14 12
Ground (0 V) Data inputs Bus outputs Output enable input (active LOW) Positive supply voltage
1 17 15 13 11 19
LOGIC SYMBOL (IEEE/IEC)
1 EN 18 16 14 12
t
FUNCTION TABLE
nOE INPUTS nAn L H X
2 4 6 8
o
SV00622
19
EN
a
3
L L H
11 13 15 17
9 7 5 3
SV00666
NOTES: H = HIGH voltage level L = LOW voltage level X = don't care Z = high impedance OFF-state
7-4
d
1998 May 20
u
p
Samsung Electronics
r
OUTPUT nYn L H Z
IC Internal Diagram
7-3 DAC3550A ; IC2
DAC 3550A
Stereo Audio DAC 1. Introduction The DAC 3550A is a single-chip, high-precision, dual digital-to-analog converter designed for audio applications. The employed conversion technique is based on oversampling with noise-shaping. With MICRONAS INTERMETALL's unique multibit sigma-delta technique, less sensitivity to clock jitter, high linearity, and a superior S/N ratio has been achieved. The DAC 3550A is controlled via I2C bus. Digital audio input data is received by a versatile I2S interface. The analog back-end consists of internal analog filters and op amps for cost-effective additional external sound processing. The DAC 3550A provides line-out, headphone/speaker amplifiers, and volume control. Moreover, mixing additional analog audio sources to the D/A-converted signal is supported. The DAC 3550A is designed for all kinds of applications in the audio and multimedia field, such as: MPEG players, CD players, DVD players, CD-ROM players, etc. The DAC 3550A ideally complements the MPEG 1/2 layer 2/3 audio decoder MAS 3507D. No crystal required for standard applications with sample rates from 32 to 48 kHz. Crystal required only for automatic sample rate detection below 32 kHz, MPEG mode (refer to Section 2.10), and use of clock output CLKOUT. 1.1. Main Features no master main input clock required integrated stereo headphone amplifier and mono speaker amplifier SNR of 103 dBA I2C bus, I2S bus internal clock oscillator
full-feature mode by I2C control (three selectable subaddresses) reduced feature mode for non-I2C applications
analog deemphasis for 44.1 kHz
analog volume and balance: +18... 75 dB and mute oversampling and multibit noise-shaping technique THD better than 0.01 %
a
DAC MAS 3507D
I2S
p
t
low-power mode Input Select and Mixing
DAC 3550A
line out 14.725 MHz
two additional analog stereo inputs (AUX) with source selection and mixing supply range: 2.7 V...5.5 V
additional line-out on-chip op amps for cost-effective external analog sound processing
Analog Inputs
WSI CLI DRI I S
2
o
continuous sample rates from 8 kHz to 50 kHz
Interpolation Filter
Volume and Headphone Amplifier
Fig. 11: Block diagram of the DAC 3550A
d
Host (PC, Controller)
ROM, CD-ROM, RAM, Flash Mem. ..
u
demand signal MPEG clock MPEG bit stream
CLKOUT
Fig. 12: Typical application: MPEG Layer 3 Player
MICRONAS INTERMETALL
r
OUTL OUTR 3
Samsung Electronics
7-5
IC Internal Diagram
DAC 3550A
CLI 23
DAI 24
WSI 25 18 Vdd Vss
I2S
Digital Supply
17
Analog Supply PLL Variable S & H
o
CLKOUT 14
3rd-order Noise Shaper & Multibit DAC Osc.
I2C
XTO
13
t
Analog Low-pass Filter
XTI
12
Control
a
Input Select Switch Matrix
AUX2L
29
AUX1L
31
p u
5
DEEML FOPL FOUTL FINL
34 38 37 39
Postfilter Op Amps Deemphasis Op Amps Line-Out
Analog Volume
d
Headphone Amplifier
7 OUTR
OUTL
Fig. 13: Block diagram of the DAC 3550A
4
MICRONAS INTERMETALL
7-6
r
3 2 AVSS0 AVSS1 VREF AGNDC 44 1 16 15 SDA SCL 27 26 21 19 20 TESTEN PORQ DEECTRL MCS1 MCS2 32 AUX1R 30 AUX2R 35 42 41 43 DEEMR FOPR FOUTR FINR
Sample Rate Detection
9
AVDD0 AVDD1
Interpolation Filter
10
Samsung Electronics
IC Internal Diagram
DAC 3550A
2. Functional Description 2.1. I2S Interface The I2S interface is the digital audio interface between the DAC 3550A and external digital audio sources such as CD/DAT players, MPEG decoders etc. It covers most of the I2S-compatible formats. All modes have two common features: 1. The MSB is left justified to an I2S frame identification (WSI) transition. 2. Data is valid on the rising edge of the bit clock CLI. 16-bit mode In this case, the bit clock is 32 × fsaudio. Maximum word length is 16 bit. 32-bit mode In this case, the bit clock is 64 × fsaudio. Maximum word length is 32 bit. Automatic Detection No I2C control is required to switch between 16- and 32-bit mode. It is recommended to switch the DAC 3550A into mute position during changing between 16- and 32-bit mode. For high-quality audio, it is recommended to use the 32-bit mode of the I2S interface to make use of the full dynamic range (if more than 16 bits are available). Left-Right Selection Standard I2S format defines an audio frame always starting with left channel and low-state of WSI. However, I2C control allows changing the polarity of WSI. Delay Bit Standard I2S format requires a delay of one clock cycle between transitions of WSI and data MSB. In order to fit other formats, however, this characteristic can be switched off and on by I2C control.
Vh
CLI
Vl
DAI
15 14 13 12 11 10 9 8
Vl
7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8
a
Vh
t
7 6 5 4 3 2 1 0 programmable delay bit
WSI
Vh Vl
left 16-bit audio sample
right 16-bit audio sample
Fig. 21: I2S 16-bit mode (LR_SEL=0)
Vh
CLI
Vl
Vh
u
DAI
31 30 29 28 27 26 25 24
Vl
d
programmable delay bit
WSI
Vh Vl
p
7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 7 6 5 4 3 2 1 0
left 32-bit audio sample
Fig. 22: I2S 32-bit mode (LR_SEL=0)
Note: Volume mute should be applied before changing I2S mode in order to avoid audible clicks.
MICRONAS INTERMETALL
o
right 32-bit audio sample
r
5
Samsung Electronics
7-7
IC Internal Diagram
DAC 3550A
2.2. Interpolation Filter The interpolation filter increases the sampling rate by a factor of 8. The characteristic for fsaudio = 48 kHz is shown in Fig. 23. 2.6. Input Select and Mixing Matrix This block is used to switch between or mix the auxiliary inputs and the signals coming from the DAC. A switch matrix allows to select between mono and stereo mode as shown in Fig. 24.
dB 0 -0.02 -0.04 -0.06 -0.08 -0.1 -0.12 -0.14 0 5000 10000 15000 20000 f/Hz
24.576 MHz
AUX1L AUX1R AUX2L AUX2R
-
Fig. 23: 18 Interpolation filter; frequency range: 0...22 kHz
Fig. 24: Switch matrix 2.3. Variable Sample & Hold The advantage of this system is that even at low sample frequencies the out-of-band noise is not scaled down to audible frequencies.
Mono mode is realized by adding left and right channel.
2.4. 3rd-order Noise Shaper and Multibit DAC
2.5. Analog Low-pass
d
6
u
The analog low-pass is a first order filter with a cut-off frequency of approximately 1.4 MHz which removes the high-frequency components of the noise-shaping signal.
p
The 3rd-order noise shaper converts the oversampled audio signal into a 5-bit noise-shaping signal at a high sampling rate. This technique results in extremely low quantization noise in the audio band.
a
2.7. Postfilter Op Amps, Deemphasis Op Amps, and Line-Out This block contains the active components for the analog postfilters and the deemphasis network. The op amps and all I/O-pins for this block are shown in Fig. 25.
t
7-8
o
AUX_MS INSEL_AUX2 INSEL_AUX1 INSEL_DAC
MICRONAS INTERMETALL
r
FOUTR
DAD DAI WSI
FOUTL D/A
Samsung Electronics
IC Internal Diagram
DAC 3550A
optional line-out
AVSS
AGNDC +
3.3 µF/100 nF
For external components, see section "Applications"
AVOL_R
+ OUTL
150 µF 1.5 k Speaker 32
VREF
FOUTL
from switch matrix
FINL FINR
FOUTR DEEMR
FOPR
47
-
150 µF 1.5 k
Fig. 25: Postfilter op amps, deemphasis op amps, and line-out
2.8. Analog Volume The analog volume control covers a range from +18 dB to -75 dB. The lowest step is the mute position. Step size is split into a 3-dB and a 1.5-dB range:
t
Table 21: Volume Control Volume/dB 18.0 16.5 15.0 13.5 AVOL 111000 110111 110110 110101
-75 dB...-54 dB: 3 dB step size -54 dB...+18 dB: 1.5 dB step size
p
a
- - -
AVOL_L
IRPA
For external components, see section "Applications"
2.9. Headphone Amplifier
The headphone amplifier output is provided at the OUTL and OUTR pins connected either to stereo headphones or a mono loudspeaker. The stereo headphones require external 47- serial resistors in both channels. If a loudspeaker is connected to these outputs, the power amplifier for the right channel must be switched to inverse polarity. In order to optimize the available power, the source of the two output amplifiers should be identical, i.e. a monaural signal.
0.0
-1.5
u
-54.0 -57.0
d
Please note, that if a speaker is connected, it should strictly be connected as shown in Fig. 25. Never use a separate connector for the speaker, because electrostatic discharge could damage the output transistors.
-75
Mute
MICRONAS INTERMETALL
o
OUTR
+
to µC (HP-switch)
r
16-32 Headphones
DEEML
FOPL
47
AVDD
-
101100 (default) 101011
-
001000 000111
-
000001 000000
7
Samsung Electronics
7-9
IC Internal Diagram
DAC 3550A
2.10. Clock System The advantage of the DAC 3550A clock system is that no external master clock is needed. Most DACs need 256 × fsaudio, 384 × fsaudio, or at least an asynchronous clock. All internal clocks are generated by a PLL circuit, which locks to the I2S bit clock (CLI). If no I2S clock is present, the PLL runs free, and it is guaranteed that there is always a clock to keep the IC controllable by I2C. The device can be set to two different modes: Standard mode MPEG mode In the standard mode, I2C subaddressing is possible (ADR0, ADR1, ADR2). MPEG mode always uses ADR3. To select the modes, the MCS1/MCS2 pins must be set according to Table 22. Table 22: Operation Modes
MCS1 MCS2 Mode Subaddress ADR0 ADR1 ADR2 Default Sample Rate
2.10.1. Standard Mode without I2C In standard mode, sample rates from 48 kHz to 32 kHz are handled without I2C control automatically. The setting for this range is the default setting. with I2C Sample rates below 32 kHz require an I2C control to set the PLL divider. This ensures that even at low sample rates, the DAC 3550A runs at a high clock rate. This avoids audible effects due to the noiseshaping technique of the DAC 3550A. Sample rate range is continuous from 8 to 50 kHz. The I2C setting of low sample rates must follow according to Section 3.5. "Control Registers" on page 15. An additional mode allows automatic sample rate detection. In this case, the clock oscillator is required and must run at frequencies between 13.3 MHz to 17 MHz. This mode, however, does not support continuous sample rates. Only the following sample rates are allowed:
The sample rate detection allows a tolerance of ±200 ppm at WSI. If the oscillator is not used for automatic sample rate detection, it can be used as a general-purpose clock for the application. The frequency range in this case is 10 MHz to 25 MHz.
0 0 1 1
0 1 0 1
Standard Standard Standard MPEG
3248 kHz
3248 kHz 3248 kHz Automatic
ADR3
u
p
d
8
a
2.10.2. MPEG Mode This mode should be used in conjunction with MAS 3507D in MPEG player applications. In this case a 14.725 MHz signal is needed to provide a clock for the MAS 3507D and to allow an automatic sample rate detection in the DAC 3550A. All MPEG sample rates from 8 to 48 kHz can be detected. The internal processing and the DAC itself are automatically adjusted to keep constant performance throughout the entire range. I2C control for sample rate adjustment is not needed in this case. Register SR_REG[0:2] is locked to SRC_A; see Section 3.5. "Control Registers" on page 15. The MPEG sample rates: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz As in standard mode, the sample rate detection allows a tolerance of ±200 ppm at WSI. Subaddressing is not possible in MPEG mode; this means, in multi-DAC systems, only one DAC 3550A can run in MPEG mode.
t
8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz
7-10
o
MICRONAS INTERMETALL
r
Samsung Electronics
IC Internal Diagram
7-4 MAS3507D ; IC1
PRELIMINARY DATA SHEET
MAS 3507D
1.1. Features Serial asynchronous MPEG bit stream input (SDI) Parallel (PIO-DMA) Input Broadcast and multimedia operation mode Automatic locking to given data rate in broadcast mode
MPEG 1/2 Layer 2/3 Audio Decoder Release Note: Revision bars indicate significant changes to the previous edition. This data sheet applies to MAS 3507D version G10 and following versions.
1. Introduction The MAS 3507D is a single-chip MPEG layer 2/3 audio decoder for use in audio broadcast or memory-based playback applications. Due to embedded memories, the embedded DC/DC up-converter, and the very low power consumption, the MAS 3507D is ideally suited for portable electronics. In MPEG 1 (ISO 11172-3), three hierarchical layers of compression have been standardized. The most sophisticated and complex, layer 3, allows compression rates of approximately 12:1 for mono and stereo signals while still maintaining CD audio quality. Layer 2 (widely used in DVB, ADR, and DAB) achieves a compression of 8:1 providing CD quality. In order to achieve better audio quality at low bit rates (<64 kbit/s per audio channel), three additional sampling frequencies are provided by MPEG 2 (ISO 13818-3). The MAS 3507D decodes both layer 2 and layer 3 bit streams as defined in MPEG 1 and 2. The multichannel/multilingual capabilities defined by MPEG 2 are not supported by the MAS 3507D. An extension to the MPEG 2 layer 3 standard developed by FhG Erlangen, Germany sometimes referenced as MPEG 2.5, for extremely low bit rates at sampling frequencies of 12, 11.025, or 8 kHz is also supported by the MAS 3507D.
Data request triggered by 'demand signal' in multimedia mode Output audio data delivered (in various formats) via an I2S bus (SDO) Digital volume / stereo channel mixer / Bass / Treble Output sampling clocks are generated and controlled internally. Ancillary data provided via I2C interface Status information accessible via PIO pins or I2C
u
CLKI CLKO
p
RISC DSP Core Serial In MPEG frame sync
MAS 3507D
DC/DC Converter /3/
Clock Synthesizer
decoded output
d
/3/
Serial Out I2S
a
PIO I2C CRC error
MPEG 1/2 audio bit stream /2/
Fig. 11: MAS 3507D block diagram
Micronas
t
/8+5/ serial control /2/
"CRC Error" and "MPEG Frame Synchronization" Indicators at Pins in serial input mode
Power management for reduced power consumption at lower sampling frequencies Low power dissipation (30 mW @ fs 12 kHz, 46 mW @ fs 24 kHz, 86 mW @ fs > 24 kHz @ 2.7 V) Supply voltage range: 1.0 V to 3.6 V due to built-in DC/DC converter (1-cell/2-cell battery operation) Adjustable power supply supervision Power-off function Additional functionality achievable via download software (CELP voice Decoder, ADPCM encoder / decoder)
o
r
5
Samsung Electronics
7-11
IC Internal Diagram
MAS 3507D
1.2. Application Overview The MAS 3507D can be applied in two major environments: in multimedia mode or in broadcast mode. For both modes, the DAC 3550A fits perfectly to the requirements of the MAS 3507D. It is a high-quality multi sample rate DAC (8 kHz ... 50 kHz) with internal crystal oscillator, which is only needed for generating the decoder clock, and integrated stereo headphone amplifier plus 2 stereo inputs.
PRELIMINARY DATA SHEET
A delayed response of the host to the demand signal (by several milliseconds) or an interrupted response of the host will be tolerated by the MAS 3507D as long as the input buffer does not run empty. A PC might use its DMA capabilities to transfer the data in the background to the MAS 3507D without interfering with its foreground processes. The source of the bit stream may be a memory (e.g. ROM, Flash) or PC peripherals, such as CD-ROM drive, an ISDN card, a hard disk or a floppy disk drive.
1.2.1. Multimedia Mode 1.2.2. Broadcast Mode In a memory-based multimedia environment, the easiest way to incorporate a MAS 3507D decoder is to use its data-demand pin. This pin can be used directly to request input bit stream data from the host or memory system. While the demand pin is active, the data stream shall be transmitted to the MAS 3507D. The bit stream clock should be higher than the actual data rate of the MPEG bit stream (1 MHz bit stream clock works with all MPEG bit rates). The demand signal will be active until the input buffer of the MAS 3507D is filled.
In environments where the bit stream is delivered from an independent transmitter to one or more receivers, the MAS 3507D cannot act as master for the bit stream clock. In this mode, it synchronizes itself to the incoming bit stream data rate by a digital PLL and generates a synchronized digital audio sample clock for the required output sample rates.
I2C demand signal demand clock MPEG bit stream
a
I2S
Host (PC, Controller)
MAS 3507D
p
CLKI
ROM, CD-ROM, RAM, Flash Mem. ..
Fig. 12: Block diagram of a MAS 3507D, decoding a stored bit stream in multimedia mode
u
control I2C L3 bit stream (fixed rate) I2S
d
Receiver
Front-end
MAS 3507D
DAC 3550A
clock
CLKI
Fig. 13: Block diagram of a MAS 3507D in a broadcast environment
6
t
14.725 MHz line out
DAC 3550A
CLKOUT
14.725 MHz line out
CLKOUT
o
7-12
r
Micronas
Samsung Electronics
IC Internal Diagram
PRELIMINARY DATA SHEET
MAS 3507D
2.2. Firmware (Internal Program ROM) A valid MPEG 1/2/2.5 layer 2/3 data signal is taken as input. The signal lines are a clock line SIC and the data line SID. The MPEG decoder performs the audio decoding. The steps for decoding are synchronization, side information extraction,
2. Functional Description of the MAS 3507D 2.1. DSP Core The hardware of the MAS 3507D consists of a high performance RISC Digital Signal Processor (DSP) and appropriate interfaces (see Fig. 21). The internal processor works with a memory word length of 20 bits and an extended range of 32 bits in its accumulators. The instruction set of the DSP is highly optimized for audio data compression and decompression. Thus, only very small areas of internal RAM and ROM are required. All data input and output actions are based on a `non cycle stealing' background DMA that does not cause any computational overhead.
ancillary data extraction, and volume and tone control.
MPEG Bit Stream
Sync
a
Digital Audio Output
t
Ancillary Data
Volume Tone Control
MPEG Decoder
Decoder Status
p
Config. Reg.
u
PIO
Status
Start-up Config.
d
Fig. 21: Block diagram of the MPEG Decoder in serial input mode
Micronas
o
to µC
For the supported bit rates and sample rates, see Table 312 on page 32. Frame synchronization and CRC-error signals are provided at the output pins of the MAS 3507D in serial input mode.
r
7
audio data decoding,
Samsung Electronics
7-13
IC Internal Diagram
PIN CONFIGURATIONS
4.2.2. Pin Configurations
VSS VDD I2CD I2CC POR TE DCEN EOD RTR RTW DCSG PI4 SIC SII XVSS SID
XVDD PI8 SOC SOI SOD PI12
AVSS CLKI AVDD WRDY WSEN PUP CLKO PI0 PI1 PI2 PI3
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PI4 SIC SII SID XVSS XVDD PI8 SOI SOC
39 38 37 36 35
DCSO VSENS PR PCS PI19 PI18 PI17 PI16 PI15 PI14 PI13
PI3 PI2 PI1 PI0 CLKO PUP WSEN WRDY AVDD CLKI AVSS
34 35 36 37 38
33 32 31 30 29
40 41 42 43 44 1
o
2 3 4 5 6 7 8 9 10 11 I2CC I2CD VDD RTR EOD DCEN VSS
MAS 3507D
34
39
MAS 3507D
t
TE POR
PI12 SOD
Fig. 44: 44-pin PLCC package
7-14
d
u
p
a
Fig. 45: 44-pin PMQFP package
r
22 21 20 19 18 17 16 15 14 13 12 PI13 PI14 PI15 PI16 PI17 PI18 PI19 PCS PR VSENS DCSO DCSG RTW
6
5
4
3
2
1
44 43 42 41 40
33 32 31 30 29 28 27 26 25 24 23
Samsung Electronics
IC Internal Diagram
7-5 MAX1676 ; IC4
19-1360; Rev 0; 7/98
KIT ATION EVALU LE VAILAB A
High-Efficiency, Low-Supply-Current, Compact, Step-Up DC-DC Converters
General Description ____________________________Features
o 94% Efficient at 200mA Output Current o Internal Synchronous Rectifier (no external diode) o 0.1µA Logic-Controlled Shutdown o LBI/LBO Low-Battery Detector o Selectable Current Limit for Reduced Ripple o 8-Pin and 10-Pin µMAX Packages
MAX1674/MAX1675/MAX1676
_______________Ordering Information
PART TEMP. RANGE PIN-PACKAGE 8 µMAX 8 µMAX 10 µMAX MAX1674EUA MAX1675EUA MAX1676EUB -40°C to +85°C -40°C to +85°C -40°C to +85°C
________________________Applications
Pagers Wireless Phones Medical Devices Hand-Held Computers PDAs RF Tags 1 to 3-Cell Hand-Held Devices
a
Pin Configurations
TOP VIEW
FB 1 LBI 2 LBO 3 REF 4 8 OUT
INPUT 0.7V TO V OUT
p
LX LBO GND
Typical Operating Circuit
MAX1674 MAX1675
7 LX 6 GND 5 SHDN
ON
OFF
u
SHDN
MAX1674OUT MAX1675
OUTPUT 3.3V, 5V, OR ADJ (2V TO 5.5V) UP TO 300mA
t
FB 1 LBI 2 LBO 3 CLSEL 4 REF 5
All three devices have a 0.3 N-channel MOSFET power switch. The MAX1674 has a 1A current limit. The MAX1675 has a 0.5A current limit, which permits the use of a smaller inductor. The MAX1676 comes in a 10-pin µMAX package and features an adjustable current limit and circuitry to reduce inductor ringing.
o Preassembled Evaluation Kit (MAX1676EVKIT)
d
LOW-BATTERY DETECT IN
LBI REF FB
LOW-BATTERY DETECT OUT
0.1F µ
________________________________________________________________ Maxim Integrated Products
o
µMAX
9 LX
The MAX1674/MAX1675/MAX1676 compact, high-efficiency, step-up DC-DC converters fit in small µMAX packages. They feature a built-in synchronous rectifier, which improves efficiency and reduces size and cost by eliminating the need for an external Schottky diode. Quiescent supply current is only 16µA. The input voltage ranges from 0.7V to VOUT, where VOUT can be set from 2V to 5.5V. Start-up is guaranteed from 1.1V inputs. The MAX1674/MAX1675/ MAX1676 have a preset, pin-selectable output for 5V or 3.3V. The outputs can also be adjusted to other voltages using two external resistors.
o Low-Noise, Anti-Ringing Feature (MAX1676)
MAX1676
µMAX 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 408-737-7600 ext. 3468.
Samsung Electronics
r
10 OUT 8 GND 7 BATT 6 SHDN
o 16µA Quiescent Supply Current
7-15
IC Internal Diagram
High-Efficiency, Low-Supply-Current, Compact, Step-Up DC-DC Converters MAX1674/MAX1675/MAX1676
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (OUT to GND) ..............................-0.3V to +6.0V Switch Voltage (LX to GND) .....................-0.3V to (VOUT + 0.3V) Battery Voltage (BATT to GND).............................-0.3V to +6.0V SHDN, LBO to GND ..............................................-0.3V to +6.0V LBI, REF, FB, CLSEL to GND ...................-0.3V to (VOUT + 0.3V) Switch Current (LX) ...............................................-1.5A to +1.5A Output Current (OUT) ...........................................-1.5A to +1.5A Continuous Power Dissipation (TA = +70°C) 8-Pin µMAX (derate 4.1mW/°C above +70°C) .............330mW 10-Pin µMAX (derate 5.6mW/°C above +70°C) ...........444mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +165°C Lead Temperature (soldering, 10sec) .............................+300°C
ELECTRICAL CHARACTERISTICS
PARAMETER Minimum Input Voltage Operating Voltage Start-Up Voltage Start-Up Voltage Tempco Output Voltage Output Voltage Range VOUT FB = OUT FB = GND VIN TA = +25°C SYMBOL CONDITIONS
(VBATT = 2V, FB = OUT (VOUT = 3.3V), RL = , TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) MIN 1.1 0.9 -2 3.17 4.80 2 300 150 180 90 1.274 420 220 mA FB = GND (VOUT = 5V) IREF = 0 MAX1674, MAX1676 (CLSEL = OUT) MAX1675, MAX1676 (CLSEL = GND) 285 130 1.30 0.024 IREF = 0 to 100µA VOUT = 2V to 5.5V 1.274 ILX = 100mA MAX1674, MAX1676 (CLSEL = OUT) MAX1675, MAX1676 (CLSEL = GND) VLX = 0, 5.5V; VOUT = 5.5V 0.80 0.4 3 0.08 1.30 0.3 1 0.5 0.05 15 2.5 1.326 0.6 1.20 0.65 1 1.326 V mV/°C mV mV/V V A µA MAX1674, MAX1676 (CLSEL = OUT) 3.30 5 3.43 5.20 5.5 TYP 0.7 5.5 1.1 MAX UNITS V V V mV/°C V V
TA = +25°C, RL = 3k (Note 1)
FB = OUT (VOUT = 3.3V) Steady-State Output Current (Note 2) IOUT
Reference Voltage Reference Voltage Tempco Reference Voltage Load Regulation Reference Voltage Line Regulation
FB, LBI Input Threshold Internal NFET, PFET On-Resistance
d
LX Switch Current Limit (NFET)
LX Leakage Current
2
_______________________________________________________________________________________
7-16
u
p
VREF TEMPCO VREF_LOAD VREF_LINE RDS(ON) ILIM ILEAK
a
MAX1675, MAX1676 (CLSEL = GND)
t
o
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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Samsung Electronics
IC Internal Diagram
High-Efficiency, Low-Supply-Current, Compact, Step-Up DC-DC Converters
ELECTRICAL CHARACTERISTICS (continued)
(VBATT = 2V, FB = OUT (VOUT = 3.3V), RL = , TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
MAX1674/MAX1675/MAX1676
Operating Current into OUT (Note 3) Shutdown Current into OUT Efficiency LX Switch On-Time LX Switch Off-Time FB Input Current LBI Input Current CLSEL Input Current SHDN Input Current LBO Low Output Voltage LBO Off Leakage Current Damping Switch Resistance SHDN Input Voltage CLSEL Input Voltage VIL VIH VIL VIH I LBO tON tOFF IFB ILBI ICLSEL I SHDN
VFB = 1.4V, VOUT = 3.3V SHDN = GND VOUT = 3.3V, ILOAD = 200mA VOUT = 2V, ILOAD = 1mA VFB = 1V, VOUT = 3.3V VFB = 1V, VOUT = 3.3V VFB = 1.4V VLBI = 1.4V MAX1676, CLSEL = OUT V SHDN = 0 or VOUT VLBI = 0, ISINK = 1mA MAX1676, VBATT = 2V 3 0.8
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1 0.03 1 1.4 0.07 0.2 0.07 88
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0.8VOUT 0.8VOUT MIN 3.13 4.75 2.20 1.2675 1.2675 2.7 0.75 0.75 0.36
V LBO = 5.5V, VLBI = 5.5V
Note 1: Start-up voltage operation is guaranteed with the addition of a Schottky MBR0520 external diode between the input and output. Note 2: Steady-state output current indicates that the device maintains output voltage regulation under load. See Figures 5 and 6. Note 3: Device is bootstrapped (power to the IC comes from OUT). This correlates directly with the actual battery supply.
ELECTRICAL CHARACTERISTICS
(VBATT = 2V, FB = OUT, RL = , TA = -40°C to +85°C, unless otherwise noted.) (Note 4) PARAMETER Output Voltage Output Voltage Range Reference Voltage FB, LBI Thresholds Internal NFET, PFET On-Resistance VREF IREF = 0 SYMBOL VOUT CONDITIONS MAX 3.47 5.25 5.5 1.3325 1.3325 0.6 VFB = 1.4V, VOUT = 3.3V SHDN = GND tON tOFF ILIM VFB = 1V, VOUT = 3.3V VFB = 1V, VOUT = 3.3V MAX1674, MAX1676 (CLSEL = OUT) MAX1675, MAX1676 (CLSEL = GND) 40 1 7.0 1.25 1.25 0.69 UNITS V V V V µA µA µs µs A FB = OUT
Operating Current into OUT (Note 3) Shutdown Current into OUT
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LX Switch On-Time LX Switch Off-Time LX Switch Current Limit (NFET)
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FB = GND
RDS(ON)
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PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
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IC Internal Diagram
7-6 MSM66573 ; SIC1
PEDL66573-02
1 Semiconductor MSM66573 Family
16-Bit Microcontroller
This version: Aug. 1999 Previous version: Jun.1999
Preliminary
GENERAL DESCRIPTION
The MSM66573 family of highly functional CMOS 16-bit single chip microcontrollers utilize the nX-8/500S, Oki's proprietary CPU core. A wide variety of internal multi-functioned timers provide timer functions such as compare out, capture, event counter, auto reload, and PWM, and can be used for periodic and timed measurements. In addition to the main clock and clock gear functions, there is a sub clock (32.768 kHz) that is suitable for low power applications. A three channel serial interface and a high-speed bus interface that has separate address and data buses and does not require external address latches are provided as interfaces to external devices. With a 16-bit CPU core that enables high-speed 16-bit arithmetic computations and a variety of bit processing functions, this general-purpose microcontroller is optimally suited for Digital Audio devices such as a Mini-Disc and an MP3 player. The flash ROM version (MSM66Q573L) programmable with a single 2.4 V (minimum) power supply and flash ROM version (MSM66Q573) programmable with a single 5 V power supply are also included in the family. These versions are easily adaptable to sudden specification changes and to new product versions.
Digital Audio Control Systems PC peripheral Control Systems Office Electronics Control Systems
ORDERING INFORMATION
Order Code or Product Name MSM66573L-TB MSM66573-TB MSM66Q573L-TB MSM66Q573-TB MSM66P573-TB
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Package 100-pin plastic TQFP (TQFP 100-P-1414-0.50-K) Remark Low voltage version (2.4 to 3.6 V) 5V mask ROM version (4.5 to 5.5 V) MSM66573L flash ROM version MSM66573 flash ROM version MSM66573 OTP ROM version (2.7 to 5.5 V)
APPLICATIONS
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IC Internal Diagram
PEDL66573-02
1 Semiconductor
MSM66573 Family
FEATURES
Name Operating temperature Power supply voltage/ maximum frequency Minimum instruction execution time Internal ROM size (max. external) Internal RAM size (max. external) I/Oports MSM66573L 30°C to +70°C VDD=2.4 to 3.6 V/f=14 MHz MSM66573 VDD=4.5 to 5.5 V/f=30 MHz
A/D converter External interrupt Interrrupt priority Others OTP ROM version Flash ROM version
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Serial port
UART × 1ch Synchronous × 1ch UART/ Synchronous × 1ch
10-bit A/D converter, 8-ch multiplexer × 1ch Non-maskable × 1ch Maskable × 6ch 3 levels Separate address and data busses Bus release function Dual clocks MSM66P573 (Max. f = 24 MHz) MSM66Q573L MSM66Q573
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Timers
143 ns at 14 MHz (2.4 to 3.6 V) 67ns at 30 MHz (4.5 to 5.5 V) 61µs at 32.768 kHz (2.4 to 3.6/4.5 to 5.5 V) 64 KB (1 MB) 4 KB (1 MB) 75 I/O pins (with programmable pull-up resistors) 8 input-only pins 16-bit free running timer × 1ch Compare out/capture input × 2ch 16-bit timer (auto reload/timer out) × 1ch 8-bit auto reload timer × 1ch 8-bit auto reload timer × 3ch (also fumctions as serial communication baud rate generator) Watchdog timer (also functions as 8-bit auto reload timer) Watch timer (real-time counter) × 1ch 8-bit PWM × 4ch (can also be used as 16-bit PWM × 2ch)
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IC Internal Diagram
PEDL66573-02
1 Semiconductor
MSM66573 Family
SPECIAL FEATURES
1. High-performance CPU The family includes the high-performance CPU, powerful bit manipulation instruction set, full symmetrical addressing mode, and ROM WINDOW function, and also provides the best optimized C compiler support. 2. A variety of power saving modes Attaching a 32.768-kHz crystal produces a real-time clock signal from the internal clock timer. Use of a single clock in place of dual clocks is possible. Switching the CPU clock to this clock signal, 1/2 × main clock, or 1/4 × main clock, then produces operation in a low power consumption mode. The clock gear function allows a 1/2 × or 1/4 × main clock to be selected for the CPU operating clock. The family provides a wide range of standby control functions. In addition to the usual STOP mode that stops the oscillator, there are the quick restart STOP mode that shuts down the CPU and peripherals but leaves the oscillator running, and the HALT mode that shuts down the CPU but leaves the peripherals running. 3. MSM66Q573L and MSM66Q573 with flash memory programmable with single power supply In addition to the regular mask ROM version, the family includes these versions with 64KB of flash memory that can be programmed using a single power supply. For the MSM66Q573L, an internal booster circuit derives the necessary program voltage from the device's low (2.4 V min) power supply, and the program voltage for the MSM66Q573 is provided with a single 5 V power supply. 4. Multifunction, high-precision analog-to-digital converter The family includes a high-precision 10-bit analog-to-digital converter with eight channels and is ideal for such analog control functions as processing audio signals, processing sensor inputs, detecting key switch states, and controlling battery use in portable equipment. Each channel has its own result register readily accessible from the software. In addition to single-channel conversions, there is also a scan function offering automatic conversion from the user's choice of starting channel through to the last channel. 5. Multifunction PWM The family supports both 8- and 16-bit PWM operation. Choosing between the time-base counter output or overflow from an 8-bit auto-reload timer as the PWM counter clock source provides a wide number of possibilities over a broad frequency range. The 16-bit PWM configuration supports a high-speed synchronization mode that generates a high-precision output signal with less ripple suitable for digital-to-analog control applications. 6. Programmable pull-up resistors Building the pull-up resistors into the chip contributes to overall design compactness. Making them programmable on a per-bit basis allows complete flexibility in circuit board layout and system design. These programmable pull-up resistors are available for all I/O pins not already assigned specific functions (such as the oscillator connection pins). 7. High-speed bus interface The interface to external devices uses separate data and address buses. This arrangement permits rapid bus access for controlling the system from the microcontroller. 8. Wide support for external interrupts There are a total of seven interrupt channels for use in communicating with external devices: six for maskable interrupts and one for non-maskable interrupts.
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IC Internal Diagram
PEDL66573-02
1 Semiconductor
MSM66573 Family
BLOCK DIAGRAM
TM0OUT TM0EVT CLKOUT XTOUT RXD0 TXD0 RXC0 TM3OUT TM3EVT RXD1 TXD1 RXC1 TXC1 TM4OUT SIOI3 SIOO3 SIOCK3 TM5EVT 16 bit Timer0 CPU Core Peripheral SIO0 (UART) XT0 XT1 OSC0 OSC1 HOLD HLDACK RES
System Control ALU Control Registers 8 bit Timer3/BRG
ALU Control ACC
LRB
SIO1 (UART/SYNC)
8 bit Time4/BRG
SIO3 (SYNC)
Memory Control Pointing Registers Local Registers
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RAM 4K TBC RTC
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8 bit Timer5/BRG
ROM 64K Bus Port Control
8 bit Timer6/WDT PWMOUT0 PWMOUT2 PWMOUT1 PWMOUT3 TM9OUT TM9EVT CPCM0 CPCM1
8 bit PWM0 8 bit PWM1
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8 bit Timer9
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CAP/CMP
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VREF AGND AI0 to AI7
10 bit A/D Converter
NMI EXINT0 to EXINT5
Interrupt
Port Control
16 bit FRC
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PC
DSR TSR CSR
SSP
PSW
Instruction Decoder
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IC Internal Diagram PEDL66573-02
1 Semiconductor
MSM66573 Family
PIN CONFIGURATION (TOP VIEW)
P10-3 SIOO3/P10-2 SIOI3/P10-1 SIOCK3/P10-0 TM3EVT/P7-5 TM3OUT/P7-4 RXC0/P7-2 GND TXD0/P7-1 RXD0/P7-0 AGND AI7/P12-7 AI6/P12-6 AI5/P12-5 AI4/P12-4 AI3/P12-3 AI2/P12-2 AI1/P12-1 AI0/P12-0 VREF VDD A19/P2-3 A18/P2-2 A17/P2-1 A16/P2-0 95 90 85
P10-4 P10-5 TM5EVT/P10-7 RXD1/P8-0 TXD1/P8-1 RXC1/P8-2 TXC1/P8-3 TM4OUT/P8-4 PWM2OUT/P8-6 PWM3OUT/P8-7 PWM0OUT/P7-6 PWM1OUT/P7-7 VDD GND HLDACK/P9-7 EXINT4/P9-0 EXINT5/P9-1 P9-2 P9-3 EXINT0/P6-0 EXINT1/P6-1 EXINT2/P6-2 EXINT3/P6-3 P6-4 P6-5
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P6-6 P6-7 P5-4/CPCM0 P5-5/CPCM1 P5-6/TM0OUT P5-7/TM0EVT RES NMI EA VDD XT0 XT1 GND OSC0 OSC1 VDD P11-0/WAIT P11-1/HOLD P11-2/CLKOUT P11-3/XTOUT P11-6/TM9OUT P11-7/TM9EVT P3-1/PSEN P3-2/RD P3-3/WR
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100-pin Plastic TQFP
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75 P1-7/A15 P1-6/A14 P1-5/A13 P1-4/A12 P1-3/A11 P1-2/A10 P1-1/A9 P1-0/A8 P4-7/A7 P4-6/A6 P4-5/A5 P4-4/A4 P4-3/A3 P4-2/A2 P4-1/A1 P4-0/A0 GND P0-7/D7 P0-6/D6 P0-5/D5 P0-4/D4 P0-3/D3 P0-2/D2 P0-1/D1 P0-0/D0
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8. Referenc Information
MPEG Audio Layer-3 History Quality Details
History
In 1987, the IIS started to work on perceptual audio coding in the framework of the EUREKA project EU147, Digital Audio Broadcasting (DAB). In a joint cooperation with the University of Erlangen (Prof. Dieter Seitzer), the IIS finally devised a very powerful algorithm that is standardized as ISO-MPEG Audio Layer-3 (IS 11172-3 and IS 13818-3). Without data reduction, digital audio signals typically consist of 16 bit samples recorded at a sampling rate more than twice the actual audio bandwidth (e.g. 44.1 kHz for Compact Disks). So you end up with more than 1.400 Mbit to represent just one second of stereo music in CD quality. By using MPEG audio coding, you may shrink down the original sound data from a CD by a factor of 12, without losing sound quality. Factors of 24 and even more still maintain a sound quality that is significantly better than what you get by just reducing the sampling rate and the resolution of your samples. Basically, this is realized by perceptual coding techniques addressing the perception of sound waves by the human ear. Using MPEG audio, one may achieve a typical data reduction of
still maintaining the original CD sound quality. By exploiting stereo effects and by limiting the audio bandwidth, the coding schemes may achieve an acceptable sound quality at even lower bitrates. MPEG Layer-3 is the most powerful member of the MPEG audio coding family. For a given sound quality level, it requires the lowest bitrate - or for a given bitrate, it achieves the highest sound quality. Sound Quality Some typical performance data of MPEG Layer-3 are:
In all international listening tests, MPEG Layer-3 impressively proved its superior performance, maintaining the original sound quality at a data reduction of 1:12 (around 64 kbit/s per audio channel). If applications may tolerate a limited bandwidth of around 10 kHz, a reasonable sound quality for stereo signals can be achieved even at a reduction of 1:24. For the use of low bit-rate audio coding schemes in broadcast applications at bitrates of 60 kbit/s per audio channel, the ITU-R recommends MPEG Layer-3. (ITU-R doc. BS.1115)
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telephone sound 2.5 kHz mono better than shortwave 4.5 kHz mono better than AM radio 7.5 kHz mono similar to FM radio 11 kHz stereo near-CD 15 kHz stereo CD >15 kHz stereo *) Fraunhofer uses a non-ISO extension of MPEG Layer-3 for enhanced
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by Layer 1 (corresponds with 384 kbps for a stereo signal), by Layer 2 (corresponds with 256..192 kbps for a stereo signal), by Layer 3 (corresponds with 128..112 kbps for a stereo signal),
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8 kbps * 96:1 16 kbps 48:1 32 kbps 24:1 56...64 kbps 26...24:1 96 kbps 16:1 112..128kbps 14..12:1 performance ("MPEG 2.5")
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reduction ratio
Reference Information
Details
Filter bank The filter bank used in MPEG Layer-3 is a hybrid filter bank which consists of a polyphase filter bank and a Modified Discrete Cosine Transform (MDCT). This hybrid form was chosen for reasons of compatibility to its predecessors, Layer-1 und Layer-2. Perceptual Model The perceptual model is mainly determining the quality of a given encoder implementation. It uses either a seperate filter bank or combines the calculation of energy values (for the masking calculations) and the main filter bank. The output of the perceptual model consists of values for the masking threshold or the allowed noise for each coder partition. If the quantization noise can be kept below the masking threshold, then the compression results should be indistinguishable from the original signal. Joint Stereo Joint stereo coding takes advatage of the fact that both channels of a stereo channel pair contain far the same information. These stereophonic irrelevancies and redundancies are exploited to reduce the total bitrate. Joint stereo is used in cases where only low bitrates are available but stereo signals are desired. Quantization and Coding A system of two nested iteration loops is the common solution for quantization and coding in a Layer-3 encoder. Quantization is done via a power-law quantizer. In this way, larger values are automatically coded with less accuracy and some noise shaping is already built into the quantization process. The quantized values are coded by Huffman coding. As a specific method for entropy coding, hufman coding is lossless. Thus is called noiseless coding because no noise is added to the audio signal. The process to find the optimum gain and scalefactors for a given block, bit-rate and output from the perceptual model is usually done by two nested iteration loops in an analysis-by-synthesis way:
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Reference Information
Inner iteration loop (rate loop)
The Huffman code tables assign shorter code words to (more frequent) smaller quantized values. If the number of bits resulting from the coding operation exceeds the number of bits available to code a given block of data, this can be corrected by adjusting the global gain to result in a larger quantization step size, leading to smaller quantized values. This operation is repeated with different quantization step sizes until the resulting bit demand for Huffman coding is small enough. The loop is called rate loop because it modifies the overall coder rate until it is small enough.
Outer iteration loop (noise control/distortion loop)
To shape the quantization noise according to the masking threshold, scalefactors are applied to each scalefactor band. The systems starts with a default factor of 1.0 for each band. If the quantization noise in a given band is found to exceed the masking threshold (allowed noise) as supplied by the perceptual model, the scalefactor for this band is adjusted to reduce the quantization noise. Since achieving a smaller quantization noise requires a larger number of quantization steps and thus a higher bitrate, the rate adjustment loop has to be repeated every time new scalefactors are used. In other words, the rate loop is nested within the noise control loop. The outer (noise control) loop is executed until the actual noise (computed from the difference of the original spectral values minus the quantized spectral values) is below the masking threshold for every scalefactor band (i.e. critical band).
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