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INTEGRATED CIRCUITS

DATA SHEET
For a complete data sheet, please also download:
· The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC · The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC

HEF4557B LSI 1-to-64 bit variable length shift register
Product specification File under Integrated Circuits, IC04 January 1995

Philips Semiconductors

Product specification

1-to-64 bit variable length shift register
DESCRIPTION The HEF4557B is a static clocked serial shift register whose length may be programmed to be any number of bits between 1 and 64. The number of bits selected is equal to the sum of the subscripts of the enabled length control inputs (L1, L2, L4, L8, L16 and L32) plus one. Serial data may be selected from the DA or DB data inputs with the A/B select input. This feature is useful for recirculation

HEF4557B LSI

purposes. Information on DA or DB is shifted into the first register position and all the data in the register is shifted one position to the right on the LOW to HIGH transition of CP0 while CP1 is LOW or on the HIGH to LOW transition of CP1 while CP0 is HIGH. A HIGH on master reset (MR) resets the register and forces O to LOW and O to HIGH, independent of the other inputs.

Fig.1 Functional diagram.

PINNING DA, DB A/B CP0 CP1 MR L1 to L32 O, O data inputs select data input clock input clock enable input asynchronous master reset bit-length control inputs buffered outputs HEF4557BT(D): HEF4557BD(F): HEF4557BP(N): 16-lead DIL; plastic (SOT38-1) 16-lead DIL; ceramic (cerdip) (SOT74) 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America FAMILY DATA, IDD LIMITS category LSI See Family Specifications

Fig.2 Pinning diagram.

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1-to-64 bit variable length shift register HEF4557B LSI

Product specification

Philips Semiconductors

Product specification

1-to-64 bit variable length shift register
FUNCTION TABLE INPUTS MR L L L L H A/B L H L H X DA D1 D1 D1 D1 X DB D2 D2 D2 D2 X H H X X CPO CP1 L L OUTPUT O (1) D2 D1 D2 D1 L Notes

HEF4557B LSI

1. The moment Dn appears at O depends on the bit-length shown in the table below. 2. H = HIGH state (the more positive voltage) 3. L = LOW state (the less positive voltage) 4. X = state is immaterial 5. 6. = positive-going transition = negative-going transition

7. Dn = either HIGH or LOW

BIT-LENGTH SELECT FUNCTION TABLE L32 L L L L L L L L L H H H H H H L16 L L L L L L L L H L L H H H H L8 L L L L L L L L H L L H H H H L4 L L L L H H H H H L L H H H H L2 L L H H L L H H H L L L L H H L1 L H L H L H L H H L H L H L H REGISTER LENGTH 1-bit 2-bits 3-bits 4-bits 5-bits 6-bits 7-bits 8-bits 32-bits 33-bits 34-bits 61-bits 62-bits 63-bits 64-bits

AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; input transition times 20 ns VDD V Dynamic power dissipation per package (P) 5 10 15 TYPICAL FORMULA FOR P (µW) 3 500 fi + (foCL) × VDD2 15 000 fi + (foCL) × VDD 37 000 fi + (foCL) × VDD
2 2

where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) (foCL) = sum of outputs VDD = supply voltage (V)

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Philips Semiconductors

Product specification

1-to-64 bit variable length shift register
AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times 20 ns VDD V Propagation delays CP0, CP1 O, O HIGH to LOW 5 10 15 5 LOW to HIGH MR O HIGH to LOW MR O LOW to HIGH Output transition times HIGH to LOW 10 15 5 10 15 5 10 15 5 10 15 5 LOW to HIGH 10 15 Interpolation table (see note next page) LENGTH CONTROL INPUTS L1 L H X X X X X Notes 1. H = HIGH state (the more positive voltage) 2. L = LOW state (the less positive voltage) 3. X = state is immaterial L2 L L H X X X X L4 L L L H X X X L8 L L L L H X X L16 L L L L L H X L32 L L L L L L H MINIMUM NUMBER OF BITS SELECTED 1 2 3 5 9 17 33 SET-UP, HOLD, RECOVERY TIMES specified six equal steps specified tTLH tTHL tPLH tPHL tPLH tPHL 240 90 65 240 90 65 170 80 60 140 70 55 60 30 20 60 30 20 480 180 130 480 180 130 340 160 120 280 140 110 120 60 40 120 60 40 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL TYP. MAX.

HEF4557B LSI

TYPICAL EXTRAPOLATION FORMULA 213 ns + (0,55 ns/pF) CL 79 ns + (0,23 ns/pF) CL 57 ns + (0,16 ns/pF) CL 213 ns + (0,55 ns/pF) CL 79 ns + (0,23 ns/pF) CL 57 ns + (0,16 ns/pF) CL 143 ns + (0,55 ns/pF) CL 69 ns + (0,23 ns/pF) CL 52 ns + (0,16 ns/pF) CL 113 ns + (0,55 ns/pF) CL 59 ns + (0,23 ns/pF) CL 47 ns + (0,16 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL

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Philips Semiconductors

Product specification

1-to-64 bit variable length shift register
AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times 20 ns; see also waveforms Fig.4 VDD V Minimum clock pulse width; LOW for CP0 or HIGH for CP1 Minimum reset pulse width; HIGH Set-up times DA, DB, A/B CP0, CP1 L1 to L32 = LOW L32 = HIGH Hold times DA, DB, A/B CP0, CP1 L1 to L32 = LOW L32 = HIGH Recovery times for MR L1 to L32 = LOW 5 10 15 5 10 15 5 10 15 5 L32 = HIGH Minimum clock pulse frequency 10 15 5 10 15 Note fmax tRMR tRMR thold thold -40 -10 0 90 60 50 500 250 150 110 70 60 2,5 7 10 -110 ns -45 ns -30 ns 30 ns 20 ns 15 ns 250 ns 125 ns 75 ns 50 ns 30 ns 25 ns 5 MHz 14 MHz 20 MHz see note 5 10 15 5 10 15 tsu tsu 360 140 90 40 35 30 180 ns 70 ns 45 ns -20 ns -10 ns -5 ns 5 10 15 5 10 15 tWMRH tWCPL or tWCPH 180 60 40 150 70 50 90 ns 30 ns 20 ns 75 ns 35 ns 25 ns SYMBOL MIN. TYP.

HEF4557B LSI

1. The set-up, hold and recovery times vary with the minimum number of bits selected. For other values as specified one may interpolate as shown in the table (see previous page).

January 1995

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Philips Semiconductors

Product specification

1-to-64 bit variable length shift register

HEF4557B LSI

Fig.4

Waveforms showing recovery time for MR and minimum CP0, CP1 and MR pulse widths, set-up and hold times for DA, DB and A/B to CP0 and CP1. Set-up and hold times are shown as positive values but may be specified as negative values.

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