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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14580B 4 x 4 Multiport Register
The MC14580B is a 4 by 4 multiport register useful in small scratch pad memories, arithmetic operations when coupled with an adder, and other data storage applications. It allows independent reading of any two words (or the same word at both outputs) while writing into any one of four words. Address changing and data entry occur on the rising edge of the clock. When the write enable input is low, the contents of any word may be accessed but not altered. · · · · · No Restrictions on Clock Input Rise or Fall Times 3State Outputs Single Phase Clocking Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Lowpower TTL Loads or one Lowpower Schottky TTL Load Over the Rated Temperature Range · Pin Compatible with CD40108 MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol VDD Parameter DC Supply Voltage L SUFFIX CERAMIC CASE 623
P SUFFIX PLASTIC CASE 709
DW SUFFIX SOIC CASE 751E
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Value Unit V V mA 0.5 to + 18.0 Vin, Vout Iin, Iout PD Tstg TL Input or Output Voltage (DC or Transient) Input or Output Current (DC or Transient), per Pin Power Dissipation, per Package Storage Temperature Lead Temperature (8Second Soldering) 0.5 to VDD + 0.5 ± 10 500 65 to + 150 260 mW
ORDERING INFORMATION
MC14XXXBCP MC14XXXBCL MC14XXXBDW Plastic Ceramic SOIC
TA = 55° to 125°C for all packages.
PIN ASSIGNMENT
Q3B Q2B 3STATE A Q0A Q1A Q2A Q3A WRITE 0 WRITE 1 READ 1B READ 0B VSS 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD Q1B Q0B 3STATE B D0 D1 D2 D3 CLOCK WE READ 1A READ 0A
_C _C
* Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages: 12 mW/_C From 100_C To 125_C
BLOCK DIAGRAM
W0 W1 R0A R1A R0B R1B 8 9 13 14 11 10 16
CLOCK
DECODER 3STATE A 3
WE
15 20 D0 19 D1 18 D2 17 D3
DATA INPUT
4X4 MEMORY
Q0A Q1A Q2A Q3A
4 5 6 7
WORD A OUTPUT
22 Q0B 23 Q1B 2 Q2B 1 Q3B 21 3STATE B
WORD B OUTPUT
VDD = PIN 24 VSS = PIN 12
REV 3 1/94
©MOTOROLA CMOS LOGIC DATA Motorola, Inc. 1995
MC14580B 1
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Symbol VOL VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 VIH 5.0 10 15 IOH Source 5.0 5.0 10 15 IOL 5.0 10 15 15 -- 5.0 10 15 5.0 10 15 3.0 0.64 1.6 4.2 0.64 1.6 4.2 -- -- -- -- -- -- -- -- -- -- -- -- ± 0.1 -- 5.0 10 20 2.4 0.51 1.3 3.4 0.51 1.3 3.4 -- -- -- -- -- 4.2 0.88 2.25 8.8 0.88 2.25 8.8 ± 0.00001 5.0 0.010 0.020 0.030 -- -- -- -- -- -- -- ± 0.1 7.5 5.0 10 20 1.7 0.36 0.9 2.4 0.36 0.9 2.4 -- -- -- -- -- -- -- -- -- -- -- -- ± 1.0 -- 150 300 600 mAdc 3.5 7.0 11 -- -- -- 3.5 7.0 11 2.75 5.50 8.25 -- -- -- 3.5 7.0 11 -- -- -- mAdc Min -- -- -- 55_C 25_C 125_C Max Min -- -- -- Typ # 0 0 0 Max Min -- -- -- Max Unit Vdc Output Voltage Vin = VDD or 0 "0" Level 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 Vdc "1" Level Vin = 0 or VDD Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) "1" Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current Input Capacitance (Vin = 0) Quiescent Current (Per Package) Total Supply Current** (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) ThreeState Leakage Current VIL -- -- -- -- -- -- 2.25 4.50 6.75 -- -- -- VOH 4.95 9.95 14.95 4.95 9.95 14.95 5.0 10 15 4.95 9.95 14.95 Vdc Vdc Sink Iin Cin IDD µAdc pF µAdc IT IT = (1.18 µA/kHz) f + IDD IT = (1.91 µA/kHz) f + IDD IT = (2.67 µA/kHz) f + IDD µAdc ITL 15 -- ± 0.1 -- ± 0.0001 ± 0.1 -- ± 3.0 µAdc #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. ** The formulas given are for the typical characteristics only at 25_C. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL 50) Vfk where: IT is in µA (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.004. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
MC14580B 2
MOTOROLA CMOS LOGIC DATA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns Propagation Delay Time Clock to Output Write Enable Setup Time (Enabling a Write or Read) Write Enable Removal Time (Disabling a Write or Read) Setup Time** Address, Data to Clock Hold Time** Clock to Address, Data 3State Enable/Disable Delay Time Symbol VDD 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 Min -- -- -- -- -- -- 800 300 200 0 0 0 50 30 25 480 195 150 -- -- -- 820 330 220 Typ # 100 50 40 650 250 170 400 150 100 100 50 35 20 0 0 160 65 50 130 60 45 410 165 110 Max 200 100 80 Unit ns tTLH, tTHL (Figures 3 and 6) tPLH, tPHL (Figures 3 and 6) tsu (Figure 5) trem (Figure 5) tsu (Figure 3) th (Figure 3) tPHZ, tPLZ tPZH, tPZL (Figures 4 and 7) tw (Figure 3) 1300 500 340 -- -- -- -- -- -- -- -- -- -- -- -- 260 120 90 -- -- -- ns ns ns ns ns ns Clock Pulse Width ns ** When loading repetitive highs, the output may glitch low momentarily after the rising edge of Clock. However, data integrity remains unaffected and data is valid after the propagation delays listed in the Switching Characteristics Table. VDD WE W0 W1 R0A R1A R0B R1B C D0 D1 D2 D3 Q0A Q1A Q2A Q3A Q0B Q1B Q2B Q3B VSS EXTERNAL POWER SUPPLY Position of S1 VGS = VDS = IDS Sink Current 2 VDD Vout Source Current 1 VDD Vout VDD Vout PULSE GENERATOR 1 2 S1 VDD VSS
Figure 1. Output Drive Current Test Circuit
MOTOROLA CMOS LOGIC DATA
MC14580B 3
VDD IDD PULSE GENERATOR 1 WE W0 W1 R0A R1A R0B R1B C D0 D1 D2 D3 VSS Q0A Q1A Q2A Q3A Q0B Q1B Q2B Q3B CL CL CL CL CL P.G. 2 CL CL P.G. 1 CL
REPETITIVE WAVEFORMS
PULSE GENERATOR 2 PULSE GENERATOR 3
P.G. 3 OUTPUT Qn A, B
Figure 2. Power Dissipation Test Circuit and Waveforms (3State Inputs are High)
tw(H) tw(L) CLOCK 50% tsu ADDRESS DATA 50% VSS tPLH, tPHL Q tTLH, tTHL 50% 90% 10% VOH VOL VSS th VDD VDD 3STATE A OR B tPHZ QA tPZL QB 10% 90% 50% 50% VSS tPZH 10% tPZL 90% VOH VOL VOH VOL VDD
Figure 3.
Figure 4.
VDD CLOCK tsu WE 50% 50% 50% VSS trem 50% VSS VDD DEVICE UNDER TEST Q CL
Figure 5.
Figure 6. Test Circuit
Q DEVICE UNDER TEST CL
1 k
CONNECT TO VCC WHEN TESTING tPLZ AND tPZL CONNECT TO GND WHEN TESTING tPHZ AND tPZH
Figure 7. Test Circuit
MC14580B 4
MOTOROLA CMOS LOGIC DATA
LOGIC DIAGRAM
R1A 14 C D Q Q R0A 13 C D Q Q R1B 10 C D Q Q R0B 11 C D Q Q Q C D 3STATE Q C D 3STATE 17 C D Q Q C D 3STATE Q C D 3STATE Q C D 3STATE D1 19 C D Q Q C D 3STATE Q C D 3STATE Q C D 3STATE 7 Q3A 3STATE A 3
CLOCK WE
16 15
6
Q2A
5
Q1A
D3
4
Q0A
D2
18
C D Q
1
Q3B
2
Q2B
D0
20
C D Q
23 Q1B
22 Q0B
W1
9
C D
Q Q
C W0 8 D
Q Q
21 3STATE B
TRUTH TABLE
Clock WE 1 1 X X 0 1 X X X 1 Write 1 0 0 X X X X 0 Write 0 1 1 X X X X 0 Read 1A 0 0 X X X X 0 Read 0A 1 1 X X X X 1 Read 1B 0 0 X X X X 1 Read 0B 1 1 X X X X 0 3State A 1 1 1 0 1 1 1 3State B 1 1 1 0 1 1 1 Dn 1 0 X X X X Dn to word 0 Word 0 not altered QnA 1 0 No Change Z No Change No Change Contents of word 1 displayed Contents of word 1 displayed QnB 1 0 No Change Z No Change No Change Contents of word 2 displayed Contents of word 2 displayed
0
0
0
0
1
1
0
1
1
Z = High Impedance X = Don't Care
MOTOROLA CMOS LOGIC DATA
MC14580B 5
OUTLINE DIMENSIONS
L SUFFIX CERAMIC DIP PACKAGE CASE 62305 ISSUE M
24 13 NOTES: 1. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 2. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION (WHEN FORMED PARALLEL). DIM A B C D F G J K L M N MILLIMETERS MIN MAX 31.24 32.77 12.70 15.49 4.06 5.59 0.41 0.51 1.27 1.52 2.54 BSC 0.20 0.30 3.18 4.06 15.24 BSC 0_ 15 _ 0.51 1.27 INCHES MIN MAX 1.230 1.290 0.500 0.610 0.160 0.220 0.016 0.020 0.050 0.060 0.100 BSC 0.008 0.012 0.125 0.160 0.600 BSC 0_ 15_ 0.020 0.050
B
1 12
A
SEATING PLANE
F
C
L G D N K M J
P SUFFIX PLASTIC DIP PACKAGE CASE 70902 ISSUE C
24 13 NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 31.37 32.13 13.72 14.22 3.94 5.08 0.36 0.56 1.02 1.52 2.54 BSC 1.65 2.03 0.20 0.38 2.92 3.43 15.24 BSC 0_ 15_ 0.51 1.02 INCHES MIN MAX 1.235 1.265 0.540 0.560 0.155 0.200 0.014 0.022 0.040 0.060 0.100 BSC 0.065 0.080 0.008 0.015 0.115 0.135 0.600 BSC 0_ 15_ 0.020 0.040
B
1 12
A N K H G F D
SEATING PLANE
C
L
M
J
MC14580B 6
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
DW SUFFIX PLASTIC SOIC PACKAGE CASE 751E04 ISSUE E
A
24 13 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 15.25 15.54 7.40 7.60 2.35 2.65 0.35 0.49 0.41 0.90 1.27 BSC 0.23 0.32 0.13 0.29 0_ 8_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.601 0.612 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 0_ 8_ 0.395 0.415 0.010 0.029
B
12X
P 0.010 (0.25)
M
B
M
1
12
24X
D 0.010 (0.25)
M
J T A
S
B
S
F R C T
SEATING PLANE X 45 _
M
22X
G
K
DIM A B C D F G J K M P R
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MOTOROLA CMOS LOGIC DATA
*MC14580B/D*
MC14580B MC14580B/D 7