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INTEGRATED CIRCUITS
DATA SHEET
TDA10045H DVB-T channel receiver
Product specification Supersedes data of 2000 Jun 21 File under Integrated Circuits, IC02 2001 Nov 08
Philips Semiconductors
Product specification
DVB-T channel receiver
FEATURES · 2 and 8 kbytes Coded Orthogonal Frequency Division Multiplexer (COFDM) demodulator (fully DVB-T compliant: ETSI 300-744) · All modes supported, including hierarchical modes · Fully automatic transmission parameters detection (including Fast Fourier Transformer (FFT) size and guard interval) · Digital Signal Processor (DSP) based synchronization (software can be upgraded on the fly) · No extra-host software required · On-chip 10-bit Analog-to-Digital Converter (ADC) · 2nd or 1st IF variable analog input · Only fundamental crystal oscillator required (4 MHz typical ±100 ppm) · 6, 7 and 8 MHz channels with the same crystal · Pulse killer algorithm to protect against impulse noise · Digital frequency correction (±90 kHz) · Frequency offset (±1/6 MHz) automatic estimator to speed-up the scan · RF tuner input power measurement · Parallel or serial transport stream interface · BER measurement (before and after Viterbi decoder) · Signal-to noise ratio estimation · Constellation, CSI and channel frequency response outputs · TPS bits I2C-bus readable (including spare ones) · Controllable dedicated I2C-bus for the tuner (5 V tolerant) · 3 low frequency spare DACs and 2 spare inputs · CMOS 0.2 µm technology. APPLICATIONS · DVB-T fully compatible · Digital data transmission using COFDM modulation. GENERAL DESCRIPTION
TDA10045H
The TDA10045H is a single-chip channel receiver for 2 and 8 kbytes COFDM modulated signals based on the ETSI specification (ETSI 300-744). The device interfaces directly to an IF signal, which could be either 1st or 2nd IF and integrates a 10-bit Analog-to-Digital Converter (ADC), a Numerically Controlled Oscillator (NCO) and a Phase-Locked Loop (PLL), simplifying external logic requirements and limiting system costs. The TDA10045H performs all the COFDM demodulation tasks from IF signal to the MPEG-2 transport stream. An internal DSP core manages the synchronization and the control of the demodulation process, and implements specially developed software for robustness against co-channel and adjacent channel interference, to deal with Single Frequency Network (SFN) echo situations, and to assist in a very fast scan of the bandwidth. After baseband conversion and FFT demodulation, the channel frequency response is estimated, which is based on the scattered pilots, and filtered in both time and frequency domains. This estimation is used as a correction on the signal, carrier by carrier. A common phase error and estimator is used to deal with the tuner phase noise. The Forward Error Correction (FEC) decoder is automatically synchronized by the frame synchronization algorithm that uses the TPS information included in the modulation. An embedded `pulse killer' algorithm enables the bad effects of short and strong impulsive noise interference that could be caused by electrical domestic devices and/or car traffic to be greatly reduced. This device is controlled via an I2C-bus (master). The chip provides 2 switchable I2C-buses derived from the master: a tuner I2C-bus to be disconnected from the I2C-bus master when not necessary and an EEPROM I2C-bus. The DSP software code can be fed to the chip via the master I2C-bus or via the dedicated EEPROM I2C-bus. Designed in 0.2 µm CMOS technology and housed in a 100 pin QFP package, the TDA10045H operates over the commercial temperature range.
2001 Nov 08
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Philips Semiconductors
Product specification
DVB-T channel receiver
ORDERING INFORMATION TYPE NUMBER TDA10045H PACKAGE
TDA10045H
VERSION NAME QFP100 DESCRIPTION plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 × 20 × 2.8 mm SOT317-2
2001 Nov 08
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VAGC digital IF FI (9:0) 10 AGC
BLOCK DIAGRAM
Philips Semiconductors
DVB-T channel receiver
TIME RECOVERY (NCO)
DIGITAL FRONT-END AND COFDM DEMODULATION CARRIER RECOVERY COFDM spectrum FFT
CHANNEL ESTIMATION AND CORRECTION
analog IF (VIM, VIP) fs SACLK 2fs
A 10 D C
BASEBAND CONVERSION
CPE CALCULATION
COARSE TIME ESTIMATOR
PARTIAL CHANNEL ESTIMATION
XIN
PLL SP_IN(1:0) spare inputs
TIME INTERPOLATION
DSP CORE
3 SPARE optional I2C-BUS INTERFACE 3* 10 SYNCHRONIZATION FREQUENCY, TIME, FRAME, RECOVERY FFT WINDOW POSITIONING TPS DECODING CONFIDENCE CALCULATION CHANNEL CORRECTION (I,Q) constellation FREQUENCY INTERPOLATION
Fig.1 Block diagram.
handbook, full pagewidth
4
DS_SPARE(3:1) SCL_EEP SDA_EEP SCL SDA
SCL_TUN SDA_TUN MPEG-2 OUTPUT INTERFACE
TDA10045H
confidence frequency response
DESCRAMBLER
RS DECODER
OUTER FORNEY DE-INTERLEAVER
VITERBI DECODER VBER
BIT DE-INTERLEAVER CBER
INNER FREQUENCY DE-INTERLEAVER AND DE-MAPPER
CPT_UNCOR CHANNEL DECODER
TDA10045H
Product specification
MGU414
Philips Semiconductors
Product specification
DVB-T channel receiver
PINNING SYMBOL VDDD33 VSSD DS_SPARE3 VAGC SCL_EEP VDDD33 VSSD SDA_EEP PIN 1 2 3 4 5 6 7 8 TYPE - - O O O - - I/OD digital ground supply (0 V DESCRIPTION digital supply voltage for the pads (3.3 V typ.)
TDA10045H
spare delta-sigma output; managed by the DSP to generate an analog level (after a RC low-pass filter) output value from the Delta-Sigma modulator, used to control a log-scaled amplifier (after analog filtering) extra I2C-bus clock to download DSP code from an external EEPROM (optional mode); can be connected to the master I2C-bus digital supply voltage for the pads (3.3 V typ.) digital ground supply (0 V) extra I2C-bus data bus to download DSP code from an external EEPROM (optional mode). It can be connected to the master I2C-bus; this pin is open-drain which requires an external pull-up resistor (to VDDD33 or VDDD50), even if not used. tuner I2C-bus serial clock signal; this signal is derived from the master SCL and is open-drain which requires an external pull-up resistor (to VDDD33 or VDDD50), even if not used tuner I2C-bus serial data signal; this signal is derived from the master SDA and is open-drain which requires an external pull-up resistor (to VDDD33 or VDDD50), even if not used I2C-bus master serial clock; up to 700 kbit/s I2C-bus master serial data input/output, open-drain I/O pad, which requires an external pull-up resistor (to VDDD33 or VDDD50) not connected asynchronous reset signal; active LOW EEPADDR is the LSB of the I2C-bus address of the EEPROM. The MSBs are internally set to 101000. Therefore the complete I2C-bus address of the EEPROM is (MSB to LSB): 1, 0, 1, 0, 0, 0, EEPADDR. SADDR[1:0] are the 2 LSBs of the I2C-bus address of the TDA10045; the MSBs are internally set to 00010; therefore the complete I2C-bus address of the TDA10045 is (MSB to LSB): 0, 0, 0, 1, 0, SADDR[1] and SADDR[0] digital supply voltage for the core (1.8 V typ.) digital ground supply (0 V) test mode bus; for test purpose; must be set to `0000' scan enable for production test; connected to GND digital supply voltage (5 V typ.); can be set to 3.3 V (with caution) if the 5 V tolerant I/O is not required digital ground supply (0 V) processor control, boot mode; if set to logic 0, the DSP downloads the software from an external EEPROM on the dedicated I2C-bus (pins SDA_EEP and SCL_EEP). If set to logic 1 the software is downloaded in the I2C-bus register CODE_IN from the host; in this case the external EEPROM is not needed. spare inputs
SCL_TUN
9
OD(1)
SDA_TUN
10
I/OD
SCL SDA n.c. CLR# EEPADDR
11 12 13 14 15
I(2) I/OD - I(2) I(2)
SADDR[1:0]
16 and 17
I(2)
VDDD18 VSSD TM[3:0] SCAN_EN VDDD50 VSSD DWNLOAD
18 19 20 to 23 24 25 26 27
- - I(2) I(2) - - I(2)
SP_IN[1:0]
28 and 29
I(2)
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Philips Semiconductors
Product specification
DVB-T channel receiver
TDA10045H
SYMBOL FFT_WIN VDDD33 VSSD SACLK FI[9:5]
PIN 30 31 32 33 34 to 38
TYPE I/O - - O I/O
DESCRIPTION output or input signal indicating the start of the active data; equals 1 during complex sample 0 of the active FFT block; can be used to synchronize 2 chips digital supply voltage for the pads (3.3 V typ.) digital ground supply (0 V) sampling frequency output; this output clock can be fed to an external (10-bit) ADC as a sampling clock; SACLK can also provide twice the sampling clock input data from an external ADC, FI must be tied to ground when unused, positive notation (from 0 to 1023) or twos complement notation (from -512 to +511). In internal ADC mode, these outputs can be used to monitor extra demodulator output signals (constellation or frequency response). digital supply voltage for the core (1.8 V typ.) digital ground supply (0 V) input data from an external ADC, FI must be tied to ground when unused, positive notation (from 0 to 1023) or twos complement notation (from -512 to +511). In internal ADC mode, these outputs can be used to monitor extra demodulator output signals (constellation or frequency response). digital supply voltage (5 V typ.); can be set to 3.3 V (with caution) if 5 V tolerant I/O is not required digital ground supply (0 V) interrupt line; this output interrupt line can be configured by the I2C-bus interface. This pin is an open-drain output and therefore requires an external pull-up resistor (to VDDD33 or VDDD50). front-end lock; FEL is an open-drain output and therefore requires an external pull-up resistor (to VDDD33 or VDDD50) not connected not connected asynchronous reset signal for boundary scan; connected to GND if not used mode programming signal for boundary scan; connected to GND if not used input port for boundary scan; connected to GND if not used clock signal for boundary scan; connected to GND if not used) output port for boundary scan; not connected if not used digital supply voltage for the core (1.8 V typ.) digital ground supply (0 V) spare delta-sigma output; managed by the DSP or by an I2C-bus register to generate an analog level (after a RC low-pass filter) spare delta-sigma output; managed by the DSP to handle a low frequency DAC (automatic first stage tuner AGC measurement or 2nd AGC loop control as examples) digital supply voltage for the pads (3.3 V typ.) digital ground supply (0 V) RS error flag, active HIGH on one RS packet if the RS decoder fails to correct the errors pulse synchro; this output signal goes HIGH on a rising edge of OCLK when a synchro byte is provided, then goes LOW until the next synchro byte 6
VDDD18 VSSD FI[4:0]
39 40 41 to 45
- - IO
VDDD50 VSSD IT
46 47 48
- - OD(1)
FEL n.c. n.c. TRSTN TMS TDI TCK TDO VDDD18 VSSD DS_SPARE2 DS_SPARE1
49 50 51 52 53 54 55 56 57 58 59 60
OD(1) - - I(2) I(2) I(2) I(2) O - - O O
VDDD33 VSSD UNCOR PSYNC
61 62 63 64
- - O O
2001 Nov 08
Philips Semiconductors
Product specification
DVB-T channel receiver
TDA10045H
SYMBOL DEN OCLK DO[7:5]
PIN 65 66 67 to 69
TYPE O O O
DESCRIPTION output data validation signal; active HIGH during the valid and regular data bytes output clock; OCLK is the output clock for the parallel DO[7:0] outputs output data carrying the current sample of the current MPEG2 packet (188 bytes), delivered on the rising edge of OCLK by default when the serial mode is selected. The output data is delivered by DO[0]. digital supply voltage for the core (1.8 V typ.) digital ground supply (0 V) output data carrying the current sample of the current MPEG2 packet (188 bytes), delivered on the rising edge of OCLK by default when the serial mode is selected. The output data is delivered by DO[0]. digital supply voltage for the pads (3.3 V typ.) digital ground supply (0 V) crystal oscillator input pin crystal oscillator output pin; typically a fundamental crystal oscillator is connected between pins XIN and XOUT digital supply voltage for the core (1.8 V typ.) digital ground supply (0 V) not connected power supply input for the digital circuits of the PLL module (1.8 V typ.) ground return for the digital circuits of the PLL module not connected ground return for the analog circuits of the PLL module power supply input for the analog circuits of the PLL module (3.3 V typ.) ground return for the analog circuits power supply input for the analog circuits; the DC voltage should be 3.3 V positive input to the ADC; this pin is DC biased to half supply through an internal resistor divider (2 × 20 k resistors). In order to remain in the range of the ADC, the voltage difference between pins VIP and VIM should be between -0.5 and +0.5 V. negative input to the ADC; this pin is DC biased to half supply to remain in the range of the ADC, the voltage difference between pins VIP and VIM should be between -0.5 and +0.5 V through an internal resistor divider (2 × 20 k resistors) negative reference voltage for the ADC positive reference voltage for the ADC power supply input for the analog circuits; the DC voltage should be 3.3 V ground return for analog circuits ground return for the analog clock drivers power supply input for the analog clock drivers; the DC voltage should be 3.3 V ground return for the digital switching circuitry power supply input for the digital switching circuitry; sensitive to the supply noise; the DC voltage should be 1.8 V
VDDD18 VSSD DO[4:0]
70 71 72 to 76
- - O
VDDD33 VSSD XIN XOUT VDDD18 VSSD n.c. VCCD(PLL) DGND n.c. PPLGND VCCA(PLL) VSSA3 VDDA3 VIP
77 78 79 80 81 82 83 84 85 86 87 88 89 90 91
- - I(2) O - - - - - - - - - - -
VIM
92
-
Vref(neg) Vref(pos) VDDA3 VSSA3 VSSA2 VDDA2 VSSA1 VDDD1
93 94 95 96 97 98 99 100
- - - - - - - -
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Philips Semiconductors
Product specification
DVB-T channel receiver
Notes
TDA10045H
1. OD are open-drain outputs, so they must be connected to a pull-up resistor to either VDDD33 or VDDD50 2. All inputs (I) are TTL, 5 V tolerant, (if VDD50 is set to 5 V). 3. Foundry test I/O inputs must be connected to GND.
84 VCCD(PLL) 83 n.c.
88 VCCA(PLL) 87 PPLGND
93 Vref(neg)
94 Vref(pos)
100 VDDD1
handbook, full pagewidth
VDDD33 VSSD DS_SPARE3 VAGC SCL_EEP VDDD33 VSSD SDA_EEP SCL_TUN
1 2 3 4 5 6 7 8 9
82 VSSD 81 VDDD18
80 XOUT 79 XIN 78 VSSD 77 VDDD33 76 DO[0] 75 DO[1] 74 DO[2] 73 DO[3] 72 DO[4] 71 VSSD 70 VDDD18 69 DO[5] 68 DO[6] 67 DO[7] 66 OCLK 65 DEN 64 PSYNC 63 UNCOR 62 VSSD 61 VDDD33 60 DS_SPARE1 59 DS_SPARE2 58 VSSD 57 VDDD18 56 TDO 55 TCK 54 TDI 53 TMS 52 TRSTN 51 n.c.
98 VDDA2 97 VSSA2
96 VSSA3 95 VDDA3
91 VIP 90 VDDA3
99 VSSA1
89 VSSA3
SDA_TUN 10 SCL 11 SDA 12 n.c. 13 CLR# 14 EEPADDR 15 SADDR[1] 16 SADDR[0] 17 VDDD18 18 VSSD 19 TM[3] 20 TM[2] 21 TM[1] 22 TM[0] 23 SCAN_EN 24 VDDD50 25 VSSD 26 DWNLOAD 27 SP_IN[1] 28 SP_IN[0] 29 FFT_WIN 30
TDA10045H
VDDD33 31 VSSD 32
SACLK 33
FI[9] 34
FI[8] 35
FI[7] 36
FI[6] 37
FI[5] 38
VDDD18 39 VSSD 40
FI[4] 41
FI[3] 42
FI[2] 43
FI[1] 44
FI[0] 45
VDDD50 46 VSSD 47
85 DGND
92 VIM
86 n.c.
IT 48
FEL 49
n.c. 50
MGU413
Fig.2 Pin configuration.
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Philips Semiconductors
Product specification
DVB-T channel receiver
LIMITING VALUES In accordance with the Absolute Maximum Rate System (IEC 60134); note 1. SYMBOL VDDD18 VDDD33 VI II Tlead Tstg Tj Tamb Note PARAMETER digital supply voltage for the core digital supply voltage for the pads DC input voltage DC input current lead temperature storage temperature junction temperature ambient temperature MIN. -0.5 -0.5 -0.5 - - -65 - 0
TDA10045H
MAX. +2.1 +3.8 +5.5 ±20 300 +150 150 70 V V V
UNIT
mA °C °C °C °C
1. Stresses above the Absolute Maximum Ratings may cause permanent damage to the device. Exposure to Absolute Maximum Ratings conditions for extended periods may affect device reliability. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE tbf UNIT K/W
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Philips Semiconductors
Product specification
DVB-T channel receiver
CHARACTERISTICS SYMBOL Core and pads VDDD33 VDDD18 VDDD50 Tamb VIH VIL VOH VOL Ci Co PLL VCCD(PLL) VCCA(PLL) ADC VDDD1 VDDA2, VDDA3 Vi(ADC) Vi digital ADC supply voltage analog ADC supply voltage analog ADC inputs pins VIP and VIM signal input IR = VIP - VIM; depending on SW register VDDD = 1.8 V ± 5% VDDA = 3.3 V ± 10% 1.7 2.97 -0.5 -0.5 to -1.0 1.8 3.3 - - digital PLL supply voltage analog PLL supply voltage VCCD = 1.8 V ± 5% VCCA = 3.3 V ± 10% 1.7 2.97 1.8 3.3 digital supply voltage for the pads digital supply voltage for the core 5 V supply voltage ambient temperature HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage input capacitance output capacitance TTL input; note 2 TTL input IOH = ±2 mA IOL = ±2 mA VDDD = 3.3 V ± 10% VDDD = 1.8 V ± 5% only for 5 V requirements; note 1 2.97 1.7 4.75 0 2 0 2.4 - - - 3.3 1.8 5.0 - - - - - - - PARAMETER CONDITIONS MIN. TYP.
TDA10045H
MAX.
UNIT
3.63 1.9 5.25 70 VDDD50 0.8 - 0.4 5 5
V V V °C V V V V pF pF
1.9 3.63
V V
1.9 3.63 VDDD3 + 0.5 +0.5 to +1.0
V V V V
Vref(pos) Vref(neg) Vi(offset) Ri Ci BW
positive reference voltage negative reference voltage input offset voltage input resistance pin VIP or VIM input capacitance pin VIP or VIM input full power bandwidth
with SW register = 11 1.95 with SW register = 11 0.95 -25 - - 3 dB bandwidth 40
2.15 1.15 - 10 5 50
2.35 1.35 +25
V V mV k
10 -
pF MHz
2001 Nov 08
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Philips Semiconductors
Product specification
DVB-T channel receiver
TDA10045H
SYMBOL Power consumption IDDD
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
digital supply current on pins: VDDD18 and VDDD1 VDDD33 VCCD(PLL), VDDA2 and VDDA3 VDDD50
fs = 29 Mhz; direct IF application - - - - - 140 3 35 5 400 160 - - - 470 mA mA mA mA mW
Ptot Notes
total power dissipation
1. The voltage level of the 5 V supply must always exceed, or at least equal, the voltage level of the 3.3 V supply during power-up and down in order to guarantee protection against latch-up. 2. All inputs are 5 V tolerant.
2001 Nov 08
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Philips Semiconductors
Product specification
DVB-T channel receiver
APPLICATION INFORMATION
TDA10045H
handbook, full pagewidth
RC
I2C-BUS EEPROM optinal
IF1 RF TUNER + SAWs RF_AGC SCL SDA
IF_AGC IF INTERFACE
IF1 or IF2
VAGC VIP VIM A D C
XIN 10
XOUT
SDA_EEP SCL_EEP
PSYNC UNCOR
optional IF2 downconversion reference frequency RC SACLK SDA_TUN SCL_TUN RC
TDA10045H
8
DEN OCLK DO[7:0]
DS_SPARE_1 SP_IN(0) optional ADC I2C-bus
MGU415
SCL, SDA
Fig.3 DVB-T front-end receiver.
handbook, full pagewidth
VDDD50 VDDD33 VDDD18
VSSD
XIN 10
XOUT
VAGC SDA_TUN
FI[9:0]
SCL_TUN IT
TDA10045H
CLR# VIP VIM I2C-BUS INTERFACE 8
FEL PSYNC UNCOR DEN OCLK
DSP INTERFACE
JTAG
DO[7:0]
MGU416
SADDR(1:0) SCL
SDA
SDA_EEP SCL_EEP
SP_IN
BS_SPARE
TDI TDO TCK TMS TRST
Fig.4 Application diagram.
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Philips Semiconductors
Product specification
DVB-T channel receiver
Tuner · A RF tracking filter tracks the RF wanted frequency and suppresses the image · A first local wideband AGC is usually done at RF level, the AGC level information could be provided externally and the chip offers facilities to measure this level by the optional ADC (this measurement is automatically made by the DSP, the host has just to read the result) · A mixer oscillator and a PLL downconverts the RF signal to intermediate frequency IF1 (36.125 MHz typ.) · SAW filters eliminate the power of the adjacent channels around IF1. IF interface · It is either an analog IF amplifier when IF1 is sampled (direct IF: digital downconversion concept) or an analog IF amplifier followed by a downconversion from IF1 to IF2 at a few MHz (e.g. 4.57 MHz) · When this second solution is used, the ADC sampling clock could be used (after low-pass filtering) as a reference clock for downconversion (twice the ADC sampling clock could also be provided) · The IF amplifier is controlled by the digital AGC of the chip. A simple RC circuit filters the single bit ( modulated) AGC control (VAGC) · The sampling clock could also be used to control an external ADC, the inputs to the chip will then be digital (FI[9:0]). TDA10045H
TDA10045H
· The chip is controlled by an I2C-bus and driven by an external low-cost crystal oscillator · The software of the embedded DSP can be downloaded from the main I2C-bus or from a dedicated I2C-bus connected to an external slave I2C-bus EEPROM · An internal bidirectional switch enables the tuner to be programmed through the chip and then switch-off the link in order to avoid phase noise distortions due to I2C-bus traffic.
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Philips Semiconductors
Product specification
DVB-T channel receiver
PACKAGE OUTLINE QFP100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
TDA10045H
SOT317-2
c
y X
80 81
51 50 ZE
A
e E HE A A2 A1 (A 3) Lp bp 100 1 wM D HD ZD B v M B 30 v M A 31 detail X L
wM pin 1 index
e
bp
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.20 A1 0.25 0.05 A2 2.90 2.65 A3 0.25 bp 0.40 0.25 c 0.25 0.14 D (1) 20.1 19.9 E (1) 14.1 13.9 e 0.65 HD 24.2 23.6 HE 18.2 17.6 L 1.95 Lp 1.0 0.6 v 0.2 w 0.15 y 0.1 Z D (1) Z E(1) 0.8 0.4 1.0 0.6 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT317-2 REFERENCES IEC JEDEC MO-112 EIAJ EUROPEAN PROJECTION
ISSUE DATE 97-08-01 99-12-27
2001 Nov 08
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Philips Semiconductors
Product specification
DVB-T channel receiver
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 220 °C for thick/large packages, and below 235 °C for small/thin packages. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
TDA10045H
· Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. · For packages with leads on two sides and a pitch (e): larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. · For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C.
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Philips Semiconductors
Product specification
DVB-T channel receiver
Suitability of surface mount IC packages for wave and reflow soldering methods
TDA10045H
SOLDERING METHOD PACKAGE WAVE BGA, HBGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DATA SHEET STATUS DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2) Development DEFINITIONS This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable
Preliminary data
Qualification
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
2001 Nov 08
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Philips Semiconductors
Product specification
DVB-T channel receiver
DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS
TDA10045H
Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. ICs with MPEG-2 functionality Use of this product in any manner that complies with the MPEG-2 Standard is expressly prohibited without a license under applicable patents in the MPEG-2 patent portfolio, which license is available from MPEG LA, L.L.C., 250 Steele Street, Suite 300, Denver, Colorado 80206.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
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Philips Semiconductors
Product specification
DVB-T channel receiver
NOTES
TDA10045H
2001 Nov 08
18
Philips Semiconductors
Product specification
DVB-T channel receiver
NOTES
TDA10045H
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Philips Semiconductors a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: [email protected].
© Koninklijke Philips Electronics N.V. 2001
SCA73
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753504/04/pp20
Date of release: 2001
Nov 08
Document order number:
9397 750 08496