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INTEGRATED CIRCUITS
DATA SHEET
TDA8421 Hi-fi stereo audio processor; I2C bus
Product specification File under Integrated Circuits, IC02 May 1988
Philips Semiconductors
Product specification
Hi-fi stereo audio processor; I2C bus
TDA8421
GENERAL DESCRIPTION The TDA8421 is a monolithic bipolar integrated stereo sound circuit with a loudspeaker channel (CH1) and a headphone channel (CH2), digital controlled via the I2C bus, for application in hi-fi audio and television sound.
Features · Input selector · Mode selector · Loudspeaker channel (CH1); with volume control, balance control and mute · Headphone channel (CH2); with volume control, balance control and mute · Pseudo stereo and spatial function · Bass and treble control · Electrostatic discharge protection diodes
QUICK REFERENCE DATA PARAMETER Supply voltage (pin 4) Input signal handling Input sensitivity full power at the output stage Signal plus noise-to-noise ratio Total harmonic distortion Channel separation Volume control range CH1 Treble control range Bass control range Volume control range CH2 PACKAGE OUTLINE 28-lead dual in-line; plastic (SOT117); SOT 117-1; 1996 november 19. Vi (S+N)/N THD G G G G - - - - -62 -12 -12 -62 200 90 0,05 75 - - - - - - - - 16 12 15 0 mV dB % dB dB dB dB dB SYMBOL VCC VI MIN. 7,5 2 TYP. 12 - MAX. 14 - V V UNIT
May 1988
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May 1988
Philips Semiconductors
Hi-fi stereo audio processor; I2C bus
3 Product specification
* These values are dependent on the required frequency response and effect.
TDA8421
Fig.1 Block diagram.
Philips Semiconductors
Product specification
Hi-fi stereo audio processor; I2C bus
PINNING
TDA8421
Fig.2 Pinning diagram.
FUNCTIONAL DESCRIPTION Input selector The input to channel 1 (CH1) and channel 2 (CH2) is determined by the input selector. The selection is made from the following AF input signals: · IN1 L (pin 26); IN1 R (pin 28) or · IN2 L (pin 1); IN2 R (pin 3) Where IN1 is an internal input signal and IN2 an external input signal. Mode selector For each channel (CH1 and CH2) there is a mode selector which selects between stereo, sound A and sound B in the event of bilingual transmission. Both mode selectors can be controlled independently.
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Philips Semiconductors
Product specification
Hi-fi stereo audio processor; I2C bus
Headphone channel (CH2) Volume control and balance The stages for volume control for CH2 consist of two parts for left and right. In each part the gain can be adjusted between 0 and -62 dB in steps of 2 dB. An additional step allows an attenuation of 90 dB. Both parts can be controlled independently over the whole range, which allows the balance to be varied by controlling the volume of left and right. Loudspeaker channel (CH1) Volume control and balance The loudspeaker channel (CH1) also consists of two parts for volume control (left and right). In each part the gain can be adjusted between + 16 dB and -62 dB in steps of 2 dB. An additional step allows an attenuation of 90 dB. Both parts can be controlled independently over the whole range, which allows the balance to be varied by controlling the volume of left and right. Stereo/pseudo stereo/spatial stereo mode It is possible to select three modes. Stereo, pseudo or spatial stereo. The pseudo stereo mode receives mono transmissions and the stereo and spatial stereo mode receives stereo transmissions. Bass control The bass control stage can be switched from an emphasis of 15 dB to an attenuation of 12 dB for low frequencies in steps of 3 dB. Treble control The treble control stage can be switched from + 12 dB to -12 dB in steps of 3 dB. I2C bus receiver and data handling Bus specification Bias and power supply
TDA8421
The TDA8421 includes a bias and power supply stage, which generates a voltage of 1/2 VCC with a low output impedance and injector currents for the logic part. Power-on reset The on-chip power-on reset circuit sets the mute bit to active, which mutes both the loudspeaker channel (CH1) and the headphone channel (CH2). The muting can be switched by transmission of the mute bit.
The TDA8421 is controlled via the 2-wire I2C bus by a microcomputer. The two wires (SDA - serial data, SCL serial clock) carry information between the devices connected to the bus. Both SDA and SCL are bidirectional lines, connected to a positive supply voltage via a pull up resistor. When the bus is free both lines are HIGH. The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. The set up and hold times are specified in AC CHARACTERISTICS. A HIGH-to-LOW transition of the SDA line while SCL is HIGH is defined as a start condition. A LOW-to-HIGH transition of the SDA line while SCL is HIGH is defined as a stop condition. The bus receiver will be reset by the reception of a start condition. The bus is considered to be busy after the start condition. The bus is considered to be free again after a stop condition. Module address Data transmission to the TDA8421 starts with the module address MAD.
Fig.3 TDA8421 module address.
The module address is determined by pin 16. When connected to ground MAD = 0; when connected to VCC MAD = 1. Thus two TDA8421s can be selected within a system. May 1988 5
Philips Semiconductors
Product specification
Hi-fi stereo audio processor; I2C bus
Subaddress After the module address byte a second byte is used to select the functions for both channels: · CH1 - Volume left, volume right, bass, treble and switch functions · CH2 - Volume left, volume right and switch functions
TDA8421
The subaddress SAD is stored within the TDA8421. Table 1 defines the coding of the second byte after the module address MAD. Table 1 Second byte after module address MAD 128 MSB FUNCTION volume left volume right CH1 bass treble switch functions volume left CH2 volume right switch functions 7 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 3 0 0 0 0 1 0 0 1 2 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 0 64 32 16 8 4 2 1 LSB 0 0 1 0 1 0 0 1 0
subaddress SAD Definition of 3rd byte A third byte is used to transmit data to the TDA8421. Table 2 defines the coding of the third byte after module address MAD and subaddress SAD. Table 2 Third byte after module address MAD and subaddress SAD MSB FUNCTION volume left volume right CH1 bass treble switch functions volume left CH2 volume right switch functions VL1 VR1 BA TR S1 VL2 VR2 S2 1 1 1 1 1 1 1 1 7 1 1 1 1 1 1 1 1 6 5 V05 V15 1 1 MU V25 V35 1 4 V04 V14 1 1 EFL V24 V34 1 3 V03 V13 BA3 TR3 STL V23 V33 EXS 2 V02 V12 BA2 TR2 ML1 V22 V32 MH1 1 V01 V11 BA1 TR1 ML0 V21 V31 MH0 V00 V10 BA0 TR0 IS V20 V30 1 LSB 0
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Philips Semiconductors
Product specification
Hi-fi stereo audio processor; I2C bus
Truth tables Truth tables for the switch functions Table 3 Input selector function IN1 IN2 IS 0 1 stereo sound A sound B ---------Table 5 Stereo/pseudo stereo/spatial stereo choise spatial stereo pseudo ----------1 1 0 0 STL EFL 1 0 1 0 active; automatic after POR(1) not active Notes Table 6 Mute mute mode 1 1 0 0 Table 4 Mode selectors CH1 ML0 ML1 1 0 1 0
TDA8421
CH2 MH0 1 1 0 0 MH1 1 0 1 0
MU 1 0
1. Attenuation 90 dB; POR = Power-On Reset. Table 7 Output for external switch EXSN ground open collector EXS 1 0
Truth tables for the volume base and treble controls. Table 8 CH1 16 14 -46 -48 -62 -90 -90 Note 1. The values of CH1 and CH2 are in 2 dB/step measured in dBs. May 1988 7 0 -2 -62 -90 -90 -90 -90 Volume control CH2 1 1 0 0 0 0 V×5 1 0 1 1 1 0 V×4 1 0 1 1 0 0 V×3 1 0 1 0 1 0 V×2 1 0 1 0 1 0 V×1 1 0 1 0 1 0 V×0
Philips Semiconductors
Product specification
Hi-fi stereo audio processor; I2C bus
Table 9 Bass control BA3 1 ------1 1 ------0 ------0 ------0 BA2 1 ------0 0 ------1 ------0 ------0 BA1 1 ------1 1 ------1 ------1 ------0 BA0 1 ------1 0 ------0 ------0 ------0
TDA8421
3dB/STEP (dB) 15 ------15 12 ------0 -------12 -------12
Table 10 Treble control 3dB/STEP (dB) 12 ------12 ------0 -------12 -------12 TR3 1 ------1 ------0 ------0 ------0 TR2 1 ------0 ------1 ------0 ------0 TR1 1 ------1 ------1 ------1 ------0 TR0 1 ------0 ------0 ------0 ------0
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Philips Semiconductors
Product specification
Hi-fi stereo audio processor; I2C bus
Sequence of data transmission
TDA8421
After a power-on reset all eight functions have to be adjusted with eight data transmissions. It is recommended that data information for switch functions in CH1 are transmitted last because all functions have to be adjusted when the muting is switched off. The sequence of transmission of other data information is not critical. The order of data transmission is shown in Figures 4 and 5. The number of data transmissions is unrestricted but before each data byte the module address MAD and the correct subaddress SAD is required.
Fig.4 Data transmission after a power-on reset.
Fig.5 Data transmission except after power-on reset.
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Philips Semiconductors
Product specification
Hi-fi stereo audio processor; I2C bus
RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) PARAMETER Supply voltage Voltage range at pins for external capacitors pins 2, 6, 8 to 10, 19 to 21, 23 to 25, 27 pin 13 pin 14 pin 15 pin 16 Voltage range at pins 1, 3, 7, 11, 18, 22, 26, 28 Output current at pins 7, 11, 18, 22 Total power dissipation at Tamb < 70 °C Operating ambient temperature range Storage temperature range Electrostatic handling(1) Note 1. Equivalent to discharging a 100 pF capacitor through a 1,5 k resistor. Ptot Tamb Tstg ±VESD - 0 -25 - 1350 70 150 2000 VI, VO IO 0 - VCC 45 Vcap VSDA VSCL VEXSN VMAD 0 0 0 0 0 VCC VCC VCC VCC VCC SYMBOL VCC 0 MIN. 16 MAX.
TDA8421
UNIT V V V V V V V mA mW °C °C V
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Philips Semiconductors
Product specification
Hi-fi stereo audio processor; I2C bus
DC CHARACTERISTICS VCC = 12 V; Tamb = 25 °C; unless otherwise specified PARAMETER Supply voltage (pin 4) Supply current at VCC = 12 V Internal input voltage IN1 L,R (pins 26,28) IN2 L,R (pins 1,3) DC voltage internally generated; capacitive coupling recommended MAD (pin 16) input voltage HIGH input voltage LOW input current HIGH input current LOW SDA; SCL (pins 13 and 14) input voltage HIGH input voltage LOW input current HIGH input current LOW Output voltage at CH1 (pins 11 and 18); CH2 (pins 7 and 22) pins with external capacitors pins 6 to 10; 19 to 21; 23 to 25 pin 2 External switch (pin 15) at IEXSN = 1 mA Output voltage HIGH Output voltage LOW VEXSNH VEXSNL - - - - 16 0,3 Vcap.n Vcap.2 - -
1/ 2
TDA8421
SYMBOL VCC ICC 7,5 -
MIN. 12 42
TYP. 14 55
MAX. V
UNIT
mA
VI VIH VIL IIH IIL VIH VIL IIH IIL
5,4 3,0 0 - - 3,0 -0,3 - -
6,0 - - - 1 - - - 1
6,6 VCC 1,5 1,0 10 VCC 1,5 1,0 10
V V V µA µA V V µA µA
VO
5,4
1/
2
VCC
6,6
V
VCC
- -
V V
VCC-0,1
V V
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Philips Semiconductors
Product specification
Hi-fi stereo audio processor; I2C bus
AC CHARACTERISTICS VCC = 12 V; bass/treble in linear position; pseudo and spatial stereo off; RL > 10 k; CL < 100 pF; Tamb = 25 °C unless otherwise specified. PARAMETER I2C bus timing (see Fig.6) SDA, SCL (pin 13 and 14) Clock frequency range The HIGH period of the clock The LOW period of the clock SCL rise time SCL fall time Set-up time for start condition Hold time for start condition Set-up time for stop condition Time bus must be free before a new transmission can start Set-up time DATA Input signals IN1 L (pin 26) IN1 R (pin 28) IN2 L (pin 1) IN2 R (pin 3) Input signal handling (r.m.s. value) at Vu = -4 dB; THD 0,5% Input resistance Frequency response (-0,5 dB) bass and treble in linear position; stereo mode; effects off f 20 - 20 000 Vi(rms) Rn-5 2 35 - 50 - - tBUF tSU; DAT 4,7 250 - - - - fSCL tHIGH tLOW tr tf tSU;STA tHD; STA tSU; STO 0 4 4,7 - - 4,7 4 4,7 - - - - - - - - 100 - - 1 0,3 - - - SYMBOL MIN. TYP.
TDA8421
MAX.
UNIT
kHz µs µs µs µs µs µs µs µs ns
V k
Hz
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Philips Semiconductors
Product specification
Hi-fi stereo audio processor; I2C bus
TDA8421
PARAMETER LOUDSPEAKER CHANNEL OUTPUTS CH1 LEFT (pin 18); CH1 RIGHT (pin 11) Output voltage range (r.m.s. value) at THD 0,5% Load resistance Output impedance Noise level weighted according to CCIR468-2 gain = 16 dB gain = 0 dB gain = -90 dB Total harmonic distortion (f = 20 Hz to 12,5 kHz) for Vi(rms) = 0,5 V; gain = + 16 dB to -30 dB for Vi(rms) = 1,0 V; gain = +2 dB to -30 dB for Vi(rms) = 2,0 V; gain = -4 dB to -30 dB Channel separation at 10 kHz gain = 0 dB Ripple rejection (gain = 0 dB; bass and treble in linear position) fripple = 100 Hz Crosstalk attenuation from logic inputs to AF outputs (gain = 0 dB; bass and treble in linear position) VOLUME CONTROL For truth table see Table 8 L cr Vn Vn Vn
SYMBOL
MIN.
TYP.
MAX.
UNIT
Vo(rms) RL ZO
2 10 -
- - -
- - 100
V k
- - -
90 20 15
- 40 -
µV µV µV
THD THD THD
- - - -
0,05 0,07 0,1 75
0,2 0,2 - -
% % % dB
RR100
-
50
-
dB
-
110
-
dB
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Philips Semiconductors
Product specification
Hi-fi stereo audio processor; I2C bus
TDA8421
PARAMETER Loudspeaker channel (CH1) Control range at f = 1 kHz maximum voltage gain (16 dB step) minimum voltage gain (-62 dB step) last position mute position Resolution Gain difference between left and right AF channel (note 1) gain from 16 dB to -30 dB gain from -30 dB to -62 dB TREBLE CONTROL (CH1) For truth table see Table 10 Control range for C10-5; C19-5 = 5,6 nF Maximum emphasis at 15 kHz with respect to linear position Maximum attenuation at 15 kHz with respect to linear position Resolution BASS CONTROL For truth table see Table 9 Control range for C8-9; C20-21 = 33 nF Maximum emphasis at 40 kHz with respect to linear position Maximum attenuation at 40 kHz with respect to linear position Resolution SPATIAL AND PSEUDO FUNCTION Spatial: Antiphase crosstalk Pseudo: Phase shift (see Fig.15) G G G G G G
SYMBOL
MIN.
TYP.
MAX.
UNIT
Gmax Gmin Goff Gmute Gstep
15 -60 -80 -85 -
- - -85 -90 2
- - - - -
dB dB dB dB dB/step
- -
- -
0,5 1
dB dB
11 11 -
12 12 3
13 13 -
dB dB dB/step
Gstep
14 11 -
15 12 3
16 13 -
dB dB dB/step
Gstep
-
50
-
%
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Philips Semiconductors
Product specification
Hi-fi stereo audio processor; I2C bus
TDA8421
PARAMETER HEADPHONE CHANNEL OUTPUTS CH2 LEFT (pin 22); CH2 RIGHT (pin 7) Output voltage range (r.m.s. value) at THD 0,5% Load resistance Output impedance Noise level (weighted according to CCIR468-2) gain = 0 dB gain = 16 dB gain = -90 dB Total harmonic distortion (f = 20 Hz to 12,5 kHz) for Vi(rms) = 0,2 V; gain = 0 dB to -30 dB for Vi(rms) = 1,0 V; gain = 0 dB to -30 dB for Vi(rms) = 2,0 V gain = -4 dB to -30 dB Channel separation at 10 kHz gain = 0 dB Ripple rejection (gain = 0 dB; bass and treble in linear position) fripple = 100 Hz Crosstalk attenuation from logic inputs to AF outputs (gain = 0 dB; bass and treble in linear position) Crosstalk between any input/output f = 100 Hz to 12,5 kHz Crosstalk IN1/IN2 gain = 0 dB; RG = 0 L cr Vn Vn Vn
SYMBOL
MIN.
TYP.
MAX.
UNIT
Vo(rms) RL ZO
2 10 -
- - -
- - 100
V k
- - -
15 12 10
- 25 -
µV µV µV
THD THD
- - - -
0,01 0,1
0,2 - - -
% %
THD
0,3 75
% dB
RR100
-
50
-
dB
- 65 95
110 70 100
- - -
dB dB dB
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Philips Semiconductors
Product specification
Hi-fi stereo audio processor; I2C bus
TDA8421
PARAMETER Headphone channel (CH2) Control range maximum voltage gain (0 dB step) minimum voltage gain (-62 dB step) last position mute position Resolution Gain difference between left and right AF channel (note 1) gain from 0 dB to -40 dB gain from -40 dB to -62 dB Note to the AC characteristics G G
SYMBOL
MIN.
TYP.
MAX.
UNIT
Gmax Gmin Goff Gmute Gstep
-1 -57 -80 -85 -
- - -85 -90 2
- - - - -
dB dB dB dB dB/step
- -
- -
0,5 2
dB dB
1. Balance is realized via software by different volume settings in both channels.
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Philips Semiconductors
Product specification
Hi-fi stereo audio processor; I2C bus
TDA8421
tSU; STA = start code set-up time tHD; STA = start code hold time tSU; STO = stop code set-up time
tBUF = BUS free time tSU; DAT = data set-up time tHD; DAT = DATA hold time
Fig.6 Timing requirements for I 2 C bus.
Fig.7
Distortion loudspeaker channel CH1 as a function of the output voltage with gain as parameter.
Fig.8
Distortion loudspeaker channel CH1 as a function of the output voltage with input voltage as parameter.
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Philips Semiconductors
Product specification
Hi-fi stereo audio processor; I2C bus
TDA8421
Fig.9 Channel separation loudspeaker channel CH1 as a function of frequency.
Fig.10 Signal-to-noise ratio as a function of output power. Input voltage Vi = 0,5 V; according to CCIR; quasi peak; Po = 15 W.
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Philips Semiconductors
Product specification
Hi-fi stereo audio processor; I2C bus
TDA8421
Fig.11 Crosstalk 2-tone mode as a function of frequency. CH1: mode AA, Gain + 16 dB; CH2: mode BB, Gain 0 dB. Signal input RIGHT; input LEFT to ground, measured at output CH1.
Fig.12 Crosstalk between IN1 and IN2 as a function of frequency; measured at output CH1; RG = 0. a) Gain = + 16 dB; Vi = 200 mV. b) Gain = 0 dB; Vi = 1 V.
May 1988
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Philips Semiconductors
Product specification
Hi-fi stereo audio processor; I2C bus
TDA8421
Fig.13 Bass and treble tone control. Cbass = 33 nF, Ctreble = 5,6 nF.
Fig.14 Bass and treble tone control. Cbass = 68 nF, Ctreble = 3.9 nF.
May 1988
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Philips Semiconductors
Product specification
Hi-fi stereo audio processor; I2C bus
TDA8421
CURVE 1 2 3
PIN 24 (nF) 15 5,6 5,6 15 47 68
PIN (nF)
EFFECT normal intensified more intensified
Fig.15 Pseudo (phase) as a function of frequency CH 1 left.
May 1988
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Philips Semiconductors
Product specification
Hi-fi stereo audio processor; I2C bus
TDA8421
Fig.16 Test and application circuit diagram.
May 1988
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Philips Semiconductors
Product specification
Hi-fi stereo audio processor; I2C bus
TDA8421
Fig.17 Turn-on/off power supply circuit diagram.
ICC = 45 mA; Iload = 259 mA; ton = 2,64 ms; toff = 102 ms.
Fig.18 Turn-on behaviour; C = 2,2 µF; RL = 10 k.
Fig.19 Turn-off behaviour; without modulation.
Fig.20 Turn-off behaviour; with modulation (shaded area). May 1988 23
Philips Semiconductors
Product specification
Hi-fi stereo audio processor; I2C bus
TDA8421
Fig.21 Level diagram loudspeaker channel CH1 with Vi(min) = 200 mV; Vo = 1,25 for Pmax.
Fig.22 Level diagram headphone channel CH2 with Vi = 200 mV; Vo = 200 mV for Pmax.
May 1988
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Philips Semiconductors
Product specification
Hi-fi stereo audio processor; I2C bus
PACKAGE OUTLINE
handbook, plastic dual in-line package; 28 leads (600 mil) DIP28: full pagewidth
TDA8421
SOT117-1
seating plane
D
ME
A2
A
L
A1 c Z e b1 b 28 15 MH w M (e 1)
pin 1 index E
1
14
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 5.1 0.20 A1 min. 0.51 0.020 A2 max. 4.0 0.16 b 1.7 1.3 0.066 0.051 b1 0.53 0.38 0.020 0.014 c 0.32 0.23 0.013 0.009 D (1) 36.0 35.0 1.41 1.34 E (1) 14.1 13.7 0.56 0.54 e 2.54 0.10 e1 15.24 0.60 L 3.9 3.4 0.15 0.13 ME 15.80 15.24 0.62 0.60 MH 17.15 15.90 0.68 0.63 w 0.25 0.01 Z (1) max. 1.7 0.067
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT117-1 REFERENCES IEC 051G05 JEDEC MO-015AH EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-01-14
May 1988
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Philips Semiconductors
Product specification
Hi-fi stereo audio processor; I2C bus
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Soldering by dipping or by wave The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA8421
with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Repairing soldered joints Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds.
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
May 1988
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