Text preview for : b_jg.pdf part of panasonic b jg panasonic LCD TH-37PE30B Viewing SGML_VIEW_DATA ALL TH-37PE30B SVC b_jg.pdf



Back to : b_jg.pdf | Home

JG PC/SD Card Interface IC6013
XCD CARD IN NO CARD RDY/BSY
IC6010 SD CARD
MCU(JPEG)
(10-11) OPEN CLOSE REG
BUFFER I/F
SD
WP WRITE ENABLE WRITE ABLE NO CARD BVD1 IC6015
CARD
JG2 (12-11) DA,ENCODER
SLOT CLOSE OPEN CLOSE
JG3 TO DG10
3.3V 4 SD3.3V Y0 Y7 YD0
Y Q6001,Q6008 15 Y
CMD 2 SDCENA YC YD7
OUT C0 C7 CD0
CLK 5 IC6001 C Q6003,Q6010 19 C

INVERTER CD7
DAT0 7 RST
GPIO
XCD 10 SDCD
ENC RST
11 IC6001
AND GATE
WP 12 SDWP
1 TXD
RXD
D3.3V
PCCENA
PC
CARD
JG1
IC6003 TXD 3 RXD
SLOT
BUFFER
D3 D7 2 6 SYSIDO 5 IDO
D0 D15 DATA D0 D15 DATA BUS FD0
D0 D2 30 32 DATA
MRESET Q6005,Q6006 9 RST
FD15 BUS
D11 D15 37 41


D8 D10 64 66
OE
IC6012
OE 8M FLASH IC6018
RESET
IC6006,IC6008 SYSRST
BUFFER
SYSRST
A10 8
A1 A10 ADDRESS A1 A10 ADDRESS BUS
FA0 ADDRESS
A9, A8 11 12
BUS
FA19
A7 A0 22 29


OE


IC6005 IC6001
INVERTER AND GATE
IORD,FOE
CD1 36
CE1,CE2
CD2 67

IC6018
OE IC6002
128M SDRAM
OR GATE
IC6009 CD1
SDRAM
CD2
BUFFER I/F
CONTROL REG,RESET,IOWR,IORD,PWE,FOE,CE1,CE2


CONTROL SIGNAL

PC CARD
OE I/F


IC6007
BUFFER

CONTROL WAIT,RDYBSY,WP,BVD1,BVD2,INPACK


CONTROL SIGNAL


OE


TH-37PE30B/TH-42PE30B TH-37PE30B/TH-42PE30B
JG-Board Block Diagram JG-Board Block Diagram