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SA-PTX7EB / SA-PTX7EG




1 2 3 4 5 6 7




A
SCHEMATIC DIAGRAM - 6

A DVD MODULE (FPGA) CIRCUIT :+B SIGNAL LINE : DVD VIDEO SIGNAL LINE : DIGITAL AUDIO SIGNAL LIN



DA D+2R5V

DV D+3R3V



IC3000
B C1ZBZ0003207
LB3001 FL3002 FIELD PROGRAMMABLE
J0JJC0000003 F1J1A1050021 GATE ARRAY
DV NSW1R2V D4 VCCINT GND A1
C3003 0.1
D13 VCCINT GND A16
E5 VCCINT GND B9
C3004 0.1
E12 VCCINT GND F6
M5 VCCINT(+1.2V) GND F11
C3005 0.1
M12 VCCINT(+1.2V) GND G7
LB3002 N4 VCCINT(+1.2V) GND G8
C3006 0.1
J0JJC0000003 N13 VCCINT(+1.2V) GND G9
A6 VCCAUX(+2.5V) GND G10
C3007 0.1
FL59005 A11 VCCAUX(+2.5V) GND H2
F1J1A1050021 F1 H7
VCCAUX(+2.5V) GND
C C3008 0.1
F16 VCCAUX(+2.5V) GND H8
L1 VCCAUX(+2.5V) GND H9
C3009 0.1
L16 VCCAUX(+2.5V) GND H10
T6 VCCAUX(+2.5V) GND J7
LB3003 C3010 0.1
J0JJC0000003 T11 VCCAUX(+2.5V) GND J8
B5 VCCO_0(+3.3V) GND J9
FL3001 B12 J10
VCCO_0(+3.3V) GND
F1J1A1050021 C3011 0.1
E2 VCCO_3(+3.3V) GND J15
E15 VCCO_1(+3.3V) GND K7
F7 VCCO_0(+3.3V) GND K8
C3012 0.1
F10 VCCO_0(+3.3V) GND K9
G6 VCCO_3(+3.3V) GND K10
C3013 0.1
D G11 VCCO_1(+3.3V) GND L6
K6 VCCO_3(+3.3V) GND L11
K11 VCCO_1(+3.3V) GND R8
C3014 0.1
L7 VCCO_2(+3.3V) GND T1
L10 VCCO_2(+3.3V) GND T16
C3015 0.1
M2 VCCO_3(+3.3V)
M15 VCCO_1(+3.3V)
R5 VCCO_2(+3.3V)
C3016 0.1
R12 VCCO_2(+3.3V)




4.7K

4.7K


4.7K

4.7K

4.7K

4.7K
E
R3011
4.7K




DV DGND
R3012

R3153

R3013

R3014

R3015

R3047
DV SRCK
DV LRCK
DV DMIXOUT
DV DV5_ON




DV SBT3
F DV SBO3
FPGA_INIT
FPGA_DONE
PROGRAM
CONFIG_TX

CONFIG_CLK



FPGA_MEM0

SH_SCRRXD1
SH_SCRTXD1
SH_SCRCE

SH_SCRCLK1

NT_PAL_IN
NT_PAL_OUT
LCD_DON
LCDFLM
LCDCL1

LCDCL2

LCD_CLK


LCDD15
LCDD14
LCDD13
LCDD12
LCDD11
LCDD10
LCDD9
LCDD8
LCDD7
LCDD6
LCDD5
LCDD4
LCDD3
LCDD2
LCDD1
LCDD0




DV FPGACS
22
22
22
22




DV R_DATA
DV VCLK
R3178
R3177
R3176
R3175




DV VOUT0
DV VOUT1
J0JCC0000103

J0JCC0000103




DV VOUT2
22
22
22

22




DV VOUT3
LB3105


LB3104




DV VOUT4
DV VOUT5
R3004
R3003
R3002

R3001




DV VOUT6
R3180
DV VOUT7 1K
G DV NRST
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
R3182




DGND
NC
DV5_ON
DMIXOUT
LRCK
SRCK
DGND
FPGA_INIT
FPGA_DONE
PROGRAM
CONFIG_TX
DGND
CONFIG_CLK
DGND
CONFIG_RX
FPGA_MEM0
DGND
SH_SCRRXD1
SH_SCRTXD1
SH_SCRCE
DGND
SH_SCRCLK
DGND
NT_PL_IN
NT_PL_OUT
LCD_DON
LCD_FLM
LCD_CL1
DGND
LCD_CL2
DGND
LCDCLK
DGND
LCDD15
LCDD14
LCDD13
LCDD12
LCDD11
LCDD10
LCDD9
LCDD8
LCDD7
LCDD6
LCDD5
LCDD4
LCDD3
LCDD2
LCDD1
LCDD0
DGND
470




P3007
1




50




H TO B
DIGITAL CIRCUIT
(CN1503)
IN SCHEMATIC - 14


1 2 3 4 5 6 7



124
8 9 10 11 12 13 14




L AUDIO SIGNAL LINE



A108

A109
6.3V47
C3111




A110




IC3000
C1ZBZ0003207 CLK_VCXO_54 N8

FIELD PROGRAMMABLE FLDFLG_DV5 B11
GATE ARRAY HBLK_DV5 A10
N9 CLK_VCXO_27 HSYNC_DV5 E10
C8 PDOUT VSYNC_DV5 E8 DV: DVD MODULE (DV5): SCHEMATIC DIAGRAM 1 - 4
P14 VS0 PDOK J2 HD: DVD MODULE (HDMI): SCHEMATIC DIAGRAM - 5
R13 VS1 RSTOUT C5 FP: DVD MODULE (FPGA): SCHEMATIC DIAGRAM 6 - 7
T13 VS2 SW_DSEL<0> H16 DA: DVD MODULE (VIDEO DAC): SCHEMATIC DIAGRAM - 8
B3 HSWAP SW_DSEL<1> H13
L9 M0 VS_DBG A7
T10 M1 HS_DBG C7
R9 M2 FLD_DBG N6
SH_SCRCLK1 R3016 100
B8 CLK_CPU_SH TESTO_CLK27 E4
SH_SCRCE R3017 100 A113
D5 CS_SH TESTO_CLK54 F4
SH_SCRTXD1 R3018 100
D6 SERI_DATA_SH DUMMY_IN N3
SH_SCRRXD1 R3019 22
C6 SERI_O_SH DATA_O_R656<0> M14
FPGA_MEM0
4.7K




R3020 22
F8 FIFO_EMP DATA_O_R656<1> H11
E11 FIFO_FULL DATA_O_R656<2> M16
NRST R3022 22
M3 XRST DATA_O_R656<3> P16
R3047




LCD_CLK R3023 22
D11 DOT_CLK_O_SH DATA_O_R656<4> K14
LCDCL2 R3024 22
A8 DOT_CLK_SH DATA_O_R656<5> L3
LCDCL1 R3025 22 C3001 1000P H1 HSYNC_SH DATA_O_R656<6> G16
LCDFLM R3026 22 TO DVD MODULE (FPGA)
B6 VSYNC_SH DATA_O_R656<7> K16
NT_PAL_OUT R3043 100 SECTION (2/2)
T2 NTSC_PAL_IN TESTOUT1<0> J3
NT_PAL_IN
N14 NTSC_PAL_OUT TESTOUT1<1> G2
LCD_DON R3027 22 C3113 1000P C13 LCD_DON TESTOUT1<2> J5
LCDD0 R3028 22
C9 IMG_DATA_SH<0> TESTOUT1<3> G3
LCDD1 R3029 22
C12 IMG_DATA_SH<1> TESTOUT1<4> H4
LCDD2 R3030 22
L14 IMG_DATA_SH<2> TESTOUT1<5> G5
LCDD3 R3031 22
E14 IMG_DATA_SH<3> TESTOUT1<6> H3
LCDD4 R3032 22
M13 IMG_DATA_SH<4> TESTOUT1<7> H6
LCDD5 R3033 22
B10 IMG_DATA_SH<5> TESTOUT2<0> L2
LCDD6 R3034 22
L15 IMG_DATA_SH<6> TESTOUT2<1> J4
LCDD7 R3045 22
L12 IMG_DATA_SH<7> TESTOUT2<2> P1
LCDD8 R3046 22
E16 IMG_DATA_SH<8> TESTOUT2<3> K1
R3179
100K




LCDD9 R3035 22
J13 IMG_DATA_SH<9> TESTOUT2<4> R4
LCDD10 R3036 22
D12 IMG_DATA_SH<10> TESTOUT2<5> K2
LCDD11 R3037 22
K12 IMG_DATA_SH<11> TESTOUT2<6> P2
LCDD12 R3038 22
A13 IMG_DATA_SH<12> TESTOUT2<7> K3
LCDD13 R3039 22
C10 IMG_DATA_SH<13> TESTOUT3<0> N16
LCDD14 R3040 22
H14 IMG_DATA_SH<14> TESTOUT3<1> H12
LCDD15 R3041 22
J14 IMG_DATA_SH<15> TESTOUT3<2> L13
SBT3 R3115 100
M11 CLK_CPU_DV5 TESTOUT3<3> P15
SBO3 R3116 100
N11 SERI_DATA_DV5 TESTOUT3<4> K15
FPGACS R3042 100
T14 CS_DV5 TESTOUT3<5> J16
R_DATA R3117 22
R11 SERI_O_DV5 TESTOUT3<6> F14
VCLK R3125 22
D8 CLKIN_54 TESTOUT3<7> T5
VOUT0 R3126 22
J11 DATAIN_DV5<0> TESTOUT4<0> B2
VOUT1 R3118 22
G15 DATAIN_DV5<1> TESTOUT4<1> B14
VOUT2 R3119 22
G14 DATAIN_DV5<2> TESTOUT4<2> E9
VOUT3 R3120 22
J12 DATAIN_DV5<3> TESTOUT4<3> D10
VOUT4 R3121 22
F15 DATAIN_DV5<4> TESTOUT4<4> A9
VOUT5 R3122 22 1/2 2/2
G13 DATAIN_DV5<5> TESTOUT4<5> F9
VOUT6 R3123 22
F12 DATAIN_DV5<6> TESTOUT4<6> G4
VOUT7 R3124 22
F13 DATAIN_DV5<7> TESTOUT4<7> D9 SA-PTX7EB/EG
DVD MODULE (FPGA) CIRCUIT


8 9 10 11 12 13 14



124
A113
A110
A109
A108




15
15




DV
OSC27M
33
R3167




16
16




SECTION (1/2)




10K
R3165
TO DVD MODULE (FPGA)
SCHEMATIC DIAGRAM - 7

R3166
10K

R3163 4.7K




17
17




R3132 4.7K
R3161 0




R3134
R3135 330




100
R3138 4.7K
R3054 0 R3137 4.7K
R3136 4.7K




G12
D3
P4
M9
R14
T15
A15
N5
B15




18
18




A DVD MODULE (FPGA) CIRCUIT




IC3000
C1ZBZ0003207
FIELD PROGRAMMABLE
GATE ARRAY
1COUT7
LB3004




A14 DATA_O_DACC<7> NC_IO T9
1COUT6
J0JJC0000003




B7 DATA_O_DACC<6> NC_IO R1
1COUT5 A5 DATA_O_DACC<5> NC_IO D15
1COUT4 D1 DATA_O_DACC<4> NC_IO C16
1COUT3 E1 DATA_O_DACC<3> NC_IO C15
1COUT2 M10 DATA_O_DACC<2> NC_IO C11
1COUT1 E7 DATA_O_DACC<1> NC_I T12
FL3003




1COUT0 C1 DATA_O_DACC<0> NC_I T7
1VOUT7




19
19




DATA_O_DACY<7>
F1J1A1050021




C2 NC_I T3
:+B SIGNAL LINE




1VOUT6 C4 DATA_O_DACY<6> NC_I R7
1VOUT5 A4 DATA_O_DACY<5> NC_I C14 R3053 0
R3
1VOUT4 D7 DATA_O_DACY<4> NC_I A2 R3052 0
K13
1VOUT3 E3 DATA_O_DACY<3> NC_I M7
R3145
C3020
C3019
C3018




1VOUT2 B4 DATA_O_DACY<2> NC_I K4
0.1




1VOUT1
C3017




F5 DATA_O_DACY<1> NC_I J6
1VOUT0
0.1
0.1
0.1




B1 DATA_O_DACY<0> NC_I
4.7K




G1
1CVBS7 L5 DATA_O_CVBS<7> NC_I F2
1CVBS6 K5 DATA_O_CVBS<6> NC_I E13
1CVBS5 M1 DATA_O_CVBS<5> NC_I E6




R3159
1CVBS4 N1 DATA_O_CVBS<4> NC_I D16




20
20




1CVBS3 N2 DATA_O_CVBS<3> NC_I B13




0
1CVBS2 T4 DATA_O_CVBS<2> NC_I D2 C3021
1CVBS1 DATA_O_CVBS<1> NC_I 0.1
L4 A12
1CVBS0 DATA_O_CVBS<0> NC_I
M4 B16
1P_BLANC
P10 FLD422 NC_I A3
1P_VSYNC
: DVD VIDEO SIGNAL LINE




R10 VSYNC422 DUMMY<10> R15
1P_HSYNC
P6 HSYNC422 DUMMY<9> N15
1CLKIN_B
N12 CLK_O_DAC DUMMY<8> C3
1CLKIN_A
F3 CLK_O_CVBS DUMMY<7> M6
1D7 DATA_O_HDMI<7> DUMMY<6>
P7 H5
1D6 DATA_O_HDMI<6> DUMMY<5>
P8 R2
1D5 DATA_O_HDMI<5> DUMMY<4>
J1 H15
1D4




21
21




M8 DATA_O_HDMI<4> DUMMY<3> P13
1D3 DATA_O_HDMI<3> DUMMY<2>
T8 N10
1D2 DATA_O_HDMI<2> DUMMY<1>
L8 P9
1D1 DATA_O_HDMI<1> DUMMY<0>
R6 P12
1D0 G12
N7 DATA_O_HDMI<0> XRST2 G12
1PCLKIN D3
P11 CLK_O_HDMI PROG_B D3
P4
D14 DUMMY<12> INT_B P4
M9
R16 DUMMY<11> DIN_CNFG M9




125
R14
P5 DOUT_CNFG CCLK R14
R3064
R3066
R3063
R3062
R3065




C14 T15
C14 TDO DONE T15
A2 A15
A2 TDI TCK A15
22
22
22
22
22




N5
: DIGITAL AUDIO SIGNAL LINE




MOSI N5
SA-PTX7EB / SA-PTX7EG




22 23 24 25 26 27 28




A


AUDIO SIGNAL LINE




B
DV: DVD MODULE (DV5): SCHEMATIC DIAGRAM 1 - 4
HD: DVD MODULE (HDMI): SCHEMATIC DIAGRAM - 5
FP: DVD MODULE (FPGA): SCHEMATIC DIAGRAM 6 - 7
DA: DVD MODULE (VIDEO DAC): SCHEMATIC DIAGRAM - 8




1PCLKIN R3067 22
PCLKIN HD

R3068 22
C
1D0
D0 HD
1D1 R3069 22
D1 HD
1D2 R3070 22
D2 HD
1D3 R3071 22
D3 HD
1D4 R3072 22