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Contents
CHANNEL . . . 5-1 Port to Attachment Lines . . . 5-17 I/O Immediate 5-26
INTRODUCTION 5-1 MPXPO Bus Out-Nine Lines 5-17 I/O Load or I/O Control Load (lOL, 10CL) 5-26
DATA FLOW ~ . 5.,.1 Control Out Pwrd-One Line 5-17 I/O Load Instruction 5-27
I/O Instructions . 5-2 Service Out Pwrd-One Une 5-17 I/O Load (Big Picture) , 5-28
Processing Unit Storage Link to I/O Command Bus Out 0, 1, 2-Three Lines 5-17 I/O Load (Detail) 5-30
Attachments. . . . . . . . . . . 5-2 Strobe Pwrd-One Line. . . . . . 5-17 I/O Sense or I/O Control Sense (lOS, 10CS) . 5-32
Control Processor Local Storage Register Transfer Error-One Line . . . . . 5-17 I/O Sense Instruction 5-33
Link to I/O Attachments . . . . . . . 5-2 Disk Burst Mode Gated-One Line . 5-17 I/O Sense (Big Picture) 5-34
Control Processor Jump on I/O Condition Disk Strobe-One Line 5-17 I/O Sense (Detail) . 5-36
Link to I/O Attachments 5-5 CSY Trigger-One Line . . . 5-17 Sense Interrupt Level Status Byte (SILSB) 5-38
PORT CARD 5..;6 Attachment to Port Lines . . . 5-18 Sense Interrupt Level Status Byte (Big
Port Parity . . . . . . . . 5-6 MPXPO Data In-Nine Lines 5-18 Picture) , 5-38
Port Clock . . . . . . . . 5-8 Service In-One Line . . . . . . 5-18 Sense Interrupt Level Status Byte (Detail) 5-40
Generation of Port Clock Times . 5-8 Micro.interrupt Request-Five Lines. 5-18 Control Processor Load Function (MPLF) . 5-42
Generation of Port Triggers 5-8 Multidevice Response-One Line 5-18 Control Processor Sense (MPS) . 5-42
Data Buffer . . . . . 5-12 Base Cycle Steal Request-One Line I/O Storage (WTCL, WTCH, RDCL, RDCH,
Port Register . . . . 5-13 (Per Device) . " " . . . . ., , , 5-18 WTM, ROM) . 5-43
Port Checks Register . 5-14 Disk/ Dskt Block Processor Clock-One Line " 5-18 I/O Storage (Load.,....Big Picture) . 5-44
Port Decodes . . . . 5-14 Disk/Dskt (Load) BC Req-One Line . . . . 5-18 I/O Storage (Load-Detail) 5-46
Interrupt/Cycle Steal Priority Control Command Bus In (Bits 0, 1, 2, 3, 4, 5)-Six I/O Storage, (Sense-Big Picture) 5-48
for LSRs . . . . . . . . . . . . 5-14 Lines, . . . . " , . . . . . . . . . 5-18 I/O Storage (Sense-Detail) . 5-50
Command Bus Out Decode 5-15 Direct Lines-Control Processor/Attachments 5-18, Jump on I/O Condition (JIO) . 5-52
CONTROL PROCESSOR/PORT CONTROLS 5-16 Power On Reset-One ,Line . , . , . . . 5-18 Jump on I/O Condition (Big Picture) 5-52
Port to Control Processor Lines . . 5-16 System Reset-One Line . . , . , . . . 5-18 Jump on I/O Condition (Detail) 5-54
System Bus In-Nine Lines . . " 5-16 Control Storage Initial Program Load (CSIPL) ERROR CONDITIONS 5-56
Storage Cycle Request-One Line 5-16 Latch-One Line . . . . . . . . 5-18 Blast Conditions . 5-56
Advance Time-One Line . . . . 5-16 CSIPL Cycle-One Line . . . . . . 5-18 Blast Condition Because of Time-out Check 5-56
Block Proce,ssor Clock (BPC Tgr)-One Line . 5-16 Interface Clock Times-Eight Lines. 5-18 Blast Condition Because Data Bus In Is'
Interrupt/Cycle Steal LSR Decode-Three OPERATIONS. . . . . 5-19 Not Zero 5-57
Lines . . . . . . ~ . . . . 5-16 Burst Cycle Steal Mode 5-19 Blast Condition Because of Assigning the
CBI Bit 4 Gated-One Line,. . . . . 5-16 Disk Support Timing. . 5-19 Wrong Device . 5-58
New Channel Check-One Line . . 5-16 Disk Support Lines . 5-19 Port Checks . 5-59
Proc Interrupt 1, 2, 4-Three Lines. 5-16 Burst Cycle Steal Mode (Operational Check Generation 5-59
I/O Service Request-One Line . . 5-16 Sequence) . . . . . . . . . . . . 5-20 Transfer Error. 5-60
Interrupt Request to Run Latch-One Line 5-16 Base Cycle Steal Mode. . . . . . . . 5-22 Time-out Conditions 5-61
Control Processor to Port Lines 5-16 Base Cycle Steal Mode (Operational Processor Check Halt 5-62
T4 Through T6-0ne Line . . . . . . 5-16 Sequence) . . . . . . . . . 5-22
System Bus Out-Nine Lines . . . . . 5-16 Microinterrupt Level Mode . . . . . . . . . . 5-24
I/O Instrl,lction-One Line 5-16 Channel Exerciser Loop Program 5-24
Phase A-One Line '5-16 COMMANDS . . . . . . . . : . ..... 5-25
Machine Check Interrupt-One Line 5-16
CSY Trigger-One Line . . 5-16
System Reset-One Line 5-16
T7-0ne Line . . . . . 5-16
Lamp Test-One Line 5-16'
PORT / ATTACHMENT CONTROLS 5-17

Contents for Channel
,Channel
INTRODUCTION A-A1L2

The channel contains data buses and
+ System Bus Out
+ I/O Instruction
_9" Port
Control
l1li 9