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A B C D E
MODEL NAME : VBW01
PROJECT CODE : ANRVBW0100
PCB NO : DA8000WL000 LA-9982P M/B
1 DA40001FO00 LS-9101P POWER BUTTON/B 1
DA40001FP00 LS-9102P USB/B
DA40001FQ00 LS-9103P TP BUTTON/B
Dell / Compal Confidential
2 Schematic Document 2
Intel Shark Bay ULT
OAK Mainstream2
UMA/DIS AMD Venus Pro
2013-05-29 Rev: 3.0
3 3
X76@ : 76 level
46@ : 46 level
@ : Nopop component BOM config
CONN@ : Connector component UMA : UMA@,EMI@,ESD@,RF@
XDP@ : XDP function DIS VENUS : VENUS@,VENUSPRO@,DIS@,EMI@,ESD@,RF
UMA@ : Only for UMA ZZZ R1@
DIS@ : Only for Discrete
VENUS@ : VENUS Pro,VENUS XT PCB VBW01 LA9982P/LS9101P/LS9102P/LS9103P
DAZ0ZG00120
VENUSXT@ : VENUS XT
VENUSPRO@ : VENUS Pro
4
@VENUS@ : VENUS nopop component 4
EMI@ : EMI parts
@EMI@ : Reserve EMI parts
ESD@ : ESD parts Compal Secret Data
Security Classification Compal Electronics, Inc.
RF@ : RF parts Issued Date 2013/05/29 Deciphered Date 2014/06/01 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 3.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9982P
Date: Wednesday, May 29, 2013 Sheet 1 of 57
A B C D E
A B C D E
Fan Control CPU XDP
1 128M*16 128M*16 1
GDDR5*8 GDDR5*8
P.27 Conn. P.6
P.34 P.35
64bit Memory Bus (DDR3L) DDRIII-DIMM X2
128M*16 Dual Channel BANK 0, 1, 2, 3, 4 ,5 ,6 ,7
GDDR5*8 AMD P.17~18
1.35V DDR3 1600 MHz
P.36
Venus Pro , 25W PEG 2.0 x4 Intel
128M*16
GDDR5*8
64bit Haswell 8GB Max
P.37 P.28~33
Processor
Venus Pro(HD8850M)2GB GDDR5 (128Mx16x8pcs) 15W DC SATA3.0 Port 0
SATA HDD Conn. P.42
BGA1168
Port 1 SATA ODD Conn. P.42
USB 3.0 Port 1,2
LVDS eDP USB 3.0 Conn. 1
2 LVDS Conn. RTD2136R USB 3.0 Conn. 2 P.24 2
P.41 P.19 Port 0,1
USB2.0
Port 2,3 USB 2.0 Conn. 3
P.25
USB 2.0 Conn. 4 Daughter board
HDMI Port 11
HDMI Conn. Digital Camera
P.20
(With Digital MIC) P.41
Port 8 Mini Card
PCI-E P.26
Intel WLAN (Half)
Port 2 Port 1 Lynx Point-LP Port 10 Card Reader
RTS5179/5170 P.23 3 in 1 Socket P.23
Mini Card Ethernet
Port 9 Touch Screen
WLAN/BT4.0 RTL8106E (OAK 15" only) P.41
Half P.26 P.21
3 3
RJ45 Digital Mic.
P.21
HD Audio Audio Codec Headphone Jack / Mic. Jack combo P.22
SPI ALC3223 Int. Speaker R / L
P.22 P.22
SPI ROM
64M P.9 P6~16
LPC Bus
SMBus
33MHz
ENE KBC PS/2
Int.KBD KB9012 P.40 Touch Pad
P.27 P.27
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/05/29 Deciphered Date 2014/06/01 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block diagram
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
3.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9982P
Date: Wednesday, May 29, 2013 Sheet 2 of 57
A B C D E
A B C D E
Compal Confidential
Project Code : VAW00 / VAW01
File Name : LA-9981P / LA-9982P
1 1
LS-9101P (PWR/B)
UE5
Lid (SA00003VQ00)
SW1 4 pin-Hot Bar
(SN100004Y00)
PBATT
Battery
JMINI PJPDC
PWR-BTN FFC MINI Card
5 pin
4 pin JLVDS
40 pin
JKB
30 pin
2 2
JFAN LS-9102P (USB/B)
3 pin
HDMI
JHDMI JTP
6 pin JODD
JTOUCH JPWR USB JUSB4
6 pin 4 pin
USB-DB FFC
JLAN RJ-45
XDP LA-9981P M/B 8 pin
8 pin
Hot Bar
JXDP
LA-9982P M/B
JUSB1 USB Top Side JHDD
Bottom Side JDB
8 pin
TP-MB FFC
6 pin JUSB2 USB
(OAK 15")
JRTC
2 pin
JUSB3 USB JSPK
3
4 pin JREAD 3
RTC
Card
TP-Module JHP HP Reader
Led1 Led3
Led2 Led4
TP-BTN FFC
4 pin
LS-9103P (TP-BTN/B)
4 pin
Hot Bar
SW2 SW3
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/05/29 Deciphered Date 2014/06/01 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DB block diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
3.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9982P
Date: Wednesday, May 29, 2013 Sheet 3 of 57
A B C D E
A
Board ID Table for AD channel
Vcc 3.3V +/- 1%
Ra 100K +/- 1%
Board ID Rb V AD_BID min V AD_BID typ V AD_BID max EC AD3
0 0 0.000V 0.000V 0.300V 0x00 - 0x0B USB3.0
1 12K +/- 1% 0.347V 0.354V 0.360V 0x0C - 0x1C
2 15K +/- 1% 0.423V 0.430V 0.438V 0x1D - 0x26 Port1 USB connector 2
3 20K +/- 1% 0.541V 0.550V 0.559V 0x27 - 0x30
4 27K +/- 1% 0.691V 0.702V 0.713V 0x31 - 0x3B Port2 USB connector 1
5 33K +/- 1% 0.807V 0.819V 0.831V 0x3C - 0x46
6 43K +/- 1% 0.978V 0.992V 1.006V 0x47 - 0x54 Port3
7 56K +/- 1% 1.169V 1.185V 1.200V 0x55 - 0x64
8 75K +/- 1% 1.398V 1.414V 1.430V 0x65 - 0x76 Port4
9 100K +/- 1% 1.634V 1.650V 1.667V 0x77 - 0x87
10 130K +/- 1% 1.849V 1.865V 1.881V 0x88 - 0x96 USB2.0
11 160K +/- 1% 2.015V 2.031V 2.046V 0x97 - 0xA3
12 200K +/- 1% 2.185V 2.200V 2.215V 0xA4 - 0xAD Port0 USB connector 2
13 240K +/- 1% 2.316V 2.329V 2.343V 0xAE - 0xB7
14 270K +/- 1% 2.395V 2.408V 2.421V 0xB8 - 0xC0 Port1 USB connector 1
15 330K +/- 1% 2.521V 2.533V 2.544V 0xC1 - 0xC9
16 430K +/- 1% 2.667V 2.677V 2.687V 0xCA - 0xD3 Port2 USB connector 3
17 560K +/- 1% 2.791V 2.800V 2.808V 0xD4 - 0xDC
18 750K +/- 1% 2.905V 2.912V 2.919V 0xDD - 0xE6 Port3 USB connector 4 (DB)
19 NC 3.000V 3.300V 3.300V 0xE7 - 0xFF
Port4 MINI Card (WLAN)
SMBUS Control Table
Port5 Touch Screen Panel
SOURCE BATT Charger RTD2136S VGA DDR3L XDP WLAN Touch pad
mini card ULT Port6 Card Reader
EC_SMB_CK1
EC_SMB_DA1
KB9012 V V Port7 Camera
V V
1 1
EC_SMB_CK2 KB9012
EC_SMB_DA2 PCI EXPRESS
SMBCLK
SMBDATA
ULT V V V V Lane 1
Link
SML0CLK ULT
SML0DATA Lane 2
SML1CLK ULT
SML1DATA Lane 3 10/100 LAN
Board ID TABLE Lane 4 MINI Card (WLAN)
PCB Revision
ID UMA Sun XT VenusPro VenusXT
Lane 5 PEG (N14P)
0 SSI&A02
1 SSI&A02 CLOCK SIGNAL
Lane 6 PEG (N14P)
2 SSI&A02
CLKOUT_PCIE0
3 SSI&A02 Symbol Note : SATA
4 PT
5 PT CLKOUT_PCIE1
: means Digital Ground SATA0 HDD
6 PT
7 PT CLKOUT_PCIE2 10/100 LAN
SATA1 ODD
8 ST
9 : means Analog Ground CLKOUT_PCIE3 MINI Card (WLAN)
ST SATA2
10 ST
11 ST CLKOUT_PCIE4 dGPU
SATA3
12 XB
13 XB CLKOUT_PCIE5
14 XB
15 XB
16 A01 Security Classification Compal Secret Data Compal Electronics, Inc.
17 A01 Issued Date 2013/05/29 Deciphered Date 2014/06/01 Title
18 A01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
3.0
19 A01 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9982P
Date: Wednesday, May 29, 2013 Sheet 4 of 57
A
5 4 3 2 1
2.2K 10K
SMBUS Address [0x9a]
2.2K
+3.3V_ALW_PCH 10K
+3VS
N-MOS
AP2 MEM_SMBCLK DDR_XDP_WLAN_TP_SMBCLK 202 DIMMA SMBUS Address [A0]
N-MOS
AH1 MEM_SMBDATA DDR_XDP_WLAN_TP_SMBDAT 200
D D
1K
202 DIMMB
+3.3V_ALW_PCH SMBUS Address [A4]
1K 200
AN1 SML0CLK
MCH 0 ohm
AK1 SML0DATA DDR_XDP_SMBCLK_R1 53 XDP1 SMBUS Address [TBD]
Shark bay 0 ohm
2.2K DDR_XDP_SMBDAT_R1 51
2.2K
+3.3V_ALW_PCH
30 JMINI SMBUS Address [TBD]
N-MOS 32
AN1 SML1_SMBCLK EC_SMB_CK2
N-MOS
AK1 SML1_SMBDATA EC_SMB_DA2
5 JTP SMBUS Address [TBD]
6
2.2K
C 2.2K
+3VALW C
0 ohm N-MOS 0 ohm LVDS
79 EC_SMB_CK2 CSCL CIICSCL 13 UV28 Translator SMBUS Address [TBD]
0 ohm N-MOS 0 ohm
80 EC_SMB_DA2 CSDA CIICSDA 14
2.2K
2.2K
+3VS_VGA
N-MOS
VGA_SMB_CK2 T4 UV28 GPU SMBUS Address [0xXX]
N-MOS
VGA_SMB_DA2 T3
2.2K
2.2K
+3VALW
0 ohm
77 EC_SMB_CK1 SCL 11 PU701 POWER SMBUS Address [0x12]
0 ohm Charger
KBC 78 EC_SMB_DA1 SDA 10
B
KB9012A4 100 ohm
B
3 PD1 4 BAT_ALERT 3 PBATT1 BATT SMBUS Address [0x16]
100 ohm CONN
1 6 BATT_PRS 5
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/05/29 2014/06/01 Title
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SMBus block diagram
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
3.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9982P
Date: Wednesday, May 29, 2013 Sheet 5 of 57
5 4 3 2 1
5 4 3 2 1
i3-4010U-15W-GT2-MP
UC1 4010Ui3G2R1@ UC1 4010Ui3G2R3@
CL8064701478202 SR16Q C1 1.7G BGA CL8064701478202 SR16Q C1 1.7G A31!
HASWELL_MCP_E
SA00006SX1L SA00006SX2L UC1A
i5-4200U-15W-GT2-MP C54 C45
DDI1_LANE_N0 EDP_CPU_LANE_N0
<20> DDI1_LANE_N0 DDI1_LANE_P0 C55 DDI1_TXN0 EDP_TXN0 B46 EDP_CPU_LANE_P0 EDP_CPU_LANE_N0 <19>
D <20> DDI1_LANE_P0 B58 DDI1_TXP0 EDP_TXP0 A47 EDP_CPU_LANE_P0 <19> D
UC1 4200Ui5G2R1@ UC1 4200Ui5G2R3@ DDI1_LANE_N1 EDP_CPU_LANE_N1
<20> DDI1_LANE_N1 DDI1_LANE_P1 C58 DDI1_TXN1 EDP_TXN1 B47 EDP_CPU_LANE_P1 EDP_CPU_LANE_N1 <19>
<20> DDI1_LANE_P1 B55 DDI1_TXP1 EDP_TXP1 EDP_CPU_LANE_P1 <19>
DDI1_LANE_N2
<20> DDI1_LANE_N2 DDI1_TXN2
DDI1_LANE_P2 A55 C47
<20> DDI1_LANE_P2 DDI1_LANE_N3 A57 DDI1_TXP2 EDP_TXN2 C46
<20> DDI1_LANE_N3
DDI1_LANE_P3 B57 DDI1_TXN3 EDP_TXP2 A49 COMPENSATION PU FOR eDP
<20> DDI1_LANE_P3 DDI1_TXP3 DDI EDP EDP_TXN3 B49
CL8064701477702 SR170 C1 1.6G BGA CL8064701477702 SR170 C1 1.6G A31! EDP_TXP3
C51
C50 DDI2_TXN0 A45 EDP_CPU_AUX# +VCCIOA_OUT
SA00006SM2L SA00006SM3L DDI2_TXP0 EDP_AUXN EDP_CPU_AUX# <19>
C53 B45 EDP_CPU_AUX
DDI2_TXN1 EDP_AUXP EDP_CPU_AUX <19>
B54
C49 DDI2_TXP1 D20 EDP_COMP 2 1
i7-4500U-15W-GT2-MP