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Contents
CONTROLPROCESSOR. 2-1 Logical/Arithmetic 1 (XR, ZAR, OR, NCR, NR, Arithmetic and Logic Units . . . . . . . 2-110
DATA FLOW AND CLOCKS 2-1 OCR, DEC, ACYR, SR, AR, SCYR, INC) . . 2-42 Arithmetic and Logic Unit G,ates 2-111
Data Flow 2-1 Condition Code for Logical Operations . . 2-42 Arithmetic and Logic Unit Parity Predict 2-111
Clocks . . . . . . . . . . 2-3 Condition Code for Arithmetic Operations 2-42 Storage Data Register . . . 2-112
System . . . . . . . . 2-3 Logical/ Arithmetic Functions . . . . . . 2-43 Local Storage Registers 2-113
I/O Attachment and Controller 2-4 Logical/Arithmetic 2 (XR, ZAR, OR, NCR, NR, Processor Condition Register 2-114
Storage : . . . . . . . 2-4 OCR, DEC, ACYR, SR, AR, SCYR, INC) . . 2-46 Storage Gate High/Low 2-116
OPERATIONS . . . . . . . . . 2-5 Condition Code for Logical Operations. . 2-46 Status 1 Gate . . . . 2-117
IPL-Customer User Programs . . 2-5 Condition Code for Arithmetic Operations 2-46 Status 2 Gate . . . . . 2-118
Control Storage Initial Program Load (CSIPL) 2-5 Logical/ Arithmetic Functions 2-47 ERROR CONDITIONS . 2-119
Main Storage Initial Program Load (MSIPL)" 2-6 Load Immediate (L1) . . . . . . . . . . . 2-50 Control Processor Checks 2-119
IPL Timing Sequence . . . . . 2-7 Compare Immediate (CI) . . . . . . . . . 2-52 Processor Errors 2-119
Display Light Sequence (Byte 0) 2-7 Subtract Immediate/ Add Immediate (SI, AI) 2-54 Error Conditions (Second Level) 2-119
Disk Operation . . 2-8 Test Mask (TM) . 2-56 Machine Check Interrupt and Processor
Disk Sequence . . 2-9 Set Bits On (SBN) . . . . . 2-58 Check Generation 2-120
62EH Disk Timing . 2-11 Set Bits Off (SBF) . . . . . 2-60 MSP Hardware Checks 2-121
62PC Disk Timing . 2-12 Storage (LC, LM, STC, STM) 2-63 Control Processor Checks . . 2-122
IPL-Customer SSP from Diskettes. 2-13 Instruction List . . . . . 2-63 SDR Parity Check Generation . 2-123
IPL-CE Diagnostics . . . . . . . 2-15 Main Storage Access by Control MOR Parity Check . . . . . 2-124
Diskette CSIPL Diagnostic Sequence. 2-17 Processor . . . . . . . . . . 2-66 Storage Gate High/Low Parity Check
Diskette Timing (Level 1 Attachment) 2-18 Control Processor Control of MSAR 2-67 and Generation . . . . . . . 2-125
33FD/53FD CSIPL Flowchart (Level 1 MSP Bus Line Control . . . . . 2-68 ALU Gate High Parity Check and
Attachment) . . . . . . . . . . . 2-19 Main Storage Address Decoding 2-69 Generation . . . . . . . . . 2-126
Diskette Timing (Level 2 Attachment) 2-21 Register Control (WMPR, RMPR) 2-73 ALU Gate Low Parity Check and
33FD/53FD/72MD CSIPL Flowchart (Level Instruction List . . . . . . . . 2-73 Generation . . . . . . . . . 2-127
2 Attachment) . . . 2-22 Storage Direct (L, ST) . . . . . . 2-76 Control Storage SAR Parity Check 2-128
Error Indications 2-24 Move Local Storage Register (MVR) 2-78 MSP Check Bits 1 and 2. . . . . 2-129
CSI PL Switch Options 2-27 Hexadecimal Branch (HBN, HBZ) 2-80
Instructions . . . . . . 2-28 Hexadecimal Move (SRL, SRLD, MZZ, MZN) 2-82
Instruction Times . . . 2-28 I/O Immediate . . . . . . . . . . . . . 2-88
Sequence and Timing 2-28 I/O Load or I/O Control Load (lOL, IOCL) 2-94
Routine Printout . . . . 2-29 I/O Sense or I/O Control Sense (lOS, 10CS) . 2-96
Mnemonic Listing . . . 2-30 Sense Interrupt Level Status Byte (SILSB) 2-98
INSTRUCTION EXECUTION 2-32 Control Processor Load Function (MPLF) . 2-99
Signals, Gating Lines, and Logical Functions for Control Processor Sense (M PS) . . . . 2-99
Timing Charts . . . . . 2-32 I/O Storage (WTCL, WTCH, RDCL, RDCH,
Branch (B) . . . . . . . 2-34 WTM, RDM) . . . . . . . 2-100
Branch (Stop Condition) (B) 2-35 Instruction List . . . . . 2-100
Branch and Link (BAL) . . 2-36 Jump on I/O Condition (JIO) 2-104
Jump on Condition (JC) 2-38 FUNCTIONAL UNITS 2-108
Jump on Condition (Stop Condition) (JC) 2-40 Control Storage . . . . . 2-109
Storage Address Register . 2-109
Micro-Operation Register. 2-109
X-Registers and V-Registers 2-109




Contents for Control Processor
Control Processor
The control processor is made up of eight cards DATA FLOW AND CLOCKS Default Conditions
(16K-word storage positions that can be
addressed): six cards for the processor and two If no hardware conditions are specified for the
cards for storage. The control processor: Data Flow control processor, the control processor has
automatic selections and functions that are
-