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HyperTransport Technology Consortium
HyperTransportTM I/O
Link Specification
Revision 1.10
Document #
HTC2001021-0009-0022
8/25/2003
Copyright 2001, 2002, 2003 HyperTransport Technology Consortium
HyperTransport Technology Consortium
The HyperTransport Technology Consortium disclaims all warranties and liability for the use of this
document and the information contained herein and assumes no responsibility for any errors that may
appear in this document, nor does the HyperTransport Technology Consortium make a commitment to
update the information contained herein.
DISCLAMER
This document is provided "AS IS" with no warranties whatsoever, including any warranty of
merchantability, non-infringement, fitness for any particular purpose, or any warranty otherwise arising
out of any proposal, specification or sample. The HyperTransport Technology Consortium disclaims all
liability for infringement of property rights relating to the use of information in this document. No license,
express, implied, by estoppels, or otherwise, to any intellectual property rights is granted herein.
TRADEMARKS
HyperTransport is a licensed trademark of the HyperTransport Technology Consortium.
Other product names used in this publication are for identification purposes only and may be trademarks of
their respective companies.
Copyright 2001, 2002, 2003 HyperTransport Technology Consortium
HyperTransport Technology Consortium
About HyperTransportTM Technology
HyperTransport technology is a high-speed, high-performance, point-to-point link for integrated circuits, and is
designed to meet the bandwidth needs of tomorrow's computing and communications platforms. HyperTransport
technology helps reduce the number of buses while providing a high-performance link for PCs, workstations, and
servers, as well as numerous embedded applications and highly scalable multiprocessing systems. It is designed to
allow chips inside of PCs, networking and communications devices to communicate with each other up to 48 times
faster than with some existing bus technologies.
About the HyperTransport Technology Consortium
The HyperTransport Technology Consortium is a nonprofit corporation managed by its members. The consortium
promotes the common business interests of providers to the networking, telecommunications, computer and high-
performance embedded application through the conduct of a forum for the future development and adoption of the
HyperTransport specification.
AMD, Apple Computers, Broadcom, Cisco Systems, NVIDIA, PMC-Sierra, SGI, SiPackets, Sun Microsystems, and
Transmeta are the charter members that comprise the Executive Committee of the HyperTransport Technology
Consortium.
Companies interested in the HyperTransport specification are invited to join the consortium. Members of the
consortium pay annual dues and receive a royalty-free license to HyperTransport IP, gain access to technical
documentation and may attend consortium meetings and events. To become a member, visit the consortium Web site
at www.hypertransport.org. Please review the Bylaws of the HyperTransport Technology Consortium, and complete
the online membership application.
The HyperTransport Consortium, HyperTransport Technology and combinations thereof are trademarks of
HyperTransport Consortium.
Copyright 2001, 2002, 2003 HyperTransport Technology Consortium
HyperTransport Technology Consortium
REVISION CHANGE SECTION DATE
1.03 Initial release All 10/10/01
1.04 Fixed errata and made clarifications All 5/30/02
Fully defined open-drain signal behavior 2, 15, 18.5
Document Isochronous VC limitations 4.4.3, 4.4.4,
7.5.4.9, D.1
Allow RMW with count other than 1 or 3 4.4.5
Relaxed response UnitID for rejected packets 4.9.3
Updated upstream configuration requirements 4.9.4, F
Swapped Interrupt and Address chapters (5 and 9) 5, 9
Added new x86 reserved address range 5
Tighten Config and I/O space access requirements 5, B
Highlighted required registers 7.3-7.5
Expanded description of Address registers 7.3.5, 7.4.6
ISA and VGA enable bits required and documented 7.4.9.3
Require a revision ID in every function 7.5
Extend HyperTransport Capability Type field to 5 bits 7.5.3.1, 7.7.1
Documented behavior of multiple nonprefetchable 7.5.13
memory range register extensions
Added Isochronous, NonCoherent, and Compat bits to 7.7
Address Remapping Block
Created Revision ID Capability 7.8
Documented reset data corruption case 10.1
Documented behavior when all UnitIDs are consumed 12.3
Combined Appendices B and C B
Relaxed PCI ordering, added HyperTransport to PCI B.2
command mapping
Added PCI-X ordering rules and command mapping B.4
Added Deadlock Appendix C C
Document legacy interrupt boot requirements F.1
Document legacy PIC multiple ExtInt requirements F.1.3
Document delay from STOP_GRANT to LDTSTOP# F.2
Document A20M ordering requirements F.2.1.1
Updated LDTREQ# requirements F.2.4
Updated differential signal input edge rate 18.10
requirements
Copyright 2001, 2002, 2003 HyperTransport Technology Consortium
HyperTransport Technology Consortium
REVISION CHANGE SECTION DATE
1.05 Added 64-bit addressing 3.2.1, 4.4.6, 5, 11/22/02
7.3.5, 7.4.6,
7.5.4.12, 7.5.8,
7.5.10.5, 10.1.5
Changed Coherent bit from Ignored to Reserved and 3.2.1.5, 4.4.1
set
Added Data Error to Responses and Posted Writes, 4.4.1, 4.5, 7.3,
Changed Error and NXA bits in Responses to Error0/1 7.4, 10.2.1,
B.2.2, B.4.2
Added Isoc bit to Flush and Fence 4.4.3, 4.4.4, D.1
Added UnitID Clumping 4.2, 4.5, 4.6, 4.9,
6.4, 7.5.10, 7.10,
12.3
Various clarifications 3.2.1, 4.7, 4.9, 5,
6.1, 7.1, 8.3,
12.2, B.2.2,
B.4.2, C.1.2
Require peer-to-peer reflection of Atomic RMW 4.4.5
Added Extended Configuration Space and Device 4.4.1, 4.9, 5, 7.1,
Messaging 7.2, 7.5.15, 7.11,
13, B.4.2, F
Restricted ordering within the chain 6, 6.1
Added Interrupt Disable and Status bits 7.3.1.6, 7.3.2.1
Removed VGA Palette Snoop 7.4.1
Added Upstream Configuration Enable bit 7.5.10.8
Added 64-bit Address Remapping 7.8
Added INTA/B/C/D Virtual Wires 8.1, 8.4
Added No Snoop to HyperTransport-to-PCI-X B.4.2
Mapping
Added Message Signaled Interrupt Mapping B.5
Added x86 Thermal Management Messages F.2.1
Relaxed x86 SMI and SMIACK Requirements F.2.5
Added Switch Appendix 7.5.3.1, I
Combined First Two Electrical Chapters 15
Copyright 2001, 2002, 2003 HyperTransport Technology Consortium
HyperTransport Technology Consortium
REVISION CHANGE SECTION DATE
1.10 Incorporated All 1.05c Errata 3.2.3, 4.4.1, 4.4.5, 4.8.1, 4.9.5.2, 5, 6, 8/25/03
6.1, 6.2, 7.3.1.4, 7.3.2.3, 7.3.2.8, 7.4.1,
7.4.9, 7.5.3.1, 7.5.4, 7.5.5, 7.5.6, 7.5.7,
7.5.8.3, 7.5.10.6, 7.5.12, 7.5.13, 7.5.14,
7.10.2, 7.12, 8.1, 8.3, 8.5, 9.1, 10.1.1,
10.1.3, 10.1.5, 10.2.2, 10.2.4, 12.2, B.2.2,
B.4.2, B.5, F.1.1, F.2.1, I.3.3.5, J, 18.7,
M.9
Added Retry Mode 2, 3.1, 4.8, 7.5.3.1,
7.5.4.8, 7.15, 10.1.3,
10.3, H
Added New Virtual Channel Sets 3.2.1, 4.4.1, 4.5, 4.7,
4.8.2, 4.9.7, 6.1,
7.5.3.1, 7.14, 10.1.5
Added DirectRoute Peer-to-Peer Routing 4.1, 4.2, 4.9, 6,
7.5.3.1, 7.5.3.2.4, 7.13
Added Streaming Packets 14
Added End-to-End Flow Control K
Various Editorial and Typographical Corrections All
Copyright 2001, 2002, 2003 HyperTransport Technology Consortium
HyperTransport Technology Consortium
HyperTransportTM I/O Link Specification Revision 1.10
Contents
List of Figures...............................................................................................................................20
List of Tables ................................................................................................................................22
Preface...........................................................................................................................................27
This Document ..........................................................................................................................27
Organization..............................................................................................................................27
Section 1