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A B C D E

1 1

Compal confidential
2 2

Liverpool 10AR/10ARG
KSWAE LA-4971P Schematics Document
Mobile AMD S1G2 S1G3/
RS780MN & RS780MC & RX781 & RS880 /
3
SB700 & SB710 3

2009-02-09 Rev. 0.3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008-09-25 Deciphered Date 2009-09-25 Title
Cover Sheet
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-4971P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 25, 2009 Sheet 1 of 45
A B C D E
A B C D E

Compal Confidential A M D S1 G 2 C PU T he rm a l Se n s o r F a n C o n tro l
M o de l N a m e : K SW A E
A T I M 9 2/ 9 6
F ile N a m e : L A - 4 9 7 1 P uFCPGA-638 Package ADM1032ARMZ page 6 APL5607KI-TRG page 4

G r iffin P la t fo r m with VRAM
page 4,5,6,7
H y p e r T r a n s p o r t L i n k 2 .6 G H z
1 1
1 6X 1 6
V G A M X M C o n n 2 0 0 p in D D R II- S O - D IM M X 2
A T I
BANK 0, 1, 2, 3 page 8,9
Page 19
M e m o r y B U S (D D R II)
RS780MN D u a l C ha n n e l
C R T
RS780MC 1 .8 V D D R I I 6 6 7 / 8 0 0 M H Z
page 16
RX781
L C D C o n n .
RS880
page 17
H D M I C E C C o n t r o lle r H D M I C o n n .

EC SMBUS
R5F211A4SP page 18 page 18

2
PCIe 4x 1.5V 2.5GHz(250MB/s) page 10,11,12,13,14 2

A - L in k E x p r e s s II
4 X P C I- E
R ig h t U S B C o n n In t . C a m e r a B lu e t o o t h

A T I USB Port 0,1 page 32 USBPort 9 page 32 USBPort 6 page 32

R T L 81 03 E L L A N 1 0/ 1 00M P C Ie M in i C a r d W L A N N E W C a rd
SB700 USB 5x
USB 5V 480MHz SB710
USB port 11
PCIe port 3 page 26 PCIe Port 2 page 27 5V 480MHz
PCIe port 0 page 27
W L A N F in g e r P r in t e r R T S5 1 5 9 E
R J 45 e SA T A SATA 5V 1.5GHz(150MB/s)
3IN1
3IN1
USBPort 8 page 27 USBPort 7 page 27 USBPort 4 page 29 page 29
page 26 USB port 2
USB 5V 480MHz
SATA port 2 page 25
SA T A H D D 1
SATA
PCI BUS 3.3V 33 MHz
SATA port 0 page 25
3 C a r d B u s C o n t r o lle r 5V 1.5GHz(150MB/s) SA T A O D D 3

SATA
C lo c k G e n e r a t o r USB / B OZ601 page 28 page 20,21,22,23,24 SATA port 3 page 25
5V 1.5GHz(150MB/s)
SLG8SP626VTR page 15 page 32 LPC BUS 3.3V 33 MHz

R T C C K T . Po w e r/ B
D e bu g Po rt E N E K B 9 26 D 2 HD Audio 3.3V 24.576MHz/48Mhz
page 37 page 35

P o w e r O n / O ff C K T . SW / B page 33 page 34 M D C 1 .5 H D A C o de c
page 35 page 35 page 33 ALC272 page 30
G s e n s o r T o u c h Pa d I n t .K B D SPI R O M
D C / D C In t e r fa c e C K T .
page 35 page 35 page 33 page 33 R J 1 1 A M P L IF IE R M IC C O N N In t . M IC H P C O N N V o lu m e C o n t r o l
page 36
page 33 TPA6017 page 31 page 31 page 31 page 31
P o w e r C ir c u it D C / D C page 31

page 37,38,39,40 SPK C O N N
4 41,42,43,44 4

page 31

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008-09-25 Deciphered Date 2009-09-25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-4971P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 25, 2009 Sheet 2 of 45
A B C D E
A B C D E

Voltage Rails Symbol Note :
Platform Item CPU NB VGA SB Comment
O : ON
: Digital Ground GM@ S1G2 RS780MC NA SB700
X : OFF PUMA@ GM@ S1G2 RS780MN NA SB700
PM@+GPM@ S1G2 RS780MN MXM SB700
: Analog Ground PM@+PM1@ S1G2 RX781 MXM SB700
+5VS
1
+3VS @ : just reserve , no build 1
power
plane +2.5VS Platform Item CPU NB VGA SB Comment
+1.8VS DEBUG@ : reserve for debug. GM@ S1G3 RS880MC NA SB710
+1.5VS Layout Notes TIGRIS@ GM@ S1G3 RS880M NA SB710
L
+1.1VS PM@+GPM@ S1G3 RS880M MXM SB710
+B +5VALW +1.8V UMA@: means for RS780M.
+VGA_CORE PM@+PM1@ S1G3 RX881 MXM SB710
+3VL +3VALW +0.9V
+1.2V_HT
+5VL +1.2VALW +0.9V
State +CPU_CORE_NB BTO (Build-To-Order) Option Table
+RTCVCC +3V_LAN
+CPU_CORE_0
Function Express card / PCMCIA BLUE TOOTH RJ11 SSD SATA ODD WiFi G- sensor 3 in 1 card reader
+CPU_CORE_1
Description (E/A) (B) (R) (S) (H)

Explain 16" 17" Half - size First Second RTS5159

S0 BTO EXPCARD@ / PCMCIA@ BT@ MDC@ SSD@ 16inch@ 17inch@ WLAN@ WIMAX@ G@ + G_1st@ G@ + G_2nd@ CARD@
O O O O
S1
O O O O Function FingerPrinter CAMERA & MIC HDMI LVDS wireset DC-IN CHIPSET
2 2

S3 Description (F) (X) (Y)
O O O X
Explain CAMERA MIC AMD(UMA) ATI VGA/B COMMON Cost down
S5 S4/AC
O O X X
BTO FP@ CAM@ MIC@ IHDMI@ HDMI@ H@ LVDSSET@ 16inch_45@ 17inch_45@ PUMA@ TIGRIS@
S5 S4/ Battery only
O X X X
SMBUS Control Table
S5 S4/AC & Battery
don't exist X X X X CPU LCD HDMI MXM
SOURCE INVERTER BATT HDMI SODIMM CLK WLAN DDC DDC NEW Thermal
CEC THERMAL GEN
I / II ROM ROM CARD Sensor
SENSOR
EC_SMB_CK1
KB926
I2C / SMBUS ADDRESSING EC_SMB_DA1 V V
EC_SMB_CK2
KB926
EC_SMB_DA2 V V
DEVICE HEX ADDRESS
I2C_CLK
RS780M
3 DDR SO-DIMM 0 A0 10100000 I2C_DATA V 3

DDR SO-DIMM 1 A4 10100100 DDC_CLK0
RS780M
CLOCK GENERATOR (EXT.) D2 11010010 DDC_DATA0 V
DDC_CLK1
RS780M
DDC_DATA1
SCL0
SB700
SDA0 V V V
EC SM Bus1 address SCL1
SB700
SDA1 V
Device HEX Address
SCL2
Smart Battery 16H 0001 011X b SB700
SDA2
HDMI-CEC 34H 0011 010X b
SCL3
EC KB926D2 SB700
SDA3

4 4
EC SM Bus2 address
Device HEX Address
ADI1032-1 CPU 98H 1001 100X b
ADI1032-2 VGA 9AH 1001 101X b Security Classification Compal Secret Data Compal Electronics, Inc.
EC KB926D2 Issued Date 2008-09-25 Deciphered Date 2009-09-25 Title

Ext. VGA/B THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
CS/B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-4971P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 25, 2009 Sheet 3 of 45
A B C D E
A B C D E

< C1, C2 and C7 must be replaced to 10-uF for Caspian compatibility >

+1.2V_HT
VLDT CAP. Near CPU Socket
250 mil
1 1 1 1 1 1
PUMA@ TIGRIS@ PUMA@ TIGRIS@ C3 C4 C5 C6
C1 C1 C2 C2
4.7U_0805_10V4Z 10U_0805_10V6K 4.7U_0805_10V4Z 10U_0805_10V6K 0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J
2 2 2 2 2 2

1 1

H_CADIP[0..15] H_CADOP[0..15]
10 H_CADIP[0..15] H_CADOP[0..15] 10
H_CADIN[0..15] H_CADON[0..15]
10 H_CADIN[0..15] H_CADON[0..15] 10

+1.2V_HT JCPUA PUMA@
C7
D1 HT LINK AE2 +VLDT_B 1 2 4.7U_0805_10V4Z
VLDT_A0 VLDT_B0 < VLDT_A & VLDT_B : HyperTransport I/O ring power >
D2 AE3
VLDT=500mA VLDT_A1 VLDT_B1
D3 AE4
VLDT_A2 VLDT_B2 TIGRIS@
D4 VLDT_A3 VLDT_B3 AE5
C7
H_CADIP0 E3 AD1 H_CADOP0 10U_0805_10V6K
H_CADIN0 L0_CADIN_H0 L0_CADOUT_H0 H_CADON0
E2 L0_CADIN_L0 L0_CADOUT_L0 AC1
H_CADIP1 E1 AC2 H_CADOP1
H_CADIN1 L0_CADIN_H1 L0_CADOUT_H1 H_CADON1
F1 AC3
H_CADIP2 L0_CADIN_L1 L0_CADOUT_L1 H_CADOP2
G3 L0_CADIN_H2 L0_CADOUT_H2 AB1
H_CADIN2 G2 AA1 H_CADON2
H_CADIP3 L0_CADIN_L2 L0_CADOUT_L2 H_CADOP3
G1 AA2
H_CADIN3 L0_CADIN_H3 L0_CADOUT_H3 H_CADON3
H1 AA3
2 H_CADIP4 L0_CADIN_L3 L0_CADOUT_L3 H_CADOP4 2
J1 L0_CADIN_H4 L0_CADOUT_H4 W2
H_CADIN4 K1 W3 H_CADON4
H_CADIP5 L0_CADIN_L4 L0_CADOUT_L4 H_CADOP5
L3 V1
H_CADIN5 L0_CADIN_H5 L0_CADOUT_H5 H_CADON5
L2 L0_CADIN_L5 L0_CADOUT_L5 U1
H_CADIP6 L1 U2 H_CADOP6
H_CADIN6 L0_CADIN_H6 L0_CADOUT_H6 H_CADON6
M1 U3
H_CADIP7 L0_CADIN_L6 L0_CADOUT_L6 H_CADOP7
N3 L0_CADIN_H7 L0_CADOUT_H7 T1
H_CADIN7 N2 R1 H_CADON7
H_CADIP8 L0_CADIN_L7 L0_CADOUT_L7 H_CADOP8
E5 L0_CADIN_H8 L0_CADOUT_H8 AD4
H_CADIN8 F5 AD3 H_CADON8
H_CADIP9 L0_CADIN_L8 L0_CADOUT_L8 H_CADOP9
F3 L0_CADIN_H9 L0_CADOUT_H9 AD5
< From NB > H_CADIN9 F4 AC5 H_CADON9 < To NB >
H_CADIP10 L0_CADIN_L9 L0_CADOUT_L9 H_CADOP10
G5 L0_CADIN_H10 L0_CADOUT_H10 AB4
H_CADIN10 H5 AB3 H_CADON10
H_CADIP11 L0_CADIN_L10 L0_CADOUT_L10 H_CADOP11
H3 AB5
H_CADIN11 L0_CADIN_H11 L0_CADOUT_H11 H_CADON11
H4 AA5
H_CADIP12 L0_CADIN_L11 L0_CADOUT_L11 H_CADOP12
K3 Y5
H_CADIN12 L0_CADIN_H12 L0_CADOUT_H12 H_CADON12
K4 W5
H_CADIP13 L0_CADIN_L12 L0_CADOUT_L12 H_CADOP13
L5 V4
H_CADIN13 L0_CADIN_H13 L0_CADOUT_H13 H_CADON13
M5 L0_CADIN_L13 L0_CADOUT_L13 V3
H_CADIP14 M3 V5 H_CADOP14
H_CADIN14 L0_CADIN_H14 L0_CADOUT_H14 H_CADON14
M4 U5
H_CADIP15 L0_CADIN_L14 L0_CADOUT_L14 H_CADOP15
N5 T4
H_CADIN15 L0_CADIN_H15 L0_CADOUT_H15 H_CADON15
P5 T3
L0_CADIN_L15 L0_CADOUT_L15

10 H_CLKIP0 J3 Y1 H_CLKOP0 10
L0_CLKIN_H0 L0_CLKOUT_H0
10 H_CLKIN0 J2 L0_CLKIN_L0 L0_CLKOUT_L0 W1 H_CLKON0 10
10 H_CLKIP1 J5 Y4 H_CLKOP1 10
L0_CLKIN_H1 L0_CLKOUT_H1
10 H_CLKIN1 K5 Y3 H_CLKON1 10
L0_CLKIN_L1 L0_CLKOUT_L1

10 H_CTLIP0 N1 R2 H_CTLOP0 10
L0_CTLIN_H0 L0_CTLOUT_H0
10 H_CTLIN0 P1 R3 H_CTLON0 10
3 L0_CTLIN_L0 L0_CTLOUT_L0 3
10 H_CTLIP1 P3 L0_CTLIN_H1 L0_CTLOUT_H1 T5 H_CTLOP1 10
10 H_CTLIN1 P4 L0_CTLIN_L1 L0_CTLOUT_L1 R5 H_CTLON1 10

@ 6090022100G_B

< FAN Control Circuit : Vout = 1.6 x Vset >
+5VS

1A

1
D1
2 @
+FAN1 C183 1SS355_SOD323-2
JFAN +3VS

2
1
C192 10U_0805_10V4Z +FAN1 1
1 1
2

1
1

10U_0805_10V4Z 2
2 3 3
2 U6 D2 C9 R12
1 8 @ @ 4
EN GND BAS16_SOT23-3 1000P_0402_25V8J GND 10K_0402_5%
2 7 5
VIN GND 1 GND
3 6

2
2

VOUT GND ACES_85204-0300N
34 EN_DFAN1 4 VSET GND 5 FAN_SPEED1 34
4 < From EC > < To EC > 4
2
APL5607KI-TRG_SO8 C8
@
0.01U_0402_25V7K
1

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008-09-25 Deciphered Date 2009-09-25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD CPU S1G2 HT I/F
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-4971P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 25, 2009 Sheet 4 of 45
A B C D E
A B C D E

< DDR2 VREF is 0.5 ratio >