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T650HVD01.0 Product Specification
Rev.0 6
Model Name: T650HVD01.0
Issue Date : 2012/06/25
( )Preliminary Specifications
( )Final Specifications
Customer Signature Date AUO Date
Approved By Approval By PM Director
CP Wang
_________________________________ ____________________________________
Note Reviewed By RD Director
Eugene CC Chen
____________________________________
Reviewed By Project Leader
Hank Chiu
____________________________________
Prepared By PM
Fanfan Lee
____________________________________
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T650HVD01.0 Product Specification
Rev.0 6
Contents
No
CONTENTS
RECORD OF REVISIONS
1 GENERAL DESCRIPTION
2 ABSOLUTE MAXIMUM RATINGS
3 ELECTRICAL SPECIFICATION
3-1 ELECTRIACL CHARACTERISTICS
3-2 INTERFACE CONNECTIONS
3-3 SIGNAL TIMING SPECIFICATION
3-4 SIGNAL TIMING WAVEFORM
3-5 COLOR INPUT DATA REFERENCE
3-6 POWER SEQUENCE
3-7 BACKLIGHT SPECIFICATION
4 OPTICAL SPECIFICATION
5 MECHANICAL CHARACTERISTICS
6 RELIABILITY TEST ITEMS
7 INTERNATIONAL STANDARD
7-1 SAFETY
7-2 EMC
8 PACKING
8-1 DEFINITION OF LABEL
8-2 PACKING METHODS
8-3 PALLET AND SHIPMENT INFORMATION
9 PRECAUTION
9-1 MOUNTING PRECAUTIONS
/9-2 OPERATING PRECAUTIONS
9-3 ELECTROSTATIC DISCHARGE CONTROL
9-4 PRECAUTIONS FOR STRONG LIGHT EXPOSURE
9-5 STORAGE
9-6 HANDLING PRECAUTIONS FOR PROTECT FILM
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T650HVD01.0 Product Specification
Rev.0 6
Record of Revision
Version Date Page Description
0.0 2012/02/20 First release
0.1 2012/4/6 Update LED Pin assignment
0.2 2012/04/12 Third release
0.3 2012/04/12 Forth release
0.4 2012/04/19 3-7 & 8-3 spec updated
0.5 2012/05/03 20, 29 Update Internal PWM & Reliability test items
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T650HVD01.0 Product Specification
Rev.0 6
1. General Description
This specification applies to the 65.0 inch Color TFT-LCD Module T650HVD01.0. This LCD module has a TFT
active matrix type liquid crystal panel 1,920x1,080 pixels, and diagonal size of 65.0 inch. This module supports
1,920x1,080 mode. Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arranged in vertical
stripes. Gray scale or the brightness of the sub-pixel color is determined with a 10-bit gray scale signal for each
dot.
The T650HVD01.0 has been designed to apply the 10-bit 2 channel LVDS interface method. It is intended to
support displays where high brightness, wide viewing angle, high color saturation, and high color depth are very
important. Also, 3D function is also embedded into front glass as pattern retarder.
* General Information
Items Specification Unit Note
Active Screen Size 65.00 inch
Display Area 1428.48 (H) x 803.52 (V) mm
Outline Dimension 1508.0(H) x 878.0(V) x 12.8(D) mm
Driver Element a-Si TFT active matrix
Bezel Opening 1440.6 (H) x 814.6 (V) mm
Display Colors 10 bit, 1.07B Colors
Number of Pixels 1,920x1,080 Pixel
Pixel Pitch 0.744 mm
Pixel Arrangement RGB vertical stripe
Display Operation Mode Normally Black
Rotate Function Unachievable
.
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T650HVD01.0 Product Specification
Rev.0 6
2. Absolute Maximum Ratings
The followings are maximum values which, if exceeded, may cause faulty operation or damage to the unit
Item Symbol Min Max Unit Conditions
Logic/LCD Drive Voltage Vcc -0.3 14 [Volt] Note 1
Input Voltage of Signal Vin -0.3 4 [Volt] Note 1
o
Operating Temperature TOP 0 +50 [ C] Note 2
Operating Humidity HOP 10 90 [%RH] Note 2
o
Storage Temperature TST -20 +60 [ C] Note 2
Storage Humidity HST 10 90 [%RH] Note 2
o
Panel Surface Temperature PST 65 [ C] Note 3
Note 1: Duration:50 msec.
Note 2 : Maximum Wet-Bulb should be 39 and No condensation.
The relative humidity must not exceed 90% non-condensing at temperatures of 40 or less. At temperatures
greater than 40 , the wet bulb temperature must not exceed 39 .
Note 3: Surface temperature is measured at 50 Dry condition
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T650HVD01.0 Product Specification
Rev.0 6
3. Electrical Specification
The T650HND01.0 requires two power inputs. One is employed to power the LCD electronics and to drive the TFT
array and liquid crystal.
3.1 Electrical Characteristics
3.1.1: DC Characteristics
Value
Parameter Symbol Unit Note
Min. Typ. Max
LCD
Power Supply Input Voltage VDD 10.8 12 13.2 VDC
Power Supply Input Current IDD -- 1.56 1.93 A 1
Power Consumption PC -- 18.72 23.16 Watt 1
Inrush Current IRUSH -- -- 7.5 A 2
Input Differential Voltage VID 200 400 600 mVDC 3
LVDS Differential Input High Threshold Voltage VTH +100 -- +300 mVDC 3
Interface
Differential Input Low Threshold Voltage VTL -300 -- -100 mVDC 3
Input Common Mode Voltage VICM 1.1 1.25 1.4 VDC 3
VIH
CMOS Input High Threshold Voltage 2.7 -- 3.3 VDC 5
(High)
Interface VIL
Input Low Threshold Voltage 0 -- 0.6 VDC 5
(Low)
Backlight Power Consumption(Refer to Section: 3.7) PBL 182.2 202.4 Watt
Life time (MTTF) 30000 Hour 9,10
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T650HVD01.0 Product Specification
Rev.0 6
3.1.2: AC Characteristics
Value
Parameter Symbol Unit Note
Min. Typ. Max
Input Channel Pair Skew Margin tSKEW (CP) -500 -- +500 ps 6
Receiver Clock : Spread Spectrum Fclk Fclk
Fclk_ss -- MHz 7
Modulation range -3% +3%
LVDS
Interface Receiver Clock : Spread Spectrum
Fss 30 -- 200 KHz 7
Modulation frequency
Receiver Data Input Margin
Fclk = 85 MHz tRMG -0.4 -- 0.4 ns 8
Fclk = 65 MHz -0.5 -- 0.5
Note :
1. Test Condition:
(1) VDD = 12.0V
(2) Fv = 120Hz
(3) Fclk= Max freq.
(4) Temperature = 25
(5) Typ. Input current : White Pattern
Max. Input current: Heavy loading pattern defined by AUO
>> refer to "Section:3.3 Signal Timing Specification, Typical timing"
2. Measurement condition : Rising time = 400us
9''
*1'
s
3. Test Condition:
(1) The measure point of VRP is in LCM side after connecting the System Board and LCM.
(2) Under Max. Input current spec. condition.
4. VICM = 1.25V
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T650HVD01.0 Product Specification
Rev.0 6
LVDS -
V IC M V TH
|V ID |
V TL
LVDS +
GND
|V ID |
0V
|V ID |
5. The measure points of VIH and VIL are in LCM side after connecting the System Board and LCM.
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T650HVD01.0 Product Specification
Rev.0 6
6. Input Channel Pair Skew Margin.
Note: x = 0, 1, 2, 3, 4
7. LVDS Receiver Clock SSCG (Spread spectrum clock generator) is defined as below figures.
)66
)FONB
)FONBVV PD[
)FON
)FONB
)FONBVV PLQ
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T650HVD01.0 Product Specification
Rev.0 5
8. Receiver Data Input Margin
Rating
Parameter Symbol Unit Note
Min Type Max
Input Clock Frequency Fclk Fclk (min) -- Fclk (max) MHz T=1/Fclk
Input Data Position0 tRIP1 -|tRMG| 0 |tRMG| ns
Input Data Position1 tRIP0 T/7-|tRMG| T/7 T/7+|tRMG| ns
Input Data Position2 tRIP6 2T/7-|tRMG| 2T/7 2T/7+|tRMG| ns
Input Data Position3 tRIP5 3T/7-|tRMG| 3T/7 3T/7+|tRMG| ns
Input Data Position4 tRIP4 4T/7-|tRMG| 4T/7 4T/7+|tRMG| ns
Input Data Position5 tRIP3 5T/7-|tRMG| 5T/7 5T/7+|tRMG| ns
Input Data Position6 tRIP2 6T/7-|tRMG| 6T/7 6T/7+|tRMG| ns
W5,3
W5,3
W5,3
W5,3
W5,3
W5,3
W5,3
/9'6 5[
5[ 5[ 5[ 5[ 5[ 5[ 5[ 5[ 5[ 5[ 5[ 5[
,QSXW 'DWD
/9'6 5[
,QSXW &ORFN 9GLII 9
)FON 7