Text preview for : QUANTA AX3 WINBLEDON AX3.5 - DA0AX3MB6C2 DDR3 - REV 1A.pdf part of HP QUANTA AX3 WINBLEDON AX3.5 - DA0AX3MB6C2 DDR3 - REV 1A HP HP COMPAQ CQ42 CQ45 - QUANTA AX3_5 DDR3 QUANTA AX3 WINBLEDON AX3.5 - DA0AX3MB6C2 DDR3 - REV 1A.pdf



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PCB STACK UP Wimbledon AX3/5 BLOCK DIAGRAM 01
6L UMA CO-LAY DIS
A
CPU CPU THERMAL A

SENSOR
LAYER 1 : TOP Penryn 14.318MHz
PAGE 4
LAYER 2 : SGND
478P (uPGA) /35W
LAYER 3 : IN1 PAGE 3,4 CLK_CPU_BCLK,CLK_CPU_BCLK#
CLK_MCH_BCLK,CLK_MCH_BCLK# CLOCK GEN
LAYER 4 : IN2 DREFCLK,DREFCLK# ALPRS355B MLF64PIN
FSB 667/800/1066
LAYER 5 : VCC DREFSSCLK,DREFSSCLK#
PAGE 2
LAYER 6 : BOT

Level Shift
HDMI CON
(Option)
NORTH BRIDGE PAGE 13
PAGE 13
DDRIII-SODIMM0 DDRIII 800/1066 MHz

PAGE 10 CRT
B Cantiga B

PAGE 13
DDRIII-SODIMM1 DDRIII 800/1066 MHz GL40 / GM45 Dual Link
PAGE 11 LCD CONN
PAGE 5~9 PAGE 12

32.768KHz
DMI LINK
USB2.0
SYSTEM CHARGER (ISL6251AHAZ-T) SATA - HDD
SATA0 150MB 0,1,8 5 3 6
PAGE 25 PAGE 21 SOUTH BRIDGE USB2.0 Ports BlueTooth Webcam
Card Reader
X3 PAGE 22 PAGE 22 PAGE 22
RTS5159
SYSTEM POWER (RT8206BGQW) SATA - CD-ROM
SATA1 150MB PAGE 18
PAGE 26 PAGE 21 ICH-9M
C PCI-E C

VCCP +1.05V (RT8209AGQW)
X1 X1
& +1.8VSUS (RT9043GB)
PAGE 27 Azalia
PAGE 14~17 Mini PCI-E LAN
Card Realtek
CPU CORE (ISL6262ACRZ-T) PCIE-LAN
PAGE 28 Realtek (Wireless LAN) RTL8103EL
32.768KHz LPC MDC ALC270 (10/100 LAN)

PAGE 20 PAGE 19 PAGE 21 PAGE 20
DDR III SMDDR +1.5VSUS
(RT8207AGQW) PAGE 29
SPI for
ENE KBC HDCP 25MHz
SYSTEM DISCHARGER
PAGE 30 Keyboard PAGE 23 KB3926 C0/D2
PAGE 15
Internal Audio Jacks Internal RJ45
Touch Pad PAGE 23 MIC (Phone/ MIC) Speaker PAGE 20
PAGE 24 PAGE 19 PAGE 19 PAGE 19
D D




FAN SPI
PROJECT :AX3
PAGE 24 PAGE 24 Quanta Computer Inc.
Size Document Number Rev
Custom 1A
Block Diagram
NB5 Date: Wednesday, November 25, 2009 Sheet 1 of 30
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8




+3V
L26
3,4,5,6,8,9,14,17,27,28 +1.05V
4,6,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,28,30 +3V
02
+3V_CK_MAIN
HCB1608KF-181T15_6
U10
C365 C360 C331 C361 C348 C329
10U/6.3V_8 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 +3V_CK_MAIN 23 61
A VDDPLL3 CPUCLKT0 CLK_CPU_BCLK 3 A
16 VDD48 CPUCLKC0 60 CLK_CPU_BCLK# 3
9
L28 4
VDDPCI
VDDREF
CK505 CPUCLKT1 58 CLK_MCH_BCLK 5
+3V_CK_CPU 46 57
VDDSRC CPUCLKC1 CLK_MCH_BCLK# 5
HCB1608KF-181T15_6 +3V_CK_CPU 62 VDDCPU
CPUT2_ITP/SRCT8 54
C376 C370 +3V_CK_MAIN2 19 53
10U/6.3V_8 0.1U/10V_4 VDD96I/O CPUC2_ITP/SRCC8
27
VDDPLL3I/O
10/21 Montevina
33 VDDSRCI/O DOTT_96/SRCT0 20 DREFCLK 6
43 21 DREFCLK# 6
VDDSRCI/O DOTC_96/SRCC0
52 VDDSRCI/O
L22 24
27MHz_Nonss/SRCCLK1/SE1 DREFSSCLK 6
+3V_CK_MAIN2 56 25
VDDCPU_IO 27Mhz_ss/SRCCLC1/SE2 DREFSSCLK# 6
HCB1608KF-181T15_6 55 NC
28
C333 C330 C342 C374 C332 C373 C353 SRCCLKT2/SATACL
29
10U/6.3V_8 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 CG_XIN SRCCLKC2/SATACL
3 X1
CG_XOUT 2 31
X2 SRCCLKT3/CR#_C
32
SRCCLKC3/CR#_D
34 CLK_PCIE_3GPLL 6
R183 *100K/F_4 SRCCLKT4
SRCCLKC4 35 CLK_PCIE_3GPLL# 6
+3V 16 CK_PWG 63 45
+3V CK_PWRGD/PD# PCI_STOP# PM_STPPCI# 16
CPU_BSEL1 R181 2.2K_4 FSB 64 44
FSLB/TEST_MODE CPU_STOP# PM_STPCPU# 16
48 CLK_PCIE_ICH 15
SRCCLKT6
47 CLK_PCIE_ICH# 15
SRCCLKC6
2




R165 R157 10,11 CGCLK_SMB 7 51
SCLK SRCCLKT7/CR#_F CLK_PCIE_WLAN 21
2




B R164 Q9 10K/F_4 10K/F_4 6 50 B
10,11 CGDAT_SMB SDATA SRCCLKC7/CR#_E CLK_PCIE_WLAN# 21
10K/F_4 2N7002E
16 PDAT_SMB 3 1 CGDAT_SMB 37
1




SRCCLKT9 CLK_PCIE_LAN 20
22 GND SRCCLKC9 38 CLK_PCIE_LAN# 20
TME 26 GND
18 GND48 SRCCLKT10 41 CLK_PCIE_SATA 14
59 42 CLK_PCIE_SATA# 14
+3V GNDCPU SRCCLKC10
15
GNDPCI
1 40
GNDREF SRCCLKT11/CR#_H
30 39
GNDSRC SRCCLKC11/CR#_G
2




Q8 36
2N7002E GNDSRC
49
CGCLK_SMB GNDSRC
16 PCLK_SMB 3 1 8
PCICLK0/CR#_A R_CLK_MCH_OE# R160 475/F_4
PCICLK1/CR#_B 10 CLK_MCH_OE# 6
11 TME R158 33_4 PCLK_DEBUG 21
PCICLK2/TME R_PCLK_KBC R155 33_4
12 PCLK_KBC 24
PCICLK3 27M_SEL
0=overclocking PCICLK4/27_SELECT
13
of CPU and Y3
65 ITP_EN R152 33_4 PCLK_ICH 15
CG_XIN 1 CG_XOUT EPAD
SRC Allowed 2
14 R147 22_4 CLK_48M_USB 16
PCI_F5/ITP_EN R148 22_4
1 = overclocking 14.318MHZ CLK_48M_CR 18
1




1




17 FSA R149 2.2K_4 CPU_BSEL0
of CPU and SRC C367 C372 USB_48MHZ/FSLA R171 10K/F_4 CPU_BSEL2
5 FSC R172 33_4
not Allowed 33P/50V_4 33P/50V_4 CLK_14M_ICH 16
2




2




FSLC/TST_SL/REF
ICS9LPRS355BKLF MLF64

+3V

C
DB:Change from 27P to 33P(TXC suggestion) C

CK505 QFN64
2




des R153 27M_SEL Silego SLG8SP513VTR AL8SP513000
*10K/F_4 PIN20 PIN21 PIN24 PIN25 +3V
PIN13 Realtek RTM875N-606-VD-GR AL000875000
1




27M_SEL CLK_MCH_OE# R161 10K/F_4
ICS ICS9LPRS355BKLFT ALPRS355000
2




0=UMA DOT96T DOT96C SRCT1/LCDT_100 SRCT1/LCDT_100
int R156
10K/F_4 1 = External
SRCT0 SRCC0 27Mout-NSS 27Mout-SS
1




VGA

0=UMA PCLK_KBC
1 = External VGA C336 *33P/50V_4

FSC FSB FSA CPU SRC PCI C328 *27P/50V_4 PCLK_ICH
CPU Clock select
+3V C338 *33P/50V_4 PCLK_DEBUG
CPU_BSEL0 R142 *0_4/S
1 0 1 100 100 33
3 CPU_BSEL0 MCH_BSEL0 6
short0402 0 0 1 133 100 33 C314 *10P/50V_4 CLK_48M_USB

0 1 1 166 100 33 C315 *10P/50V_4 CLK_48M_CR
*10K/F_4 R145 *1K/F_4
R150 0 1 0 200 100 33 C354 *33P/50V_4 CLK_14M_ICH
R_PCLK_KBC 3 CPU_BSEL1 CPU_BSEL1 R184 *0_4/S MCH_BSEL1 6
D short0402 D
0 0 0 266 100 33 for EMI
ITP_EN

R182 *1K/F_4
1 0 0 333 100 33
+1.05V
R159 1 1 0 400 100 33
10K/F_4 *10K/F_4 3 CPU_BSEL2 CPU_BSEL2 R169 *0_4/S MCH_BSEL2 6
R154 short0402 1 1 1 RSVD 100 33 PROJECT :AX3
R168 *1K/F_4
1K to NB only when
XDP is implement.No
Quanta Computer Inc.
+1.05V
Enable ITP CLK XDP can use 0 ohm
Size Document Number Rev
Custom 1A
Clock Generator
NB5 Date: Friday, November 27, 2009 Sheet 2 of 30
1 2 3 4 5 6 7 8
5 4 3 2 1




5 H_A#[35:3]
H_A#3
H_A#4
J4
L5
U18A
A[3]# ADS# H1
E2
H_ADS# 5
5 H_D#[63:0]
H_D#0 E22
U18B
Y22 H_D#32
H_D#[63:0]
03
A[4]# BNR# H_BNR# 5 D[0]# D[32]#




ADDR GROUP 0
ADDR GROUP 0
H_A#5 L4 G5 H_D#1 F24 AB24 H_D#33
A[5]# BPRI# H_BPRI# 5 D[1]# D[33]#
H_A#6 K5 H_D#2 E26 V24 H_D#34
H_A#7 A[6]# H_D#3 D[2]# D[34]# H_D#35
M3 A[7]# DEFER# H5 H_DEFER# 5 G22 D[3]# D[35]# V26
H_A#8 N2 F21 H_D#4 F23 V23 H_D#36
A[8]# DRDY# H_DRDY# 5 D[4]# D[36]#
H_A#9 J1 E1 H_D#5 G25 T22 H_D#37
D A[9]# DBSY# H_DBSY# 5 D[5]# D[37]# D
H_A#10 N3 H_D#6 E25 U25 H_D#38
A[10]# D[6]# D[38]#




DATA GRP 0

DATA GRP 2
DATA GRP 2
H_A#11 P5 F1 H_D#7 E23 U23 H_D#39
A[11]# BR0# HBREQ#0 5 D[7]# D[39]#
H_A#12 P2 H_D#8 K24 Y25 H_D#40
A[12]# D[8]# D[40]#




CONTROL
H_A#13 L2 D20 H_IERR# R83 49.9/F_4 +1.05V H_D#9 G24 W22 H_D#41
H_A#14 A[13]# IERR# H_D#10 D[9]# D[41]# H_D#42
P4 A[14]# INIT# B3 H_INIT# 14 J24 D[10]# D[42]# Y23
H_A#15 P1 H_D#11 J23 W24 H_D#43
H_A#16 A[15]# H_D#12 D[11]# D[43]# H_D#44
R1 A[16]# LOCK# H4 H_LOCK# 5 H22 D[12]# D[44]# W25
5 H_ADSTB#0 M1 H_D#13 F26 AA23 H_D#45
ADSTB[0]# H_CPURST# 5 D[13]# D[45]#
5 H_REQ#[4:0] C1 H_D#14 K22 AA24 H_D#46
H_REQ#0 RESET# H_RS#0 H_D#15 D[14]# D[46]# H_D#47
K3 F3 H23 AB25
H_REQ#1 REQ[0]# RS[0]# H_RS#1 D[15]# D[47]#
H2 REQ[1]# RS[1]# F4 5 H_DSTBN#0 J26 DSTBN[0]# DSTBN[2]# Y26 H_DSTBN#2 5
H_REQ#2 K2 G3 H_RS#2 H_RS#[2:0] 5 5 H_DSTBP#0 H26 AA26
REQ[2]# RS[2]# DSTBP[0]# DSTBP[2]# H_DSTBP#2 5
H_REQ#3 J3 G2 5 H_DINV#0 H25 U22
REQ[3]# TRDY# H_TRDY# 5 DINV[0]# DINV[2]# H_DINV#2 5
H_REQ#4 L1
H_A#[35:3] REQ[4]# H_D#[63:0] H_D#[63:0]
G6 H_HIT# 5
H_A#17 HIT# H_D#16 H_D#48
Y2 E4 H_HITM# 5 N22 AE24
H_A#18 A[17]# HITM# H_D#17 D[16]# D[48]# H_D#49
U5 A[18]# K25 D[17]# D[49]# AD24




ADDR GROUP 1
ADDR GROUP 1
H_A#19 R3 AD4 ITP_BPM#0 TP2 H_D#18 P26 AA21 H_D#50
H_A#20 A[19]# BPM[0]# ITP_BPM#1 H_D#19 D[18]# D[50]# H_D#51
W6 AD3 TP60 R23 AB22
A[20]#