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SECTION 8 DESCRIPTION OF CIRCUITRY
8.1 CAMERA BLOCK CIRCUIT DESCRIPTION 8.1.1 IS board The CCDs of 1/3" IT, 380,000-pixel (NTSC), 440,000-pixel (PAL) CCDs. Vsub is adjustment-free. ISB, ISG and ISR are connected through FPCs, which cannot be disconnected from the circuit boards. The CCDs are soldered directly onto the board. Therefore, soldering should be removed when replacing the CCD block assembly. The S/H circuit, which in the previous models has been located on the IS board, is located in the AFE block on the Main board that is located after the IS board. This has resulted in a simplification of the IS board.
MAIN BOARD IS BOARD
IC501 Q1 IC1
IC502 Q2 IC2
IC503 Q3 IC3 IC4
IC511
IC504 IC505 IC506
IC512
IC510
Fig. 8-1-1
8-1
8.1.2 Main board The main block can be divided into the three functional components of the AFE, PLD and DBE blocks. (1) AFE (Analog Front End) block IC501, 502 and 503 are the CCD signal processor ICs. They perform S/H, AGC and A/D conversions. It converts the analog output signals from the CCDs (pixel charge signals) into 12-bit digital signals and outputs them. The handling dynamic range is 400%. ICs 504, 505 and 506 form the V-driver circuit, which supplies the vertical drive pulses to the CCDs.
ing the 27 MHz clock, are input to the LPF & Down-sampling circuit and output from it at 13.5 MHz. This signal is the Data Formatter (DV) signal. It is output in 4-bit widths by switching the LSB (4-bit) and MSB (4-bit) using the 2x clock (Fig. 8-1-3), and the signals obtained by this are the 4-bit Y and C (Cb/Cr) signals. These signals are sent to the VCR as the recorded signals. The COLOR-BAR-GEN circuit generates the color bar signal for use in recording. Apart from this, the color bar signal displayed on the LCD monitor and VIDEO output is generated by the encoder circuit in the DBE IC (IC621). When "BARS" is selected, both of the color bar signals are switched ON.
Input 400%
Graduation 4096 (12bit)
Y7 MSB Y6 Y5 Y4 Y3 Y2 Y1 Y0 13.5MHz 27MHz Y3/Y7 Y2/Y6 Y1/Y5 Y0/Y4 To DVC
100% 0%
1120 128 (8bit) 0
LSB
Fig. 8-1-2 (2) PLD (Program Logic Driver) block IC561 is the PLD IC, which can be divided functionally into the AFE-IF, TG, CLK-CTL, ZEBRA-ZONE, DV-REC-IF and DVPB-IF sections.
13.5MHz 8bit Y1 Y2 Y3 Y4
1 AFE-IF:
The 12-bit RGB digital signals output from the AFE block are input to the MUX (multiplexer) in this section and output to the DBE block by sequential switching using the 3x clock (52 MHz). At the same time, this section also generates the Y(AFY) signal for use in the lens autofocusing from the RGB signals, and output the Y(AFY) signal to the lens. The LINE REVERSE circuitry inverts (by mirror image inversion) the Bch signal, which has been inverted by the gapless prism (see section 8.2, "New prism optics") to return it to the normal signal.
4bit
Y1L Y1M Y2L Y2M Y3L Y3M Y4L Y4M
27MHz
Fig. 8-1-3
6 DV-PB-IF:
The 27 MHz, 4-bit wide Y and C (Cb/Cr) playback signals from the VCR are input to the Data Formatter (DV) circuit, and output as the DV signals including Y: 13.5 MHz, Cb: 6.75 MHz and Cr: 6.75 MHz (this is the reverse operation to 5). The Data Formatter (DVE) converts the Y/Cb/Cr signals respectively into 8-bit signals, switches them using the 3x clock in MUX and sends them to the DBE block through the PB switch. As the interface to the DBE block has a width of 12 bits, the signal width is adjusted by adding 4 bits (all "0") at the top of each 8-bit signal.
2 TG (Timing Generator):
This section generates the H-drive pulse and sends it to the CCDs through ICs 510 and 512 in the AFE block.
3 CLK-CTL:
This section switches the 2x and 3x clocks, used in signal processing, based on the 14 MHz reference clock.
4 ZEBRA-ZONE:
This section outputs the zebra signal for use in display on the LCD monitor and viewfinder.
5 DV-REC-IF:
The DV-Y (8-bit) and DV-C (8-bit) signals, which are output from the DV/IF circuit in IC621 in the DBE block us8-2
8-3
DVC VTR KADV300
IC561
IC562
MAIN BOARD
IC563
IC564
Fig. 8-1-4
(3) DBE (Digital Back End) block 1 Circuit blocks in the DBE IC (IC621): IC621 is composed of the camera DSP and mainly handles camera process signals. The DSP IC is adopted for the first time with this model. Its internal functions are as described below. a) Input signals The 12-bit RGB digital signals, obtained by A/D conversion in the AFE block, are input to the PLD (IC561), rearranged (using the 3x clock) by the internal MUX (multiplexer) and sent to the DSP. b) White blemish compensation This is the first circuit block that the input signals enter. The pixels are corrected in real time "Blemish Compensation" in the figure and the blemish is detected by "Blemish Detect" in the next stage. The position data of the detected blemish is stored inside the EEPROM (IC406), loaded every time the power is turned on and applied as a correction by "Blemish Compensation". c) Shifted pixel correction To prevent false signals and in consideration of the production tools, the CCDs are bonded by adopting the 1/2 pixel shifting technique. However, the VCR of DVC (4:1:1/ NTSC, 4:2:0/PAL ) digital camcorders do not need as high signal resolution as multipurpose cameras. Also in con-
sideration of the ease of signal processing and rate conversion, it is more convenient to handle the RGB signals at the same timing. Therefore, their timing is returned to the same timing in an early stage in the DSP. It is also in this stage that the 14 MHz sampled RGB signals are oversampled for their processing in 28 MHz. d) RGB gamma circuit "RGB Gamma" compresses the dynamic range of the signals while they are still in the RGB format. The RGB signals change from 12-bit to 10-bit signals from the output of this circuit. The gamma processing method is the "table method" in place of the "polygonal line approximation Method". The "table method" is also adopted in other circuits such as "Detail" and "Y-Gamma". The table data for use in the processing is handed from the camera's CPU to the DMA block in the DSP. e) Y/Cb/Cr conversion The signals that have been in the RGB format until "RGB Gamma" are converted into the Y/Cb/Cr format in this circuit block. However, the sampling rate is still 28 MHz (4:4:4) at this stage. f) Y-gamma processing block This circuit block applies gamma processing to the Y signal, which changes from a 10-bit to an 8-bit signal in this stage. (The Cb/Cr signals are still 10-bit signals in this stage.)
MAIN Board IC621
R,G,B(14MHz)
Digital Signal Processor Block Diagram
CCD error address Data from DMA
Input
Blemish Compensation
SD RAM
Y(8)/Cb(8)/Cr(8) 27MHz/4:2:2
DMA
SDRAM AREA
Y(8)/Cb(8)/Cr(8) 27MHz/4:2:2
Blemish Detect
Error Address to DMA
Buff
Y(8)/Cb(8)/Cr(8) 27MHz/4:2:2
NTSC/PAL 54MHz ENC (add SYNC)
10bit
IC622
Zebra Area
D/A 10bit
Half pixel shift
R,G,B(28MHz)
12bit
Rate convert from 28 to 27MHz
Y(8)/Cb(8)/Cr(8) 28MHz/4:2:2 4:4:4 to 4:2:2 CbCr 10 to 8bit Y(8)/Cb(10)/Cr(10) 28MHz/4:4:4 Y-Gamma 10 to 8bit
NTSC/PAL GEN.
LCD Monitor
Color Matrix
R,G,B(28MHz)
12bit
CCD Error Data Area
DV Inter Face
Composite Video
DVC Section Video Out
RGB Gam ma (Table)
R,G,B(28MHz)
10bit
Knee Black Strech/Compress
Look Up Table Data Area
Color Killer
RGB to Y/Cb/Cr convert (28MHz/4:4:4)
Y/Cb/Cr(28MHz/4:4:4)
10bit
Chroma Suppress Detail(Table)
Interface
Camera CPU (IC402)
Fig. 8-1-5 Digital Signal Processor Block Diagram 8-4
g) 4:4:4 4:2:2 conversion This circuit block converts the Cb/Cr signals from 14 MHz to 7 MHz (4:4:4 4:2:2) and from 10-bit to 8-bit signals. h) Rate conversion block While the signals have been processed based on the 14 MHz and 18 MHz sampling clock rates, this circuit block converts them into 27 MHz-based signals. i) Encoder After completion of the camera input signal processing, the signals are divided into those for use by the main recording circuitry (those sent to the DVC VCR) and those for use by the LCD monitor. This circuit block generates the composite signal using the NTSC/PAL timing generator and digital encoder in the DSP. It is also in this circuit block that the sync signal is added. However, as simple addition of the sync signal causes the number of bits assigned to the effective video to be reduced, the total number of signal bits is increased to 10 bits at the time of sync addition.
In consequence, the D/A block for the analog output employs a 10-bit encoder. This circuit block also generates the color bar signal for use in display on the LCD monitor and the viewfinder (the color bar signal for recording is generated in the PLC IC (IC561)). j) DMA block This circuit block mainly handles the data exchange with the camera CPU and the storage of DSP parameters (table data).
2 Analog video amplifier:
IC625 is the analog video amp. It generates the composite signal and the Y/C signals from the analog Y/C signals, which are output from the encoder of the DBE IC (IC621), and outputs them at the connectors. For the signal level adjustments, the DBE IC adjusts the overall Y signal level and the analog video amp adjusts the C signal level.
MAIN BOARD
IC621 IC622
IC625
Fig. 8-1-6
(4) Other circuits 1 Input to the KA-DV300 network pack: The input signals from the VCR (PLAYBACK or EE) are branched on the Main board and output to the KA-DV300 based on the drive by ICs 565 and 567. As a result, both the recorded EE signals and playback signals can be converted into MPEG4 by the KA-DV300.
2 ROM IC:
IC562 is the ROM IC storing the program for the PLD (IC561). The program can be rewritten through CN561 but this is not done in stores because a special tool is required.
8-5
8.2
NEW PRISM OPTICS
The GY-DV300 adopts a new, 1/3" three-CCD prism optics (gapless prism technique) featuring a compact size and light weight. The new prism optics incorporates new technologies that are different from those used in previous models. (1) Gapless prisms The light is divided into the three primary colors of light, R, G and B, by the combination of three color-spectral prisms. Each of these prisms has special surface treatment to reflect the light of specific wavelengths. These prisms have been bonded by reserving air gaps of 2/1000 mm in order to reflect the light using these air gaps. However, the difficulty in combining the prisms by providing these gaps uniformly and in parallel has become a factor for increasing the production costs. But the new gapless prism technique makes it possible to combine the prisms without leaving the air gaps. This has improved productivity and decreased the production costs. As this technique also allows the prism size to be reduced, it contributes to a reduction in both size and costs.
normal image) by an electrical circuit. In addition, the arrange ment of the RGB colors of the new optics is also different from the previous optics. (2) Direct bonding Previous optics attached the CCDs to the prisms by means of sheet metal soldering technique (solder bonding). As the CCD packages themselves are not made of a soldering-compatible material (or treatment), each CCD had to be fixed on a sheet metal plate (made of soldering-compatible metallic material), which was then soldered on the soldering section (copper-plated area) of the prism optics. With this technique, the CCDs can be replaced individually because they can be removed easily by melting the solder. (Nevertheless, bonding is possible only in the production line because it requires special tools and technologies for achieving register accuracy of the micrometric order.) The disadvantages of the previous optics included high costs due to an increase in the number of parts, such as the sheet metal plates used in the soldering process. An increase in the CCD block size for incorporating these parts was also a problem.
Previous prism optics
Fig. 8-2-2 Parts Required in Previous Bonding Techniques On the other hand, the direct bonding technique of the new optics bonds the CCD packages and prisms directly using a special adhesive agent that hardens under the irradiation of UV rays. Because of this property, the adhesive agent does not harden at the register alignment stage but is hardened when the UV rays are irradiated after the alignment. The adhesive agent can be used to bond the ceramic-made CCD packages and glass-made prisms without additional metallic parts. This feature makes it possible to implement the whole CCD block featuring a compact size and a light weight. However, the use of an adhesive agent for bonding the CCDs makes it impossible to peel the CCDs once they are fixed. In case of CCD trouble, it is not possible to replace only the faulty CCD. As a result, the CCD block of this model cannot be serviced even at the factory. If CCD faults are discovered during a store servicing, the whole CCD block assembly should be replaced.
New gapless prism optics
Fig. 8-2-1 As the use of gap-less prism optics results in the impossibility of reflections from the opposite directions inside the prism optics, the Bch signal is reflected only once (In the previous prism optic systems, a signal corresponding to Rch was reflected twice by the internal prisms. See Figure 8-2-1). This makes the Bch image an inverted one (the left and right of which are inverted like a mirror image). To deal with this, the Bch video signal from the CCD is inverted (returned to a
8-6
8.3
LENS CONTROL SYSTEM
Peak point It goes beyond the peak, goes back to the peak and stops there.
Modulation
Outline The lens assembly used with this model incorporates automatic control functions such as autofocusing and OIS (Optical Image Stabilizer) in addition to the auto iris control that has also been available with previous model. In order to provide compatibility with them, the Lens CPU (IC905 on the Main board) is provided for exclusive use in the lens control. This chapter gives a description of this control system. (1) Autofocusing control In general, autofocusing is performed by adopting one of the following three techniques. 1) Active autofocusing: Triangulation using IR rays or ultrasound waves 2) Passive autofocusing: Phase error detection using an optical focus sensor. 3) TTL (Through The Lens) autofocusing Electrical signal processing of an image incident through the lens The autofocusing of the lens in this model is controlled with the TTL method. The video signals obtained from the three RGB CCDs are A/ D converted and input to the PLD (IC561) in the digital signal processor block. The PLD generates the 9-bit Y signal for use in autofocusing (AFY) apart from the processing of the signals to be supplied to the main camcorder circuitry. The AFY signal data is subjected to the internal computation by the autofocusing DSP (IC906) and the results are sent to the lens CPU. The lens CPU outputs the data as serial data to the focus/ zoom driver IC (IC901) to drive the focusing motor of the lens using the DC voltages output from the D/A output ports. The factors deciding the autofocusing effect is the computation inside the DSP and the program processed by the lens CPU. Autofocusing control consists of moving the focusing lens a little beyond the AFY modulation peak and then returning it slightly so that the focusing lens stops at the peak position. The modulation peak point is defined as the optimum focus point. Due to the principles themselves, focusing may sometimes be difficult when the object has little contrast.
Focusing Lens Control
Fig. 8-3-1 (2) OIS (Optical Image Stabilizer) control The lens of this model incorporates the OIS function for correcting blurring due to a slight movement of the hands. The optical correction employs the shifting technique, the detail of which is described in section 8.4. This section deals only with the flow of control signals. Blurring is detected via the information from the gyro sensors provided on the lens. Two gyro sensors for horizontal and vertical directions are used to detect the lens blurring directions. The information output from the gyro sensors is input to the CAM CPU circuit block on the Main board. This circuit block obtains information such as the displacement and velocity (acceleration) of the lens, detects the blurring situation based on it, and sends the result signals (GYRO_X, GYRO_Y) to the lens CPU. The CPU performs software-based computations of the optimum correction amount based on the obtained information and outputs the results to the OIS D/A driver IC (IC902) (serial data). The OIS driver IC (IC902) outputs the pulse signal for driving the motor of the blurring correction shift lens. One of the important factors deciding the effects of OIS is the software program. We have performed a large number of experiments to investigate this point, and the best possible correction program has been developed and incorporated in the CPU. (3) Countermeasures against Malfunctions With both autofocusing and OIS control, the key is the digital data and the software program incorporated in the lens CPU. Even when the signal lines can be observed in servicing, it is difficult to analyze the operations. When analyzing malfunctions in stores, one should observe the changes in the analog signals (including voltage) at the input from and the output to the lens. CN901 is the point of concentration of all information exchanges between the lens and Main board. To check the operations and determine their availability, it is necessary to observe the signal pins of this connector. However, note that the lens is an assembly part. This means that it should be replaced as a whole assembly except for some parts.
8-7
MAIN Board LENS CTL Block Diagram
VREF_A,OUT_A VREF_B,OUT_B
Analog Process (Comparator)
GYRO_X GYRO_Y GYRO_SW
CN901
[IRIS]
HOLE OUT(-),HOLE IN(-) HOLE OUT(+),HOLE IN(+)
FZCS DACDATA DATASCK
[Focus] FMT+,FMT[Zoom] ZBP,ZAP,ZBN,ZAN OISCS
Focus/Zoom Driver (IC901) LENS CPU (IC905)
LENS_RX IRIS_POSI
LENS_TX LENS_RX LENS_CS ZOOM_MODE IRIS_CTL IRIS_BIAS TOP ZOOM TELE TOP ZOOM WIDE ZOOM
[OIS]
(9) XCOIL+ (8) XCOIL(7) YCOIL+ (6) YCOIL-
Camera CPU (IC402)
LENS ASS'Y
XDR(+),(-) YDR(+),(-)
GYRO Sensor
OIS Driver (IC902)
MAD(15:0)
AF/Zoom DSP (IC906) G A/D
AFE_R(11:0) AF_H,V,CLK AFY0:8) AFE_G(11:0) AFDATA(0:8) Pin(21)-(29)
R A/D
AFE_B(11:0)
PLD (IC561)
B A/D
9bit
Analog Front End Block
Fig. 8-3-2 Main Board LENS CTL Block Diagram
8-8
8.4
CONCEPT OF IMAGE STABILIZER SYSTEM
Entire effective image area of CCD Area usually used Assuming that the camera is vibrated toward the bottom left of the object, the area capturing the object accurately in the entire imaging area of the CCDs is only the area shown by this figure. Therefore, this area is trimmed and enlarged to correct the image stabilization due to any slight shake of the camera. The center area of the CCD imaging area is used when camera shake does not occur.
8.4.1 Image stabilizer system function The new lens assembly used in this model incorporates an optical image stabilizer system. Compared to the electronic image stabilizer system used frequently in other camcorders that are commercially available, the system is better suited to lessen the video quality degradation and is therefore suitable for professional applications. In the following, the differences between electronic and optical image stabilizer and models of correction method will be described. 8.4.2 Differences between electronic and optical image stabilizer (1) Comparison table of electronic and optical techniques
Write of the entire image in memory
Trimming and readout If camera shake occurs, the image data of the area to be corrected is trimmed and enlarged.
Enlargement and video output
Cost Volume Weight Video quality
Main applications
Electronic Low Small Light Resolution is degraded because trimmed images are enlarged in the display. Suitable for compact consumer camcorders.
Optical High Large Heavy Little degradation in resolution thanks to optical correction inside the lens. Suitable for professional camcorders.
Enlargement before the video output resultsin slight graduation in the image resolution.
Image without correction
Image after correction
Fig. 8-4-1 Electronic Image Stabilizer System (In Cases when Camera Shake Occurs) (3) Optical image stabilizer The optical image stabilizer device is more complicated than the electronic image stabilizer device. However, the advantage of the optical technique, which is the absence of resolution degradation causes the technique to be applied in highend type consumer-oriented camcorders as well as in handheld professional camcorders. When the camera (the whole camera including the lens) is deviated from the intended light axis due to a slight movement of the hand, optical image stabilizer corrects the light axis error optically using the lens. Its correction method can roughly be divided into "shift correction" and VAP (Vari-Angle Prism)" methods. The lens used with the GY-DV300 incorporates the optical image stabilizer system of the shift correction type. The shift type image stabilizer corrects the light axis error from the object due to slight movements of hands by displacing the position of the built-in correction optics. It is called the shift type technique because it shifts the correction optics in the up-down and left-right directions.
(2) Electronic image stabilizer In general, electronic image stabilizer loads the video signals from the CCDs into memory, compares the current and the next images and determines whether the camera is panned/tilted or has been shaken by assessing the quality of the image. This technique trims the image area to be used (the image containing the intended object) from the original image that is captured in a larger size than required. (This is possible because the CCDs receive the images through the light reflected from their whole surface). The enlarged image is then output (because the trimmed image is slightly smaller than required). As a result, the image resolution may be degraded slightly compared to that of the image before trimming. Thanks to the implementation of corrections using an electronic circuit and control software without the need of expensive, optically complex devices, this technique features low cost and compact size, which makes it suitable for use in consumer-oriented camcorders.
8-9
Correction optics Focusing lens system Other lens systems Imaging surface (CCD) Object side
a prism that can vary the refraction direction by varying its own thickness (vari-angle prism). The prism thickness is changed instantaneously by a variangle prism, in which two sheets of glass are connected by a bellows made of a special film and a high-refractivity fluid is contained inside it.
Fig. 8-4-2 Concept of Shift Correction
Sheet glass
For instance, when the lens (and the whole camera) is oriented downward by a slight movement of the hands, an error of the light axis from the object causes the image at the CCD input to be deviated downward. In this case, the correction optics should be shifted downward to refract the light for returning the object image to the intended position (center). As slight movements in the actual camera operation occur both in the up-down and left-right directions, the correction optics should be shifted in parallel in all of the updown and left-right directions on a plane that is orthogonal to the light axis.
High-refractivity fluid
Bellows
Fig. 8-4-4 Cross-Section of a Vari-Angle Prism
Camera shake
Fig. 8-4-5 Operation When Camera Shake Occurs When the optics (including the camera) is tilted, the light axis is corrected by controlling the prism so that the bellows structure is varied and the light axis is refracted in the desired direction as shown in Fig. 8-4-5. The advantage that the VAP method presents is that it does not require the space for allowing the correction optics shifting (space for the up-down and left-right shifting). It is said that the correction effects of the shift and VAP methods are almost identical. In consequence, they are usually selected according to the type of the lenses (optics) in use. As described above, the optical image stabilizer method corrects the light axis errors by refraction in the optical lenses (in a manner than can be called an analog correction). Thus it can deal with slight movements of a wide range of frequencies and uses the entire optical image received by the CCDs without quality degradation. It is therefore regarded to be suitable for use in professional-oriented cameras.
Control motor Image stabilizer system block
Fig. 8-4-3 Electronic image stabilizer detects camera shake from changes (correlations) in the images written in memory, determining the movement direction, movement amount and whether each change is due to a slight movement of the hands or panning/tilting of the camera. Meanwhile, optical image stabilizer uses gyro sensors incorporated in the lens and corrects the changes in the X/Y directions of the image by controlling two motors for shifting the correction lenses based on the direction and acceleration information obtained from the gyro sensors. Another optical correction method, though not employed in the GY-DV300, is the VAP method. While the shift correction refracts the light axis by shifting the correction optics (lenses), this method refracts and modifies the light axis using
8-10
8.5
BLEMISH COMPENSATION
8.5.1 Outline The GY-DV300 adopts a new blemish compensation technique to improve the correction accuracy. This function corrects blemish (spots caused by high signal levels) produced in CCDs in a digitally, using a memory. This function is used only after replacement of the optical block assembly or when a CCD produces new blemish, and is not used usually. Detection of the blemish to be corrected can be performed using a service menu (see section 1.8). 8.5.2 Detection Blemish is detected by the DSP (IC621) and PLD (IC561) on the Main board. A pixel on which blemish is produced outputs the signal even when no light is irradiated on it (dark current) so the level of the corresponding area becomes permanently high. The DSP sets a detection level and corrects the blemish exceeding that level. The maximum number of correctable blemish errors is 32 including all of the RGB channels (16 in the case where there is more than one on a single line). Blemish with composite output levels higher than 50 mV is corrected in priority. When the detected number exceeds 32, blemish detection is performed again by setting a higher detection level. The detected positions are reset every time detection is performed (ERROR DETECT EXECUTE). The blemish position data is stored in the SDRAM in the DSP and the CPU read in it and stored in the EEPROM (IC406). The CPU sends the address data of the positions to the DSP every time the power is turned on. The blemish detection area is equal to the effective video pixel area but 8 pixels on the left and right are not corrected with any line. The correction effect is reduced in the case of successive blemish (blemish errors on adjacent pixels). Caution The camera enters the LoLux mode and the lens iris is forced to close during detection. If the iris is not closed and light is incident on the CCDs, the message "LENS NOT CLOSED ?" is displayed on the LCD or viewfinder screen and the operation terminates in a detection error.
Video signal (Iris closed)
LoLux
Increase in detection level Max. 128 cycles If > 32
Detection
Blemish positions
Blemish correction
Fig. 8-5-1 Blemish Detection Flow Chart
Set as corrected positions
Blemish level
Blemish position
Detection level
Composite output of 50 mV
Not detected as blemish
Fig. 8-5-2 Blemish Detection Level
8.5.3 Correction At the moment power is turned on, the blemish position data stored in the EEPROM (IC406) is sent to the blemish correction block in the DSP through the SD RAM (IC622) for real-time blemish correction. Since blemish correction is performed in the LoLux mode, correction is always applied on a per-pair basis covering two pixels at a time. As shown in Fig. 8.5.3, for the pixel with blemish (P2) and the adjacent one located at its left or right, the average value of the pixels two positions down of each pixel is calculated and applied as the correction signal to each pixel.
L1 Blemish pixel LoLux pairs P4 P5 P6 P0 P1 P2
L2
L3
P0 LoLux pairs L1
P1
P2
P3
P3
P4
P5
P6
L2
L2
(P0 + P4) /2 (P1 + P5) /2
Detection in the LoLux mode results in the simultaneous detection of 2 pixels as a pair (L1, L2, L3,....).
Correction of the blemish pixel (P2) and the adjacent pixel on the right (P3)
Fig. 8-5-3 2-Pixel Blemish Correction 8-11
8.6
DVC CIRCUIT
8.6.1 DV IC IC5 (JCY0176) IC5 on MAIN board is the DSP for processing DVC signals. The feature of this IC compared to the circuitry of previous models such as the GY-DV500 is the single-chip implementation of the signal interface (DVIO), compression circuit (COMPRESS), shuffling circuit (SHUFFLE), error code correction (ECC), modulation/ demodulation (DCI), IEEE1394 interface, PLL circuit, auto tracking circuit (ATF) and SDRAM function. (1) Previous circuit configuration (GY-DV500)
FROM CAMERA
DVIO
COMPRESS/ AUDIO/SHUFFLE
ECC/DCI/ATF
TO PRE/REC
PLL
IEEE1394
Fig. 8-6-1
(2) New, single-chip DV IC (GY-DV300)
DV CPU
VIDEO IN VIDEO OUT AUDIO IN AUDIO OUT DVC NEW IC REC DATA RF IN
IEEE1394 BUS LINE
Fig. 8-6-2
8-12
(3) Block diagram and signal flow The video signals input from the camera signal processor are compressed and shuffled. The AUX data and sub-code data (time codes) are input through the HOST I/F. After addition of error correction codes to all of these signals, they are coded for tape formatting and recording, and sent as the REC data to the PRE-REC processor (IC1). In tape playback, the played analog signal is input from the PRE-REC amp (IC1) and supplied via the A/D, waveform equalizer, clock reproduction, Viterbi decoding, and then goes through the error correction circuits to output the video, audio, sub-code, and AUX data. This DSP also has a built-in IEEE1394 bus. The DVC DSP (JCY0176) is composed of the following blocks. Its block diagram is shown in Fig. 8-6-3.
1. Video I/F block: Base-band video signal processing 2. Audio I/F block: Audio signal input/output interfacing 3. Compressor block: Video signal compression/expansion processing 4. ECC block: Error correction 5. Formatter block: Tape formatting 6. Digital equalizer block: Waveform equalization, PLL and Viterbi decoding processing 7. Host I/F block: Interfacing with external CPU 8. AUX data processor block 9. Sub-code processor block 10. IEEE1394 I/F block (1394PHY) 11. Timing control block 12. DRAM I/F block 13. EXT I/F block
MULTIPLEX BUS
HOST I/F
TIMING CONTROL EACH BLOCK
VCO
CLK
SUBCODE
AUX EACH BLOCK
REC OUT
FORMATTER
ECC SDRAM 5Mbit
COMPRESS DECOMPRESS
SDRAM
VIDEO I/F
VIDEO DATA
RF IN
A/D
DIGITAL EQUALIZER
AUDIO I/F
AUDIO DATA
CLK CNV
EXT I/F
1394PHY
EXT BUS
1394BUS
REC SIGNAL PLAY SIGNAL
Fig. 8-6-3 DVC DSP Block Diagram
8-13
(4) Package IC5 is a CSP (Chip Size Package) type IC with 288 pins. The CSP is an IC package featuring high density and the capability of wiring via the shortest pathways. It is connected to the circuit board by means of a solder ball. Ball pitch: 0.75 mm Package size: 18 mm x 18 mm Ball diameter: 0.45 mm
18.00
1.25 [Mounting height]
0.75 TYP
15.75 INDEX
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
ABAA Y W V U T R P N M L K J H G F E D C B A
INDEX
Fig. 8-6-4
A B C D E F G H J K L M N P R T U V W Y AA AB
1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 1
2 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 23 2
3 83 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 105 24 3
4 82 159 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 179 106 25 4
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 158 157 158 155 154 153 152 151 150 149 148 147 148 145 144 143 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 288 287 286 285 264 283 282 281 280 279 278 277 278 275 274 211 273 210 272 209 INDEX 271 208 270 207 269 206 268 205 Top View 267 204 FJ pin-Ball Correspondence Table 266 203 (288 pins) 265 202 264 201 263 200 262 199 261 198 260 197 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 196 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
21 65 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 42 21
22 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 22
A B C D E F G H J K L M N P R T U V W Y AA AB
Fig. 8-6-5
8-14
8.6.2 IC1 (JCY0132) IC1 on the Main board is the recording/playback amp IC.
Fig. 8-6-6
8-15
8.6.3 Audio Circuitry (1) Signal flow The input microphone signals include the MIC1, MIC2 and built-in MIC. The reference input level of MIC1/MIC2 is -56 dBs and built-in MIC is -40 dBs. The MIC1 and MIC2 inputs are phantom microphone compatible so that +48 V DC can be supplied. The MIC signal inputs are sent to amplifiers for level boosting to -25 dB. Then, the built-in MIC and MIC1 are input to IC708 to be selected. After this, the signal is sent through the channel switch IC708 and input to ALC/ VRs 701 and 702. VRs 701 and 702 are audio recording level controls that are effective in Manual mode. ICs 706 and 707 are the ALC circuit that are effective in Auto mode. The signal is then sent through the ATT for level attenuation to -32 dB, and input to pins 54 and 59 of IC711 (AK4560AVQ), which amplifies the signal to the reference recording level of -12 dB. The signal is then A/D converted and output at pin 29 to become the REC DATA signal. In playback, the digital data is input from pin 30, D/A converted and output at pins 19 and 21. The signal is then amplified from -12 dB to -8 dB before going to the camera output terminal. IC711 uses MCLK, LRCLK and BCLK as clocks. They are not synchronized with the video signal so the GY-DV300 does not have the audio lock function. (2) Clock signals for audio data
MCK (Master Clock) Sampling frequency REC 48kHz 32kHz 48kHz 44.1kHz 32kHz BCK (Serial Clock) Sampling frequency REC 48kHz 32kHz 48kHz 44.1kHz 32kHz LRCK (LR Clock) Sampling frequency REC 48kHz 32kHz 48kHz 44.1kHz 32kHz DOLRCK 48kHz 32kHz 48kHz 44.1kHz 32kHz DOBCK 36fs : 1.536MHz 36fs : 1.024MHz 36fs : 1.536MHz 36fs : 1.4112MHz 36fs : 1.024MHz DOMCK 256fs : 12.288MHz 384fs : 12.288MHz 256fs : 12.288MHz 256fs : 11.2896MHz 256fs : 8.192MHz
PLAY
PLAY
PLAY
Table 8-6-1
8-16
LINE
+
+
DVC IC (IC5) (AUDIO DATA) 35 36
CLOCK DRIVER AUDIO I/F CONTROLLER
+
8-17
TP708 AMP TP709
METER OUT CH2
AMP Q705, 706 TP704 IC709 MIC2(H) MUTE SW TP707 LINE MUTE(H) TP706
TO : SYSCON CPU METER OUT CH1
IC708 ATT ALC ATT IC706 15 VR701
IC708 MANUAL(H)
IC705
XLR(H)
Built-in MIC AU SIG CH-1
HPF
AMP
TP701
AUTO
AU SIG CH-2
LINE OUT
TRAP
MANUAL
IC710 CH SEL CH2(L) IC709 MIC2(H) (on) IC710 (on) (off) TP705
MIC-1 (XLR)
AMP
IC701, 702
+48V_ON
+48V
ATT ALC ATT IC707 TP703 14 IC708 MANUAL(H)
+48V_ON
IC703, 702
TP702
AUTO ATT
14 (off) MIX(H)
MIC-2 (XLR) MANUAL 59 54
L-CH R-CH AMP AMP Rch ALC AMP MIC 9k 164k LINE +6.9dB AMP LOUTP AMP +6.9dB AOUT1 AOUT0 AOUT1 AMP HPF IC707 HPF ON(H) HPF AMP AMP Lch ALC AMP MIC
AMP
MIX ATT
VR702
IC709 HPF ON(H)
64 4
49 45 44 11, 13
(on) (off)
HPF
(on) (off)
5
164k
9k
MIX MIX
21 19
SPPS
38, 40 HP_DET
MOUT ALCS HP Q707, 708, 709
REC ADATA 30 34
DAC
29
ADC
AOUT0
SPEAKER
PB ADATA
BCK
Output PGA
AMP
AMP
MUTE SW
3.5 ST 25
AMP BEEPS BEEPH
PHONES
LRCK 37 14 31 32 33
CONTROL REGISTER I/F
MCK
HP_MUTE
PD_L BUZZER
(POWER DOWN & RESET)
CNT_CLK_I
IC711 (AK4560AVQ)
CONTROL DATA INTERFACE
CNT_CS
CNT_DAT_IO
Fig. 8-6-7
(3) Pin functions of IC711 (AK4560AVQ)
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pin Name EQ_P_L EQ_O_L HPF_O_L HPF_O_R MIC_IN_L VCOM VREF AGND VA ROUT2 OPGR LOUT2 OPGL BEEP SHT MOUT MIN LIN LOUT1 RIN ROUT1 HVCM HVDD HPR HPL MUTE VD DGND MVDD SDTI CDTIO CS CCLK BCLK LRCK MCLK PD SP0 ND SP1 INT EXT DET SVSS SVDD MIC_IN_R HPF_ P_R HPF_ N_R EQ_O_R EQ_P_R EQ_N_R PRE_O_R PRE_N_R MPWR EXT_MIC_R INT_MIC_R MRF MVCM MVSS MVDD INT_MIC_L EXT_MIC_L MIC_B PRE_N_L PRE_O_L EQ_N_L I/O I O I O I O O O I O I I I O I I O I O O O O I O I I/O I I I I I I O I O I I O I O I I O O O I I O O I I I I O I Function Lch EQ-Amp Positive Input Pin Lch EQ-Amp Output Pin Lch HPF-Amp Positive Input Pin Lch HPF-Amp Output Pin Lch MIC Input Pin Common Voltage Output Pin ADC, DAC Reference Level Analog Ground Pin Analog Power Supply Pin, +2.8V Rch #2 Line Output Pin Rch Analog Volume Input Pin Lch #2 Line Output Pin Lch Analog Volume Input Pin Beep Signal Input Pin Shutter Signal Input Pin Analog Mixing Output Pin ALC2 Input Pin Lch Line Input Pin Lch #1 Line Output Pin Rch Line Input Pin Rch #1 Line Output Pin LINEOUT & HP-Amp Common Voltage Output Pin LINEOUT & HP-Amp Power Supply Pin, +4.5V Rch Headphone-Amp Output Pin Lch Headphone-Amp Output Pin Mute Pin, "L": Normal Operation, "H": Mute Digital Power Supply Pin, +2.8V Digital Ground Pin Audio Serial Data Output Pin Audio Serial Data Input Pin Control Data Input/Output Pin Chip Select Pin Control Clock Input Pin Audio Serial Data Clock Pin Input/Output Channel Clock Pin Master Clock Input Pin Power Down & Reset Pin, "L":Power Down & "H": Normal operation Speaker Amp positive Output Pin Noise Decrese Pin, "L": Disable. "H": Enable Speaker Amp negative Output Pin Internal/External MIC Detect Pin, "L": Internal MIC, "H": External MIC Speaker Amp Ground Pin Speaker Amp Power Supply Pin, +4.0V Rch MIC Input Pin Rch HPF-Amp Output Pin Rch HPF-Amp Positive Input Pin Rch EQ-Amp Output Pin Rch EQ-Amp Positive Input Pin Rch EQ-Amp Negative Input Pin Rch Pre-Amp Output Pin Rch Pre-Amp Negative Input Pin MIC Power Supply Pin External MIC Rch Input Pin Internal MIC Rch Input Pin MIC Power Supply Ripple Filter Pin MIC Block Common Voltage Output Pin MIC Block Ground Pin MIC Block Power Supply Pin Internal MIC Lch Input Pin External MIC Lch Input Pin MIC-Amp Bias Pin Lch Pre-Amp Negative Input Pin Lch Pre-Amp Output Pin Lch EQ-Amp Negative Input Pin
Table 8-6-2 8-18
8.7
SYSTEM CONTROL
8.8
LCD MONITORING DEVICES
8.7.1 CPU configuration The GY-DV300 has four CPUs, which control the functions as described below. Each CPU incorporates flash memory. The program can be rewritten by a flash programmer under the CPU onto the circuit board. (1) Sys-Con CPU (A/L/S IC401) 16-bit, single-chip microcomputer Functions · Video/audio mode control · EEPROM management · RTC (Real Time Clock) control · Operation control · LCD/VF control · NETWORK PACK (KA-DV300 : Optional) control · Power control (2) Camera CPU (MAIN IC402) 16-bit, single-chip microcomputer Functions · Camera process circuit control (3) Lens CPU (MAIN IC905) 32-bit microcomputer Functions · Focusing/zoom/iris control · OIS (Optical Image Stabilizer) control (4) MSD CPU (MAIN IC3) 32-bit microcomputer. Functions · Mechanism control/servo control · IEEE1394 interface control
The GY-DV300 provides a color LCD monitor and color LCD viewfinder. 8.8.1 LCD monitor (1) Outline The LCD monitor is an active matrix panel with a diagonal size of 6.2 cm incorporating built-in drivers, made using lowtemperature, polycrystalline silicon transistors. It is capable of a full-color display in both NTSC and PAL formats. It employs the delta array and provides even pictures, which do not present fixed color patterns as in other arrangements with vertical stripe and mosaic pattern. Features · 200,000 display dots, diagonal size 6.2 cm (2.5") · Horizontal resolution 440 lines · Light transmittance 8.2% (typical) · High contrast ratio of 200 (typical) thanks to the normally white mode · H and V drivers built in (with input level converter circuit, 3 V drive possible) · Smooth pictures with a RGB delta arrangment. · NTSC/PAL compatibility · High picture quality circuit · Up-down and left-right inverted display function · 16:9 wide-screen display function · Surface stain treatment Device structure · Active matrix TFT-LCD panel with built-in drivers, using low-temperature polycrystalline silicon transistors · Number of pixels Total number of dots : 884(H) x 230(V) = 203,320 Number of display dots: 880(H) x 228(V) = 200,640 · Panel dimensions Max. dimensions : 57.8(W) x 47.85(D) x 2.2(H) mm Effective display dimensions : 49.94(H) x 37.34(V) mm
8-19
A/L/S BOARD
IC401 SYSCON CPU JOG
JOG INPUT MSD CPU COMMUNICATION DV IC CONTROL SYSCON COMMUNICATION
IC3 IC1 MSD CPU
PRE/REC CONTROL
TEMP MS_BUS DV IC MPX
MODE CONTROL
TEMP SENSOR RST RST
IC5
PRE/REC IEEE 1394
OPERATION
KEY CONTROL
EEPROM CONTROL
KEY SCAN EEPROM IC405
RTC CONTROL
IC428, IC429
SIO IC406
Key Scan IC RTC
ABST CONTROL
MECHA SENSORS
POWER CONTROL
POWER CONTROL MODE CONTROL TCG MECHA/ SERVO CONTROL
IC5501 MDA IC5502 MDA VF
LOADING MOTOR DRUM MOTOR CAPSTAN MOTOR
REGURATOR IC302
AUDIO CONTROL LCD CONTROL
A CONTROL DRIVER LCD IC301
VIDEO CONTROL VF CONTROL
AUDIO
METER SIGNAL DRIVER IC410 RESET
ADJUSTMENT CONTROL NuCore CPU COMMUNICATION TCCS CONTROL Adapter
HOUSING MOTOR
VIDEO
V CONTROL
IC404 SIO
S I O
DV MDA BOARD
OSD
OSD CONTROL
IC901 TCCS
S I O
AF/ZOOM/IRIS DRIVER IC907
EEP ROM
NETWORK PACK CTL
VD
IC905 SIO IC402
CAMERA CPU COMMUNICATION
RST CAMERA CPU
IMAGE CALCULATION LENS CONTROL
LENS CPU
LENS UNIT SIO
IC902
IC622 SDRAM
OIS DRIVER
MODE CONTROL OUTPUT DRIVER OUTPUT DRIVER
IC621 RST DBE
IC561 PLD
IC562 ROM
CN561 PLD DOWNLOAD
ADJUSTMENT IC407 SIO
D/A
AFE-R IC502
AFE-G IC503
AFE-B IC501
MAIN BOARD
Fig. 8-7-1 SYSCON BLOCK DIAGRAM
8-20
(2) LCD MONITOR block diagram and pin functions
H-LEVEL SHIFTER & SHIFT REGISTER
COM
V-SHIFT REGISTER
CS
LC
LEVEL SHIFTER COM ELECTRODE 1 2 3 4 5 6 7
BOOST VOLTAGE GENERATOR NEGATIVE VOLTAGE GENERATOR
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VCK
TESTL
DWN
VST
EN
VDDG
COM
VDD
VSS
SLVSG
WIDE
HST
VSSG
TEST
REF
Cext/Rext
HCK2
GREEN
Fig. 8-8-1
8-21
TESTR
HCK1
PSIG
RED
BLUE
RGT
Pin description
Pin No. 1 2 3 4 5 Symbol TESTL COM VST VCK EN Description Panel test pin output Common voltage input terminal Pulse input terminal for V-shift register drive start Clock input terminal for V-shift transistor drive Gate select pulse enable input terminal Drive direction signal input terminal of V-shift register H : Normal direction, L : Opposite direction H/V driver power input terminal H/V driver GND terminal Terminal for setting power voltage boost for the V driver Negative power setting terminal V driver Negative power control terminal. H: Negative power ON. L: Negative power OFF. 16:9 mode pulse input terminal Pin No. 13 14 15 16 17 Symbol HST REF TESTL Cext/Rext HCK2 Description Start pulse input terminal for H-shift register drive Level shifter reference voltage input terminal Panel test terminal output (This should be Open.) Time constant power input terminal for H-shift register drive Clock input terminal for H-shift register drive Clock input terminal for H-shift register drive Uniformity improvement signal input terminal Panel video signal (G) input terminal Panel video signal (R) input terminal Panel video signal (B) input terminal Drive direction signal input terminal of H-shift register H : Normal direction, L : Opposite direction Panel test terminal output (This should be Open when in use.)
6
DWN
18
HCK1
7 8 9 10
VDD VSS VDDG VSSG
19 20 21 22
PSIG GREEN RED BLUE
11
SLVSG
23
RGT
12
WIDE
24
TESTER
Table 8-8-1
8-22
H Circuit Standard Timings
NTSC 4:3 (Even lines)
5.0µs HST HCK1 HCK2 1.3µs FRP
VCK 2.5µs 3.1µs
EN WIDE
1.1µs
1.9µs
V Circuit Standard Timings
NTSC 4:3 (Even fields)
VST
VCK
FRP HST EN WIDE
NTSC WIDE (Even fields)
VST
VCK
FRP
HST
EN
WIDE
Fig. 8-8-2 Timing Chart
8-23
(3) Operation description 1 Color-coding The color filters are coded in a delta arrengement. The areas masked in the figure are not displayed.
Gate SW
Gate SW
Gate SW
Gate SW
Gate SW
Gate SW
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G B Display area B R G
R
G
B
R
G
B
R
1
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R 2 880 884 2
Fig. 8-8-3
2 Description of LCD panel Operatins
· A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse to each of 228 line electrodes sequentially one line electrode at a time in a single horizontal scanning period. · The selected pulse is output when the enable pin goes to high level. PAL signal pulse elimination display and 16:9 mode pulse elimination display are possibly by using the enable pin and simultaneously controlling VCK. · A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuitry, applies selected pulses to each of 880 signal electrodes sequentially in a single horizontal scanning period. These pulses are used to supply the sampled video signal to the row signal lines. · The scanning direction of the horizontal shift registers can be switched with the RGT pin. The scanning direction is left to right (right scan) for RGT pin at high level (2.6 to 5.5 V), and right to left (left scan) for RGT pin at
low level (0 V). In addition, the scanning direction of the vertical shift registers can be switched with the DWN pin. The scanning direction is top to bottom for DWN pin at high level (2.6 to 5.5 V), and bottom to top for DWN pin at low level (0 V). (These scanning directions are from a front view.) · The vertical and horizontal drivers address one pixel, and then thin film transistors (TFTs ; two TFTs for one pixel) turn on to apply a video signal to the pixel. The same procedures lead to the entire 228 x 880 pixels to display a picture in a signal vertical scanning period. · Pixel are arranged in a delta pattern, where sets of RGB pixels are positioned shifted by 1.5 dots against adjacent horizontal lines. The horizontal driver output pulse must be shifted by 1.5 dots for each horizontal line against the horizontal sync signal to apply a video signal to each pixel properly. · The video signal is input with the polarity-inverted every horizontal cycle.
1
228
230
8-24
8.8.2 LCD viewfinder (1) Outline The LCD viewfinder is an active matrix panel with a diagonal size of 1.1 cm incorporating built-in drivers, which are made using polycrystalline silicon thin film transistors. It is capable of full-color display in both NTSC and PAL formats. It employs the delta array and provides even pictures, which do not present fixed color patterns as in the other arrangements that use the vertical stripe and mosaic arrangements. Features · 180,000 display dots, diagonal size 1.115 cm (0.44") · Horizontal resolution 400 lines · Light transmittance 4.0% (typical) · High contrast ratio of 200 (typical) thanks to the normally white mode · H and V drivers built in (with input level converter circuit, TTL drive possible) · Smooth picture thanks to the RGB delta array · Full-color display · NTSC/PAL compatibility · 4:3 and 16:9 aspect ratio switching function · LCD VF has Up-down and left-right inverted display function. Those functions, however, are not used with GYDV300. Device structure · Number of pixels Total number of dots: 827(H) x 228(V) = 188,556 Number of display dots: 800(H) x 225(V) = 180,000 · Active matrix panel with built-in drivers, using polycrystalline silicon thin-film transistors
8-25
(2) Block diagram and pin functions
HCK2 HCK1 DWN BLUE GREEN COM RGT BLK RED VCK EN HST VST STB VDD VSS
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LEVEL SHIFTER
H-SHIFT REGISTER
TOP/ BOTTOM BLK CONTROLLER LEVEL SHIFTER
V-SHIFT REGISTER
CS
LC
COM ELECTRODE
Fig. 8-8-4 Pin description
Pin No. 1 Symbol COM Description Panel opposed voltage input terminal Pin No. 9 Symbol RGT Description Drive direction signal input terminal for H-shift register H: Normal direction. L: Opposite direction. Drive direction signal input terminal for V-shift register H: Normal direction. L: Opposite direction Gate select pulse enable input terminal Input terminal for Power save mode control Clock input terminal for V-shift transistor drive Start pulse input terminal for V-shift register drive H/V driver GND terminal H/V driver power input terminal
2
GREEN
Panel video signal (G) input terminal
10
EN
3 4 5 6 7 8
RED BLUE BLK HCK1 HCK2 HST
Panel video signal (R) input terminal Panel video signal (B) input terminal Top/bottom black display pulse input terminal Clock input terminal for H-shift register drive Clock input terminal for H-shift register drive Start pulse input terminal for H-shift register drive
11 12 13 14 15 16
STB VCK VST VSS VDD
Table 8-8-2 8-26