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August 1997
FDC6303N
Digital FET, Dual N-Channel
General Description Features
These dual N-Channel logic level enhancement mode field 25 V, 0.68 A continuous, 2 A Peak.
effect transistors are produced using Fairchild's proprietary, RDS(ON) = 0.6 @ VGS = 2.7 V
high cell density, DMOS technology. This very high density RDS(ON) = 0.45 @ VGS= 4.5 V.
process is especially tailored to minimize on-state
resistance. This device has been designed especially for Very low level gate drive requirements allowing direct
low voltage applications as a replacement for digital operation in 3V circuits. VGS(th) < 1.5 V.
transistors in load switching applications. Since bias Gate-Source Zener for ESD ruggedness.
resistors are not required this one N-Channel FET can >6kV Human Body Model
replace several digital transistors with different bias
resistors like the IMHxA series. Replace multiple NPN digital transistors (IMHxA series)
with one DMOS FET.
SOT-23 SuperSOTTM-6 SuperSOTTM-8 SO-8 SOT-223 SOIC-16
Mark: .303
4 3
5 2
6 1
Absolute Maximum Ratings T A = 25