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5 4 3 2 1
ZI3 SYSTEM BLOCK DIAGRAM
PCI ..CLOCK
CK-GEN 3V
AMD Processor ( Socket A ) VCC_CORE
ICS950902 2.5V DC/DC
P4,5 P3 19V IN
D D
P27,28
ADDR
CTRL
DATA
5V,3V,CPUCORE VCC etc.
POWER IN Battery
ADDR
CTRL
DATA
5V
Charger
P29,30
CRT
P15 EXT. VGA AGP BUS
ATI M9+X DDR
200/266/333/400MHZ
TV-OUT North Bridge DIMM H/W
P15
VIA KN400 THERMAL DIODE IN MONITOR
P22
VIN INTA 2.5VSUS
2.5V SMDDR_VTERM
LCD/INV 3.3V P33,34,35,36,37,38 VCC_CORE
1.5V
DDR
CONN P14 2.5V
2.5VSUS
DIMM
3.3V P6,7,8 P10
C 2'nd FAN C
P22
CH7019
TV ENCODER V-LINK
& LVDS P14 266/533MB/s
5V
HDD UltraDMA 100/133 PCI BUS
P21
South Bridge
CD-ROM
5V
VIA VT8235
P21
3V
3VSUS MII
USB
5V
USB 2.0 2.5V
RVCC
LAN PHY PCMCIA 1394 MINI-PCI
P11,12,13
CONN VT6103 3V
TI1410 TSB43AB21 3V
P22
3V_LAN P25 3VSUS 3V 3VSUS
5VSUS 5VSUS
12V
B
INTB INT C/D B
INTB REQ1 REQ2
REQ0 GNT1 GNT2
AC97 RJ45 GNT0 AD19 AD20
AD18 P18 P23 P24
Audio Realtek SIO
P25
Amplifier AC'97 Link PC87393
ALC202 3V
G1421 3V
Primary P16
1394
5V P20 5V P19 Slot0
CONN
P18 P23
5V 3V
EC/KBC LPT FIR
PC87570 Port P17 P16
RJ11 MDC AC'97 Link 5VPCU P26
3V_MODEM
P25 5V Secondary
3VSUS
P19
A A
LED/B Touch BIOS Keyboard FAN PROJECT : ZI3
CONN Pad
5V P17 5V P17 5VPCU P26 P16 5V P22 Quanta Computer Inc.
Size Document Number Rev
Custom Block Diagram 1A
Date: Wednesday, September 24, 2003 Sheet 1 of 38
5 4 3 2 1
1 2 3 4 5 6 7 8
A A
Voltage Rails Description ON S0~S1 ON S3 ON S4 ON S5 Control signal
VCC_CORE Core voltage for Processor X VR_ON
PCI DEVICE IDSEL# REQ/GNT# Interrupts
SMDDR_VTERM 1.25V for DDR Termination voltage X MAINON
PCI1410 AD18 -REQ0/-GNT0 -INTB
+1.8V X MAINON
TSB43AB21 AD19 -REQ1/-GNT1 -INTB
1.5VGA VGA core power X MAINON
B +1.5V X MAINON MINI-PCI AD20 -REQ2/-GNT2 -INTC/-INTD B
2.5VSUS X X SUSON ATi M9+XC -INTA
+2.5V X MAINON
3VPCU X X X X VL
3VSUS X X SUSON
+3V X MAINON
5VPCU X X X X VL
5VSUS X X SUSON
+5V X MAINON
12V X MAINON
12VOUT X X X X VL
RVCC X X X RVCC_ON
C C
VIN POWER SOURCE X X X X
D PROJECT : ZI3 D
Quanta Computer Inc.
Size Document Number Rev
A4 INFORMATION 1A
Date: Wednesday, September 24, 2003 Sheet 2 of 38
1 2 3 4 5 6 7 8
A B C D E
C224 1 2 10U/10V
+
C199 2 1 .1U
C198 2 1 .1U
C225 2 1 1000P
C226 2 1 .01U
C227 2 1 .01U
L47
DVCCLK R141 1 2 22
+3V AC97_14M (19)
1
TI201209G121 C228
4 4
1000P R485 1 2 22 APICCLKSB (13)
R493 1 2 22 GCLK14 (8)
2
U11
5 1 FS0 R502 1 2 22
VDDAGP FS0/REF0 REFCK1 14M_SIO (16)
16 56 R126 1 2 22 OSCSB (13)
L48 VDDPCI VTT_PG#/REF1
22
DVDDCLK AVDD48 FS3
+3V 23 20 R512 1 2 33 USBCLK
USBCLK (11)
VDD FS3/48MHZ FS2
55 21
VDDREF FS2/24_48MHZ
1
1
TI201209G121 C229 C230 51
VDDCPU3
+ C223 6 VCLK0 R506 1 2 33 VLCLKSB
VLCLKSB (13)
.1U L45 1 VCCLK2D5 MODE/AGPCK0
.01U +2.5V 2 0 50 VDDCPU2P5 SEL408/AGPCK1 7 GCLK0 R159 1 2 33 GCLKNB
GCLKNB (8)
10U/10V
2
1
FS1 2 33 SBPCLK
2
9 10 R508 1 SBPCLK (11)
GNDAGP FS1/PCI_F
1
+ C210 13 11 SBPCLK0
GNDPCI SEL_SD_DDR/PCI1
2
2
C200 24 12 PCMPCLK0 R161 1 2 33 PCMPCLK
GND MULTSEL/PCI2 PCMPCLK (18)
C217 C221 10U/10V .1U 19 14 LPCPCLK0 R509 1 2 33 LPCPCLK
GND48 PCI3 LPCPCLK (16)
10P 10P RPCLK_1394 33 PCLK_1394
2
2
2 15 R510 1 2 PCLK_1394 (23)
1 GND PCI4 RMINIPCLK 33 MINIPCLK
1
54 17 R511 1 2 MINIPCLK (24)
Y1 14.318MHZ GND PCI5
47 GND
52 RCPUCLK- R473 1 2 10
CPUCLKC CPUCLK- (4)
53 RCPUCLK+ R472 1 2 10
CPUCLKT CPUCLK+ (4)
48 RHCLKNB+ R475 1 2 10 HCLKNB+
CPUT_CS HCLKNB+ (6)
CKGEN14M_I 3 49 RHCLKNB- R474 1 2 10 HCLKNB-
X1 CPUC_CS HCLKNB- (6)
R149 *1M CKGEN14M_O 4 X2
BUF_IN 45 DCLKO (7)
SMDAT 28 46 DCLK_I R476 1 2 22
(10,12) SMDAT SDATA FBOUT DCLKI (7)
SMCLK 27 44 R_MCLK0+ R127 1 2 10 MCLK0+
(10,12) SMCLK SCLK DDRCKT0 MCLK0+ (10)
43 R_MCLK0- R477 1 2 10 MCLK0-
DDRCKC0 MCLK0- (10)
3 +3V R152 10K -ICSPD 26 42 R_MCLK1+ R128 1 2 10 MCLK1+ 3
RST/PD# DDRCKT1 MCLK1+ (10)
AGPCLK RAGPCLK 8 41 R_MCLK1- R478 1 2 10 MCLK1- VLCLKSB C852 1 2 *10P
(33) AGPCLK PCI_STP/AGPCK2 DDRCKC1 MCLK1- (10)
R507 33 18 38 R_MCLK2+ R479 1 2 10 MCLK2+
T78 CLK_STP/PCI6 DDRCKT2 MCLK2+ (10)
37 R_MCLK2- R480 1 2 10 MCLK2- GCLKNB C234 1 2 *10P
VCCLK2D5 DDRCKC2 MCLK2- (10)
40 36 R_MCLK3+ R482 1 2 10 MCLK3+
VDD3/2P5 DDRCKT3 MCLK3+ (10)
34 35 R_MCLK3- R481 1 2 10 MCLK3- AGPCLK C853 1 2 *10P
VDD3/2P5 DDRCKC3 MCLK3- (10)
1
1
1
1
1
DDRCKT4 32
C202 C201 C203 C204 C205 39 31
1000P .01U .01U .1U .1U GND DDRCKC4 USBCLK C847
33 GND DDRCKT5 30 1 2 *10P
2
2
2
2
2
DDRCKC5 29
25 IREF
MODE,PIN6 SBPCLK C854 1 2 *10P
(Latched Input) PIN26 PIN18 PIN8
ICS950902DG PCMPCLK C235 1 2 *10P
0 PD# CPU_STOP# PCI_STOP# R497 LPCPCLK C857 1 2 *10P
CLK_IREF
PCLK_1394 C858 1 2 *10P
1 RESET# PCICLK6 AGP2 475/F
MINIPCLK C859 1 2 *10P
VCLK0 R505 *10K
+3V
GCLK0 R158 10K
CPUCLK AGP PCICLK
FS3 FS2 FS1 FS0 MHZ MHZ MHZ
+3V
0 0 0 0 160.00 80.00 40.00 SBPCLK0 R160 10K
2 0 0 0 1 164.00 82.00 41.00 2
0 0 1 0 166.60 66.60 33.30
0 0 1 1 170.00 68.00 34.00
0 1 0 0 175.00 70.00 35.00 REFCK1 R138 10K
0 1 0 1 180.00 72.00 36.00 R513
0 1 1 0 185.00 74.00 37.00 5.1K
2
0 1 1 1 190.00 76.00 38.00
1 0 0 0 66.80 66.80 33.40 R498
1 0 0 1 100.90 67.27 33.63 10K R514 5.1K
+3V FS1
1 0 1 0 133.60 66.80 33.40
1 0 1 1 200.40 66.80 33.40
1 1 0 0 66.60 66.60 32.30 R492 10K FS3 R494 *10K
1
1 1 0 1 100.00 66.60 33.30
3
1 1 1 0 200.00 68.60 33.30
1 1 1 1 133.30 68.60 33.30 R491 10K FS2 R489 *10K 2
(5,12) FSB_SENSE
FSB CLOCK Q40
R500 *10K FS1 R496 *10K 2N7002E
1
SELECT BY FS1
R504 10K FS0 R503 *10K
CPU FSB SENSE TABLE CLKGEN SETTING CPU CLK
1 FSB_SENSE FS3 FS2 FS1 FS0 1
FS3/48MHZ : INTERNAL 120K PULL-UP RESISTOR TO VDD
0 1 1 1 1 133MHZ FS2/24_48MHZ : INTERNAL 120K PULL-UP RESISTOR TO VDD
FS1/PCI_F : INTERNAL 120K PULL-DOWN RESISTOR TO GND PROJECT : ZI3
1 1 1 0 1 100MHZ
FS0/REF0 : INTERNAL 120K PULL-UP RESISTOR TO VDD
Quanta Computer Inc.
Size Document Number Rev
Custom CLOCK GENERATOR 2A
Date: Wednesday, September 24, 2003 Sheet 3 of 38
A B C D E
A B C D E
Near socket-A
(6) -SDATA[0..63]
AMD K7 CPU 1 OF 2 VCC_CORE VCC_CORE
COREFB+ R342 10K
(28) COREFB+
U5A
-SDATA0 AA35 AE1 -A20M COREFB- R345 10K
SDATA0 A20M -A20M (13) (28) COREFB-
-SDATA1 W37 AG1 FERR R347 R353
-SDATA2 SDATA1 FERR -CPUINIT 60.4/F 60.4/F
W35 SDATA2 INIT AJ3 -CPUINIT (13)
-SDATA3 Y35 AL1 INTR
SDATA3 INTR INTR (13)
-SDATA4 U35 AJ1 -IGNNE R350
SDATA4 IGNNE -IGNNE (13)
-SDATA5 U33 AN3 NMI Near socket-A
SDATA5 NMI NMI (13)
-SDATA6 S37 AG3 -CPURST
4
-SDATA7 SDATA6 RESET -SMI VCC_CORE +3V 301/F 4
S33 SDATA7 SMI AN5 -SMI (13)
-SDATA8 AA33 AC1 -STPCLK
SDATA8 STPCLK -STPCLK (13)
-SDATA9 AE37 CPUCK+ C448 680P_NPO
SDATA9 CPUCLK+ (3)
-SDATA10 AC33 AE3 PWRGD_CPU
-SDATA11 SDATA10 PWROK R333 R332 CPUCK- C451 680P_NPO
AC37 SDATA11 CPUCLK- (3)
-SDATA12 Y37
-SDATA13 SDATA12 APICCLKCPU *1K 510
AA37 SDATA13 PICCLK N1
-SDATA14 AC35 N3 -PICD0
-SDATA15 SDATA14 PICD0/BYPASSCLK -PICD1 VCC_CORE
S35 SDATA15 PICD1/BYPASSCLK N5 -SB_FERR (13)
-SDATA16 Q37 SDATA16
3
-SDATA17 Q35 AG13 COREFB-
-SDATA18 SDATA17 COREFB- COREFB+ FERR Q26
N37 SDATA18 COREFB+ AG11 1 2 2 VREF_SYS is set at 50%
-SDATA19 J33 R590
-SDATA20 G33
SDATA19
AN17 CPUCK+ 33 MMBT2222A of VCC_CORE to CPU R344
-SDATA21 SDATA20 CLKIN CPUCK- 100/F
1
G37 SDATA21 CLKIN AL17
-SDATA22 E37