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Keysight Technologies
W2309EP/ET DDR Bus Simulator and
W2317EP/ET DDR Bus Simulator Distributed Computing 8-pack

Data Sheet
Introduction

The W2309EP/ET double data rate (DDR) Bus Simulator quickly generates accurate bit-error-rate
(BER) contours, masks, and margins between the two, for the DDR memory bus speciication pub-
lished by the JEDEC Solid State Technology Association.

The simulator achieves this by use of statistical simulation, meaning no lengthy and time-consuming
bit pattern is needed. Instead, it constructs the eye diagram from the transmitter, channel, and receiv-
er impulse responses, and from the stochastic properties of a conceptually ininite non-repeating bit
pattern. In doing so, it avoids the pitfalls associated with precarious dual-Dirac extrapolation of a
limited bit pattern from either SPICE-like simulation or from convolutional channel simulation.

Figure 1. Eye diagrams for a byte lane.

Key Features