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5 4 3 2 1
Cathedral Peak 2A Block Diagram
Project code: 91.4K901.001
PCB P/N : 48.4K901.001
REVISION : 08220- -1
PCB STACKUP
DDR2 667/800MHz
TOP
SYSTEM DC/DC
AMD Giffin CPU TPS51125 37
D 667/800 MHz
8,9
G792 INPUTS OUTPUTS
D
VCC
S1G2 (35W) 22
DCBATOUT
5V_S5(6A)
DDR2 667/800MHz
638-Pin uFCPGA638
4,5,6,7
S 3D3V_S5(6A)
667/800 MHz S SYSTEM DC/DC
8,9 CRT RT8202 X 2 38
15 GND
INPUTS OUTPUTS
OUT
BOTTOM 1D1V_S0(7.5A)
LCD
IN
16X16 DCBATOUT
14 1D2V_S0(4A)
SYSTEM DC/DC
North Bridge
CLK GEN. 3 AMD RS780M
RT8202
INPUTS
39
OUTPUTS
ICS9LPRS480BKLFT 71.09480.A03 CPU I/F LVDS, CRT I/F
RTM880N-796-VB-GRT 71.00880.A03 DCBATOUT 1D8V_S3(11A)
INTEGRATED GRAHPICS LAN
Giga LAN TXFM RJ45 RT9026PFP 39
27 27 DDR_VREF_S3
C
BCM5764 26 5V_S5 C
11,12,13 0D9V_S3
New card PWR SW RT9161 40
INT MIC 28 TPS223128
A-Link 3D3V_S0 2D5V_S0
30 PCIex1
Codec AZALIA 4X4 Mini Card
(200mA)
Kedron a/b/g/n
G957 40
ALC268 28
29 3D3V_S0 1D5V_S0
MIC In (1A)
30 South Bridge G9161 40
AMD SB700 LPC BUS
3D3V_S5 1D2V_S5
(400mA)
INT.SPKR USB 2.0/1.1 ports
ETHERNET (10/100/1000Mb) BIOS CHARGER
30 OP AMP High Definition Audio KBC MXIC
MX25L1605
LPC MAX8731 41
APA2057
30 ATA 66/100 Winbond 32 DEBUG INPUTS OUTPUTS
WPC773L CONN.32
B 31 B
Line Out CHG_PWR
ACPI 1.1
(No-SPDIF) 18V 6.0A
LPC I/F DCBATOUT
UP+5V
30 Touch INT. 5V 100mA
PCI/PCI BRIDGE
17,18,19,20,21 Pad 31 KB 31
CPU DC/DC
ISL6265HR 36
MODEM SATA USB INPUTS OUTPUTS
CardReader VCC_CORE_S0_0
RJ11 MDC Card MS/MS Pro/xD
24 Realtek 0~1.55V 18A
Mini USB /MMC/SD
RTS5158E 25 5 in 1
25 VCC_CORE_S0_1
Blue Tooth 24 DCBATOUT
0~1.55V 18A
HDD SATA
23 VDDNB
USB 0~1.55V 18A
3 Port 24
ODD SATA
A 23 A
Camera Daughter Board
om
LAUNCH Board Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
l.c
Taipei Hsien 221, Taiwan, R.O.C.
ai
08575 16
tm
Title
ho
BLOCK DIAGRAM
@
Size Document Number Rev
nf
A3 -1
Cathedral Peak 2A
ai
Date: Friday, August 22, 2008 Sheet 1 of 43
x
5 4 3 2 1
he
5 4 3 2 1
D D
C C
B B
A A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
HISTORY
Size Document Number Rev
A3 Cathedral Peak 2A -1
Date: Friday, August 22, 2008 Sheet 2 of 43
5 4 3 2 1
5 4 3 2 1
3D3V_S0 3D3V_CLK_VDD
3D3V_S0
1 R140 2 R139
0R0603-PAD 1 2 3D3V_48MPWR_S0
1
1
1
1
1
1
1
1
1
C213 C220 DY C217 C219 C216 C209 C193 C194 C211 Due to PLL issue on current clock chip, the SBlink clock
1
1
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
DY 2R3J-GP C190 C197
SC1U10V2KX-1GP need to come from SRC clocks for RS740 and RS780.
DY
2
2
2
2
2
2
2
2
2
Future clock chip revision will fix this.
SC4D7U6D3V3KX-GP
2
2
3000mA.80ohm
D D
Clock chip has internal serial terminations
3D3V_S0 for differencial pairs, external resistors are
SB reserved for debug purpose.
1 R308 2
0R0603-PAD
1D1V_S0 1D1V_CLK_VDDIO C201
R154 SC27P50V2JN-2-GP
1 DY 2 R141
0R3-0-U-GP 1 DY 2 1 2
1
1
1
1
1
1
1
C230 C232 C192 C215 C200 C210 C218 3D3V_CLK_VDD X4
1
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
10MR2J-L-GP X-14D31818M-35GP
U13 82.30005.891
2
2
2
2
2
2
2
1D1V_CLK_VDDIO 2ND = 82.30005.951 C198
26 61 GEN_XTAL_IN
2
VDDATIG X1 GEN_XTAL_OUT
25 VDDATIG_IO X2 62 1 2
CL=20pF