Text preview for : F75125 Serial VID_252C Parallel VID Translator for AMD AM2 and AM2+. [rev.0.16].[2008-03].pdf part of AMD F75125 Serial VID 252C Parallel VID Translator for AM2 and AM2+. [rev.0.16].[2008-03] AMD _Chips & Cores F75125 Serial VID_252C Parallel VID Translator for AMD AM2 and AM2+. [rev.0.16].[2008-03].pdf
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F75125
Serial VID, Parallel VID Translator for AMD
AM2 and AM2+
Release Date: Mar, 2008
Version: 0.16P
Fintek Feature Integration Technology Inc.
F75125
F75125 Datasheet Revision History
Version Date Page Revision History
0.10P Jun, 2007 Preliminary version
17 Add register description
0.11P Jul, 2007
22 Company address
0.12P Jul, 2007 8 Add Electrical Characteristics
1 Correct over voltage max a\value:2.325V
0.13P Sep, 2007 16 Add VSI/VSO illustration
19 Revise register description
0.14P Oct, 2007 27 Remove "G" from ordering information
4 Add SVI output and PSI description in General Description
Add SVI output in Features
5 Add PSI in Features
6 Revise Pin Configuration
7 Add SVI output related pin descriptions in NB related pins
8 Set VID_OUT[2] and VID_OUT[3] to multi-function pins with SVC_OUT
0.15P Feb, 2008
and SVD_OUT
17 Add NB OFF code and power saving mode description
25 Add VDD and VDD_NB follow mode register
26 Add VDD0,1 and VDD_NB SVID value monitor function register
27 Add VDD timeout set register
32 Add Serial VID output application circuit
25 Register 0x08 renamed to VSI/VSO 1
26 Register 0x09 renamed to VSI/VSO 2
0.16P Mar, 2008 27 Add register 0x10 description
27 Add register 0x11 description
28 Add register 0x12 description
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F75125
Please note that all data and specifications are subject to change without notice. All the trade marks of products and
companies mentioned in this data sheet belong to their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Customers using or selling these products for use in
such applications do so at their own risk and agree to fully indemnify Fintek for any damages resulting from such
improper use or sales.
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Table of Contents
1 GENERAL DESCRIPTION ........................................................................................................................................................ 5
2 FEATURE ..................................................................................................................................................................................... 5
3 PIN CONFIGURATION .............................................................................................................................................................. 7
4 PIN DESCRIPTION..................................................................................................................................................................... 8
4.1. POWER PIN ........................................................................................................................................................................... 8
4.2. NORTH BRIDGE VOLTAGE PIN/ VOLTAGE REGULATOR SET TRAP PIN ................................................................................... 8
4.3. VID PIN ................................................................................................................................................................................ 9
4.4. POWER GOOD PIN ................................................................................................................................................................. 9
4.5. VOLTAGE SENSE INPUT/VOLTAGE SENSE OUTPUT PIN ........................................................................................................ 10
4.6. I2C INTERFACE PIN ............................................................................................................................................................. 10
4.7. MISCELLANEOUS PIN .......................................................................................................................................................... 10
5 ELECTRICAL CHARACTERISTIC........................................................................................................................................11
5.1 ABSOLUTE MAXIMUM RATINGS .......................................................................................................................................... 11
5.2 DC CHARACTERISTICS ........................................................................................................................................................ 11
6 FUNCTIONAL DESCRIPTION ............................................................................................................................................... 14
6.1 LINEAR CON PARALLEL VID INTERFACE ............................................................................................................................ 14
6.2 SERIAL VID INTERFACE ...................................................................................................................................................... 16
6.3 2-BIT BOOT CODE AND VFIXEN MODE ............................................................................................................................. 18
6.4 NORTH BRIDGE REFERENCE VOLTAGE AND ENABLE .......................................................................................................... 18
6.5 POWER SAVING MODE ........................................................................................................................................................ 19
6.6 CORE_TYPE..................................................................................................................................................................... 20
6.7 VOLTAGE SENSE INPUT/ VOLTAGE SENSE OUTPUT ............................................................................................................. 20
6.8 I2C INTERFACE ................................................................................................................................................................... 21
7 REGISTER DESCRIPTION (I2C ADDRESS = 0X5C).......................................................................................................... 22
7.1 VDDNB VOLTAGE VALUE REGISTER INDEX 00H ............................................................................................................ 22
7.2 VDD0 VOLTAGE VALUE REGISTER INDEX 01H ............................................................................................................... 23
7.3 VDD1 VOLTAGE VALUE REGISTER INDEX 02H ............................................................................................................... 23
7.4 VID KEY PROTECT REGISTER INDEX 03H ..................................................................................................................... 24
7.5 VDDNB VOLTAGE OFFSET VALUE REGISTER INDEX 04H................................................................................................ 24
7.6 VDD0 VOLTAGE OFFSET VALUE REGISTER INDEX 05H ................................................................................................... 24
7.7 VDD1 VOLTAGE OFFSET VALUE REGISTER INDEX 06H ................................................................................................... 25
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7.8 VDDNB STEP TIME REGISTER INDEX 07H ................................................................................................................ 25
7.9 VSI/VSO 1 OVER VOLTAGE SELECT READING REGISTER INDEX 08H ............................................................................ 25
7.10 VSI/VSO 2 OVER VOLTAGE SELECT READING REGISTER INDEX 09H ............................................................................ 26
7.11 VDD0, VDD1 AND VDDNB MANUAL ENABLE REGISTER INDEX 0AH .......................................................................... 26
7.12 NB_VREF VOLTAGE READING REGISTER (LSB) INDEX 0BH ...................................................................................... 26
7.13 VDDNB SVI OUTPUT READING REGISTER (LSB) INDEX 0CH .................................................................................... 27
7.14 VDD0 SVI OUTPUT READING REGISTER (LSB) INDEX 0DH........................................................................................ 27
7.15 VDD1 SVI OUTPUT READING REGISTER (LSB) INDEX 0EH ........................................................................................ 27
7.16 SLOTOCC CONTROL ENABLE READING REGISTER INDEX 0FH................................................................................... 27
7.17 VDD_NB VOLTAGE VALUE REGISTER INDEX 10H ....................................................................................................... 27
7.18 VDD0 VOLTAGE VALUE REGISTER INDEX 11H ............................................................................................................. 27
7.19 VDD1 VOLTAGE VALUE REGISTER INDEX 12H............................................................................................................. 28
7.20 VID TIMEOUT VALUE SELECT REGISTER INDEX 13H.................................................................................................... 28
7.21 CHIP ID1 REGISTER INDEX 5AH ................................................................................................................................... 28
7.22 CHIP ID2 REGISTER INDEX 5BH .................................................................................................................................... 28
7.23 VERSION ID REGISTER INDEX 5CH ................................................................................................................................ 28
7.24 VENDOR ID1 REGISTER INDEX 5DH............................................................................................................................... 28
7.25 VENDOR ID2 REGISTER INDEX 5EH ............................................................................................................................... 28
8 ORDERING INFORMATION .................................................................................................................................................. 29
9 PACKAGE DIMENSIONS (28-SSOP) ..................................................................................................................................... 29
10 APPLICATION CIRCUIT ........................................................................................................................................................ 32
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1 General Description
The Serial VID interface (SVI)/ Parallel VID interface (PVI) translator,F75125, which can translate PVI to PVI
and SVI to PVI for AMD AM2 or AM2+ platform and output a programmable reference voltage of North Bridge
voltage (VNB) to an external single phase PWM by decoding serial VID. Or, it can translate SVI to SVI and PVI
to SVI for AMD AM2 or AM2+ platform.
In the PVI output application, the F75125 can replace the hybrid (PVI+SVI) or SVI voltage regulator by the
original PVI voltage regulator controller to save the extra cost. The F75125 supports VDDIO, VDDA, and
CPU power good input, CPU_PG_IN, such as from the south bridge, SB600, to control the signal, VR_EN to
enable the VR controller. F75125 supports all AM2+ new features including CORE_TYPE and VFIXEN. The
CORE_TYPE is used to indicate AM2 or AM2+ placed, and the VFIXEN paired with SVC and SVD let voltage
regulator output a fixed voltage. In this application of the F75125, VID[5] is recommended to pull low ,so the
VID output [4:0] is corresponding to output from 0.775 to 1.550V. In concern of mapping SVI to PVI, VID table
on-the-fly tuning is constrained in 0.800V to 1.550V. The Voltage Sense Input (VSI)/Voltage Sense Output
(VSO) also provide the similar function, but the tuning range up to 2.325V.
In the SVI output application, the F75125 will issue SVI OFF code to VDD_NB to avoid VDD_NB mis-action
when AM2 is implemented. In SVI output mode, the F75125 also supports PSI (bit7 of SVI command).
The F75125 is SSOP-28 package and powered by 3.3VSB.
2 Feature
Serial VID Input to Parallel VID Output or Parallel VID Input to Parallel VID Output Translation for Parallel
VID Interface Voltage Regulator Controller
Serial VID Input to Serial VID Output or Parallel VID Input to Serial VID Output Translation for Hybrid/Serial
VID Interface Voltage Regulator Controller
Serial or Parallel VID Mapping Table Is Adjustable to Tune Voltage Regulator Controller Output.
Programmable Reference Voltage Output for North Bridge Voltage for Over or Under Voltage in PVI Output
Mode
VFIXEN, SVC, SCD Translation to PVI Voltage Regulator Realizes AM2+ Fixed Voltage Output to CPU
Function
Support CORE_TYPE Input to Indicate AMD Processor Family 0Fh,AM2 or 10h,AM2+
Support VDDIO, VDDA, CPU Power Good, CPU_PG_IN, Input to Generate Voltage Regulator Controller
Enable Signal, VR_EN, and CPU Power Good Output, CPU_PG_OUT, to CPU and Voltage Regulator.
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2 Sets of Voltage Sense Input (VSI) and Voltage Sense Output (VSO) for Over Voltage Vcore and VNB
beyond Maximum of VID Table, 1.55V.
I2C Interface Is Built-in to Fine Tune Vcore and VNB output.
Power Saving Mode Supported in Both AM2+ Platform
Powered by 3.3VSB and SSOP-28 Package
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3 Pin Configuration
Figure1. F75125 pin configuration
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F75125
4 Pin Description
P - Power pins
INst - TTL level input pin with schmitt trigger
INLV - Low level input, transient point at 0.9V
I/OD12st5V - TTL level bi-directional pin with schmitt trigger, Open-drain output with 12 mA sink
capability, 5V tolerance
I/OD12st - TTL level bi-directional pin with schmitt trigger, Open-drain output with 12 mA sink
capability.
I/OD12LV - Low level input, transient point at 0.9V , Open-drain output with 12 mA sink capability
O12 - Output pin with 12mA sink/driving capability.
OD12 - Open-Drain output pin with 12mA sink capability.
AIN - Input pin (Analog).
AOUT - Output pin (Analog).
4.1. Power Pin
Pin No. Pin Name Type Description
4 VSB3V P 3.3V stand by power
6 VDDA P VDDA input
8 VDDIO P VDDIO power
26 VSS P Ground
4.2. North Bridge Voltage Pin/ Voltage Regulator Set Trap Pin
Pin No. Pin Name Type PWR Description
In PVI output mode, reference voltage output to external
3 VREF_NB AOUT VSB3V
single phase PWM to supply VNB.
Pull high to 3,3VSB before POK, the F75125 will enter SVI
output mode, or the F75125 is set to PVI output mode.
5 NB_EN#/VR_TRAP O12 VSB3V
In PVI output mode, NB_EN# is an external single phase
PWM enable signal.
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4.3. VID Pin
Pin No. Pin Name Type PWR Description
CPU VID input pin.
10 VID_IN[4] INLV VSB3V
Special level input VIH 0.9, VIL 0.6
CPU VID input pin.
VID_IN[3] Special level input VIH 0.9, VIL 0.6
11 INLV VSB3V
SVC (Serial VID Clock)-open drain output of the
SVC_IN
processor. Connect to this pin to the processor.
CPU VID input pin.
VID_IN[2]
Special level input VIH 0.9, VIL 0.6
12 I/OD12LV VSB3V SVD (Serial VID Data)-bidirectional signal that is an input
SVD_IN and open drain output for both master and slave devices.
Connect to this pin to the processor.
CPU VID input pin.
13 VID_IN[1] INLV VSB3V
Special level input VIH 0.9, VIL 0.6
CPU VID input pin.
14 VID_IN[0] INLV VSB3V
Special level input VIH 0.9, VIL 0.6
CPU VID output pin.
15 VID_OUT[0] OD12 VSB3V
Special level input VIH 0.9, VIL 0.6
CPU VID output pin.
16 VID_OUT[1] OD12 VSB3V
Special level input VIH 0.9, VIL 0.6
CPU VID output pin. Special level input VIH 0.9, VIL
VID_OUT[2]
0.6
17 OD12 VSB3V
SVC(Serial VID Clock)-open drain output of the F75125.
SVC_OUT
Connect to this pin to the voltage regulator.
CPU VID output pin. Special level input VIH 0.9, VIL
VID_OUT[3]
0.6
18 I/OD12 VSB3V SVD (Serial VID Data)-bidirectional signal that is an input
SVD_OUT and open drain output for both master and slave devices.
Connect to this pin to the voltage regulator.
CPU VID output pin.
19 VID_OUT[4] OD12 VSB3V
Special level input VIH 0.9, VIL 0.6
4.4. Power Good Pin
Pin No. Pin Name Type PWR Description
VR disable signal input. The source is NOR S3# and
VLDT.
21 VR_DIS_IN INLV VSB3V
VR_DIS_IN < 0.6V, VR_EN goes high.
VR_DIS_IN > 0.9V, VR_REN goes low.
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CPU power good signal input, usually from the south
22 CPU_PG_IN INst VSB3V
bridge
4.5. Voltage Sense Input/Voltage Sense Output Pin
Pin No. Pin Name Type PWR Description
Voltage sensor channel 1 input for Vcore or VNB change
1 VSI_1 AIN VSB3V
use.
Voltage sensor channel 1 output for Vcore or VNB change
2 VSO_1 AOUT VSB3V
use.
Voltage sensor channel 2 output for Vcore or VNB change
27 VSO_2 AOUT VSB3V
use.
Voltage sensor channel 2 input for Vcore or VNB change
28 VSO_1 AIN VSB3V
use.
4.6. I2C Interface Pin
Pin No. Pin Name Type PWR Description
24 SCL INst VSB3V I2C interface, serial clock input pin.
25 SDA I/OD12st VSB3V I2C interface, serial data pin.
4.7. Miscellaneous Pin
Pin No. Pin Name Type PWR Description
Hardware jumper input that selects normal operation
7 VFIXEN INLV VSB3V mode or VFIX mode. When VFIXEN inserts, the voltage
regulator will enter VFIX mode.
Processor CORE_TYPE input.
In AMD NPT Family 0Fh, CORE_TYPE is floating
9 CORE_TYPE INLV VSB3V
In AMD NPT Family 10h, CORE_TYPE is tied to VSS at
package.
20 VR_EN OD12 VSB3V Active-high signal enables the VID VR
23 SLOTOCC# INst VSB3V CPU SLOTOCC# input.
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5 Electrical Characteristic
5.1 Absolute Maximum Ratings
PARAMETER RATING UNIT
Power Supply Voltage -0.5 to 5.5 V
Input Voltage -0.5 to VDD+0.5 V
Operating Temperature 0 to +70