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DesignCon 2014
IBIS AMI Modeling of Retimer and
Performance Analysis of Retimer
based Active Serial Links
Kian Haur (Alfred) Chong, Texas Instruments
Venkatesh Avula, LSI Research and Development, Bangalore,
India
Liu Liang, Texas Instruments
Srikanth Pam, Texas Instruments
Makram Mansour, Texas Instruments
Fangyi Rao, Agilent Technologies, Inc
Abstract
This paper presents a novel retimer modeling approach based on IBIS-AMI to capture the
performance of a retimer that operates up to 15 Gbps. The retimer model consists of two back-to-
back Rx-Tx AMI models. It captured characteristic of the continuous linear time equalizer
(CTLE), the variable gain amplifier (VGA), the decision feedback equalizer (DFE), and the
clock-data-recovery (CDR) unit. It also implemented the adaptation algorithms for the CTLE,
DFE, and CDR by optimizing the eye metric through an eye-monitoring system. The digital
signal that drives the Tx model is recovered by the simulator by sampling the Rx AMI_GetWave
output waveform at one half UI after each clock tick returned by the Rx AMI_GetWave function.
We demonstrate the interoperability between retimer and SerDes models and their loss
compensation features in full link simulation. It is shown that the retimer CDR tracks low-
frequency jitter and filters high-frequency jitter to improve the system jitter rejection ratio.
Author(s) Biography
Kian Haur (Alfred) Chong is a Senior System Engineer in the WEBENCH