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April 1999
FDC6321C
Dual N & P Channel , Digital FET
General Description Features
These dual N & P Channel logic level enhancement mode N-Ch 25 V, 0.68 A, RDS(ON) = 0.45 @ VGS= 4.5 V
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very P-Ch -25 V, -0.46 A, RDS(ON) = 1.1 @ VGS= -4.5 V.
high density process is especially tailored to minimize
on-state resistance. This device has been designed Very low level gate drive requirements allowing direct
especially for low voltage applications as a replacement for operation in 3 V circuits. VGS(th) < 1.0V.
digital transistors in load switching applications. Since bias
Gate-Source Zener for ESD ruggedness.
resistors are not required this dual digital FET can replace
>6kV Human Body Model
several digital transistors with different bias resistors.
Replace multiple dual NPN & PNP digital transistors.
SOT-23 SuperSOTTM-6 SuperSOTTM-8 SO-8 SOT-223 SOIC-16
Mark:.321
D2
S1 4 3
D1
5 2
G2
S2
SuperSOT TM -6 G1 6 1
Absolute Maximum Ratings TA = 25oC unless other wise noted
Symbol Parameter N-Channel P-Channel Units
VDSS, VCC Drain-Source Voltage, Power Supply Voltage 25 -25 V
VGSS, VIN Gate-Source Voltage, 8 -8 V
ID, IO Drain/Output Current - Continuous 0.68 -0.46 A
- Pulsed 2 -1.5
PD Maximum Power Dissipation (Note 1a) 0.9 W
(Note 1b)
0.7
TJ,TSTG Operating and Storage Tempature Ranger -55 to 150