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A B C D E




Compal Confidential
Model Name : P7YE0/P7YH0/P7YS0
File Name : LA-6911P
1 1

BOM P/N:43




Compal Confidential
2 2




P7YE0/P7YH0/P7YS0 M/B Schematics Document
Intel Sandy Bridge Processor with DDRIII + Cougar Point PCH
ATI Seymour/Whistler/Granville


3 2010-11-01 3




REV:0.3




4 4




Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/07/12 Deciphered Date 2012/07/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6911
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019A9
Date: Tuesday, November 09, 2010 Sheet 1 of 60
A B C D E
A B C D E




Fan Control
page 40




1
204pin DDRIII-SO-DIMM X2 1
Channel A BANK 0, 1, 2, 3 page 11
100MHz PCI-E 2.0x16 5GT/s PER LANE
PEG(DIS) Intel
ATI Seymour/ 133MHz Memory BUS(DDRIII)
Whistler/ Sandy Bridge Two Dimm Per Channel
Granville 1.5V DDRIII 1066/1333/
Processor 204pin DDRIII-SO-DIMM X2
page22`29 BANK 0, 1, 2, 3 page 12

rPGA988B Channel B
page 4~10

HDMI(DIS) CRT(DIS) LVDS(DIS) EDP(DIS) FDI x8 DMI x4 USB 2.0 conn x2 Bluetooth CMOS Camera Card Reader
USB port 0,1 on USB/B Conn RTS5138
HDMI Conn. CRT Conn. LVDS Conn. USBx1(3D) 100MHz 100MHz
USB port 13 USB port 10 USB port 11
page 36 page 36 page 30 page 36
page 32 page 31 page 30 USB port 4 2.7GT/s 1GB/s x4
2 USBx14 3.3V 48MHz 2


HDMI(UMA) LVDS(UMA)
Intel
CRT(UMA) HD Audio 3.3V 24MHz

TMDS(UMA) Cougar Point-M
PCH
PCI-Express x 8 (ARD PCIE2.0 2.5GT/s) 100MHz HDA Codec
989pin BGA ALC271X/277X
port 3 port 2 port 1 SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S) 100MHz SPI page 39
page 13~21

USB 2.0 conn x1 MINI Card x2 LAN(GbE)
WLAN, WWAN
USB port 8,9 page 35
AR8151/8152
page 42 page 34 SPI ROM x1 Int. Speaker Combo Jack x 1
page 13
MIC Jack x1
port 0,1 port 2 page 39 page 39
SATA HDD SATA CDROM
3
RJ45 Conn. x2 Conn. page 33 LPC BUS 3
page 33
page 34
33MHz


Sub-board ENE KB930
page 37
LS-6911P
USB/B 2Port
RTC CKT. USB Port0,1 CPU XDP
page 35
page 13
Touch Pad Int.KBD
page 38 page 6
page 38
LS-6912P
Power On/Off CKT. LAN/B
page 38
page 37
BIOS ROM
page 38
DC/DC Interface CKT. LS-6913P LS-6914P
4
page 41 PWR/B LID/B 4

page 34

Power Circuit DC/DC
page 43~ Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/07/12 Deciphered Date 2012/07/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6911
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019A9 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, November 09, 2010 Sheet 2 of 60
A B C D E
A B C D E




Voltage Rails
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Power Plane Description S1 S3 S5
VIN Adapter power supply (19V) N/A N/A N/A Full ON HIGH HIGH HIGH HIGH ON ON ON ON
BATT+ Battery power supply (12.6V) N/A N/A N/A
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
B+ AC or battery power rail for power circuit. N/A N/A N/A
1 1
+CPU_CORE Core voltage for CPU ON OFF OFF S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
+VGA_CORE Core voltage for GPU ON OFF OFF
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
+VGFX_CORE Core voltage for UMA graphic ON OFF OFF
+0.75VS +0.75VP to +0.75VS switched power rail for DDR terminator ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.0VSDGPU +1.0VSDGPU switched power rail for GPU ON OFF OFF
+1.05VS_VTT +1.05VS_VTTP to +1.05VS_VTT switched power rail for CPU ON OFF OFF
+1.05VS_PCH +1.05VS_VTT to +1.05VS_PCH power for PCH ON OFF OFF Board ID / SKU ID Table for AD channel
+1.5V +1.5VP to +1.5V power rail for DDRIII ON ON OFF Vcc 3.3V +/- 5%
+1.5VS +1.5V to +1.5VS switched power rail ON OFF OFF Ra/Rc/Re 100K +/- 5%
+1.5VSDGPU +1.5V to +1.5VSDGPU switched power rail for GPU ON OFF OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+1.8VS (+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU ON OFF OFF 0 0 0 V 0 V 0 V
+3VALW +3VALW always on power rail ON ON ON* 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+3VALW_PCH +3VALW to +3VALW_PCH power rail for PCH (Short Jumper) ON ON ON* 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+3VS +3VALW to +3VS power rail ON OFF OFF 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+5VALW +5VALWP to +5VALW power rail ON ON ON* 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+5VALW_PCH +5VALW to +5VALW_PCH power rail for PCH (Short resister) ON ON ON* 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
2 2
+5VS +5VALW to +5VS switched power rail ON OFF OFF 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+VSB +VSBP to +VSB always on power rail for sequence control ON ON ON* 7 NC 2.500 V 3.300 V 3.300 V
+RTCVCC RTC power ON ON ON

BOARD ID Table BTO Option Table
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
BTO Item BOM Structure
Board ID PCB Revision
UMA Only UMAO@
0 0.1
EC SM Bus1 address EC SM Bus2 address Muxless/UMA UMA@
1 0.2 P9,P19,P23,P30-32,P59
DIS Only DISO@
Device Address Device Address
2 0.3 P4,P14
Muxless/DIS DIS@
Smart Battery 0001 011X b
3 1.0 P.22-28
Muxless/DIS VGA@
4
PCH SM Bus address BACO mode BACO@ P.26 ,P.29
5
VRAM P/N
nonBACO mode NOBACO@
Device Address
6 P.27,28
SAM 64*16 900M SA00004GS10(S IC D3 64M16 K4W1G1646G-BC11 FBGA ABO!)
VRAM X76@
ChannelA DIMM0 A0 1010 000X JDIMM1 SAM 64*16 800M SA000035720(S IC D3 64MX16 K4W1G1646E-HC12 FBGA ABO!)
7 P.27
SAM 128*16 800M SA00003MQ60 (S IC D3 128M16 K4W2G1646C-HC12 FBGA ABO!)
128bit VRAM 128@
DIMM1 A2 1010 001X JDIMM3 HYN 64*16 900M SA000041S40(S IC D3 64MX16 H5TQ1G63DFR-11C FBGA ABO!) Granville GPU GRAN@ P.23,P.59
HYN 64*16 800M SA000032420 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA ABO!)
ChannelB DIMM0 A4 1010 010X JDIMM2 HYN 128*16 800M SA00003VS10 (S IC D3 128M16 H5TQ2G63BFR-12C FBGA ABO!) Whistler GPU WHIS@ P.59
3 3
HYN 64*16 800M SA0000324G0(S IC D3 64M16 H5TQ1G63DFR-12C FBGA ABO!)
DIMM1 A6 1010 011X JDIMM4 Seymour GPU SEYM@ P.22-26
USB Port Table P.23,P.25
non Granville GPU NOGRAN@
BT Config GPU config BACO config 3 External P.35
USB 2.0 USB 1.1 Port Blue Tooth BT@
BT SKU: BT@ Whistler: WHIS@ BACO: BACO@ USB Port
Connector CONN@
4DIMM config Seymour: SEYM@ nonBACO: NOBACO@ 0 USB/B(Right side 2.0 option)
UHCI0 Unpop @
4 DIMM: 4DIMM@ Granville: GRAN@ Muxless config 1 USB/B(Right side 2.0 option)
LVDS/eDP config Granville config Muxless: MUXL@ 2 USB port(left side 2.0)
UHCI1 DIS eDP DEDP@ P.30,59
UMA LVDS: ULVDS@ Granville: GRAN@ (VDDCI) nonMuxless: NOMUXL@ (DISO,UMAO) 3 USB/B(Right side 3.0 option) P.30
EHCI1 UMA LVDS ULVDS@
DIS LVDS: DLVDS@ nonGranville: NOGRAN@ (VGA_CORE) 4
VRAM BOM Config UHCI2 DIS LVDS DLVDS@
DIS eDP: DEDP@ GPU Frame config 5
X76264BOL01: 64Mx16x4 Seymour 512M HYN NEW Muxless MUXL@ P.18,P.32
128bit: 128@ (WHIS,GRAN) 6
X76264BOL02: 64Mx16x4 Seymour 512M HYN OLD UHCI3 non Muxless NOMUXL@ P.18
7 P.41
X76264BOL03: 64Mx16x8 Whistler/Granville 1G HYN NEW USB2.0 Conn USB2@
8 Mini Card(WLAN) P.41
X76264BOL04: 64Mx16x8 Whistler/Granville 1G HYN OLD UHCI4 USB3.0 Conn USB3@
9 Mini Card P.11-12
X76264BOL05: 128Mx16x8 Whistler/Granville 2G HYN 4 Dimm 4DIMM@
10 Camera
X76264BOL06: 128Mx16x8 Whistler/Granville 2G SAM EHCI2 UHCI5
11 Card Reader
4
X76264BOL07: 128Mx16x4 Seymour 1G SAM 4
12
X76264BOL08: 128Mx16x4 Seymour 1G HYN UHCI6
13 Blue Tooth
BOM Config
* UMA Only LVDS Panel: BT@/UMAO@/UMA@/ULVDS@/NOMUXL@ +DIMM,USB option
* DIS Only LVDS Panel: BT@/DIS@/VGA@/DISO@/DLVDS@/NOMUXL@ +X76+GPU +DIMM,USB option Security Classification Compal Secret Data Compal Electronics, Inc.
DIS Only EDP Panel: BT@/DIS@/VGA@/DISO@/DEDP@/NOMUXL@ +X76+GPU +DIMM,USB option Issued Date 2010/07/12 Deciphered Date 2012/07/12 Title

* Muxless BACO LVDS Panel: BT@/UMA@/DIS@/VGA@/ULVDS@/BACO@/MUXL@
SCHEMATIC,MB A6911
+X76+GPU(S,W) +DIMM,USB option THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Document Number
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Muxless nonBACO LVDS Panel: BT@/UMA@/DIS@/VGA@/ULVDS@/NOBACO@/MUXL@ +X76+GPU(G) +DIMM,USB option DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019A9 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, November 09, 2010 Sheet 3 of 60
A B C D E
A B C D E


PEG_ICOMPI and RCOMPO signals should be
shorted and routed
with - max length = 500 mils - typical
impedance = 43 mohms +1.05VS_VTT
PEG_ICOMPO signals should be routed with -




1
max length = 500 mils
R532
- typical impedance = 14.5 mohms 24.9_0402_1%

JCPU1A




2
1 J22 PEG_COMP 1
PEG_ICOMPI
PEG_ICOMPO J21
15 DMI_CRX_PTX_N0 B27 DMI_RX#[0] PEG_RCOMPO H22
PEG_GTX_HRX_N[0..15] 22 15 DMI_CRX_PTX_N1 B25 DMI_RX#[1]
PEG_GTX_HRX_P[0..15] 22 15 DMI_CRX_PTX_N2 A25 DMI_RX#[2]
15 DMI_CRX_PTX_N3 B24 K33 PEG_GTX_C_HRX_N15 C320 1 2 DIS@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N15
DMI_RX#[3] PEG_RX#[0] PEG_GTX_C_HRX_N14 C316 DIS@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N14
PEG_HTX_C_GRX_N[0..15] 22 PEG_RX#[1] M35 1 2
15 DMI_CRX_PTX_P0 B28 L34 PEG_GTX_C_HRX_N13 C313 1 2 DIS@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N13
PEG_HTX_C_GRX_P[0..15] 22 DMI_RX[0] PEG_RX#[2]
15 DMI_CRX_PTX_P1 B26 J35 PEG_GTX_C_HRX_N12 C308 1 2 DIS@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N12
DMI_RX[1] PEG_RX#[3]




DMI
15 DMI_CRX_PTX_P2 A24 J32 PEG_GTX_C_HRX_N11 C300 1 2 DIS@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N11
DMI_RX[2] PEG_RX#[4] PEG_GTX_C_HRX_N10 C297 DIS@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N10
15 DMI_CRX_PTX_P3 B23 DMI_RX[3] PEG_RX#[5] H34 1 2
H31 PEG_GTX_C_HRX_N9 C287 1 2 DIS@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N9
PEG_RX#[6] PEG_GTX_C_HRX_N8 C275 DIS@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N8
15 DMI_CTX_PRX_N0 G21 DMI_TX#[0] PEG_RX#[7] G33 1 2
E22 G30 PEG_GTX_C_HRX_N7 C262 1 2 DIS@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N7
15 DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8]
F21 F35 PEG_GTX_C_HRX_N6 C249 1 2 DIS@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N6
15 DMI_CTX_PRX_N2 DMI_TX#[2] PEG_RX#[9]
D21 E34 PEG_GTX_C_HRX_N5 C244 1 2 DIS@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N5
15 DMI_CTX_PRX_N3 DMI_TX#[3] PEG_RX#[10]
E32 PEG_GTX_C_HRX_N4 C233 1 2 DIS@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N4
PEG_RX#[11] PEG_GTX_C_HRX_N3 C224 DIS@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N3
15 DMI_CTX_PRX_P0 G22 DMI_TX[0] PEG_RX#[12] D33 1 2
D22 D31 PEG_GTX_C_HRX_N2 C207 1 2 DIS@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N2
15 DMI_CTX_PRX_P1 DMI_TX[1] PEG_RX#[13]




PCI EXPRESS* - GRAPHICS
F20 B33 PEG_GTX_C_HRX_N1 C206 1 2 DIS@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N1
15 DMI_CTX_PRX_P2 DMI_TX[2] PEG_RX#[14]
C21 C32 PEG_GTX_C_HRX_N0 C194 1 2 DIS@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N0
15 DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15]
J33 PEG_GTX_C_HRX_P15 C318 1 2 DIS@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P15
PEG_RX[0] PEG_GTX_C_HRX_P14 C314 DIS@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P14
PEG_RX[1] L35 1 2
K34 PEG_GTX_C_HRX_P13 C309 1 2 DIS@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P13
PEG_RX[2] PEG_GTX_C_HRX_P12 C303 DIS@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P12
15 FDI_CTX_PRX_N0 A21 FDI0_TX#[0] PEG_RX[3] H35 1 2
H19 H32 PEG_GTX_C_HRX_P11 C298 1 2 DIS@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P11
15 FDI_CTX_PRX_N1 FDI0_TX#[1] PEG_RX[4]
E19 G34 PEG_GTX_C_HRX_P10 C288 1 2 DIS@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P10
15 FDI_CTX_PRX_N2 FDI0_TX#[2] PEG_RX[5] PEG_GTX_C_HRX_P9 C278 DIS@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P9




Intel(R) FDI
15 FDI_CTX_PRX_N3 F18 FDI0_TX#[3] PEG_RX[6] G31 1 2
2 B21 F33 PEG_GTX_C_HRX_P8 C265 1 2 DIS@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P8 2
15 FDI_CTX_PRX_N4 FDI1_TX#[0] PEG_RX[7]
C20 F30 PEG_GTX_C_HRX_P7 C255 1 2 DIS@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P7
15 FDI_CTX_PRX_N5 FDI1_TX#[1] PEG_RX[8]
D18 E35 PEG_GTX_C_HRX_P6 C246 1 2 DIS@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P6
15 FDI_CTX_PRX_N6 FDI1_TX#[2] PEG_RX[9]
E17 E33 PEG_GTX_C_HRX_P5 C235 1 2 DIS@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P5
15 FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10]
F32 PEG_GTX_C_HRX_P4 C225 1 2 DIS@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P4
PEG_RX[11] PEG_GTX_C_HRX_P3 C214 DIS@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P3
PEG_RX[12] D34 1 2
A22 E31 PEG_GTX_C_HRX_P2 C210 1 2 DIS@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P2
15 FDI_CTX_PRX_P0 FDI0_TX[0] PEG_RX[13]
G19 C33 PEG_GTX_C_HRX_P1 C196 1 2 DIS@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P1
15 FDI_CTX_PRX_P1 FDI0_TX[1] PEG_RX[14]
E20 B32 PEG_GTX_C_HRX_P0 C190 1 2 DIS@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P0
15 FDI_CTX_PRX_P2 FDI0_TX[2] PEG_RX[15]
15 FDI_CTX_PRX_P3 G18 FDI0_TX[3]
B20 M29 PEG_HTX_GRX_N15 C685 1 2 DIS@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N15
15 FDI_CTX_PRX_P4 FDI1_TX[0] PEG_TX#[0]
C19 M32 PEG_HTX_GRX_N14 C683 1 2 DIS@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N14
15 FDI_CTX_PRX_P5 FDI1_TX[1] PEG_TX#[1]
D19 M31 PEG_HTX_GRX_N13 C680 1 2 DIS@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N13
15 FDI_CTX_PRX_P6 FDI1_TX[2] PEG_TX#[2]
F17 L32 PEG_HTX_GRX_N12 C676 1 2 DIS@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N12
15 FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3]
L29 PEG_HTX_GRX_N11 C673 1 2 DIS@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N11
+1.05VS_VTT PEG_TX#[4] PEG_HTX_GRX_N10 C671 DIS@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N10
15 FDI_FSYNC0 J18 FDI0_FSYNC PEG_TX#[5] K31 1 2
eDP_COMPIO and ICOMPO signals 15 FDI_FSYNC1 J17 K28 PEG_HTX_GRX_N9 C667 1 2 DIS@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N9
FDI1_FSYNC PEG_TX#[6] PEG_HTX_GRX_N8 C663 DIS@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N8
J30 1 2
should be shorted near balls and 15 FDI_INT H20
PEG_TX#[7]
J28 PEG_HTX_GRX_N7 C661 1 2 DIS@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N7
FDI_INT PEG_TX#[8] PEG_HTX_GRX_N6 C659 DIS@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N6
routed with typical impedance PEG_TX#[9] H29 1 2
1




15 FDI_LSYNC0 J19 G27 PEG_HTX_GRX_N5 C654 1 2 DIS@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N5
<25 mohms R118 H17
FDI0_LSYNC PEG_TX#[10]
E29 PEG_HTX_GRX_N4 C648 1 2 DIS@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N4
15 FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11]
should not be left floating 24.9_0402_1% F27 PEG_HTX_GRX_N3 C644 1 2 DIS@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N3
PEG_TX#[12] PEG_HTX_GRX_N2 C640 DIS@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N2
D28 1 2
,ev