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RX MID CHANNELS Internal
850: CH190 -- 881,6 Antenna
GSM: CH 62 -- 947,4 MHz
EGSM: CH 37 -- 942,4Mhz M3
DCS: CH 700 -- 1842,8MHz
PCS: CH 661 -- 1960MHz
Mechanical
DCS/PCS OUT Antenna Switch
TX_OUT_HB 9 M1201
1 2 3
21
5
BP
TX_OUT_LB 2
1 2 3 Power and
Antenna
GSM850/ Control
U50 GSM900 OUT
PA + Antenna Switch 16 15 14 13 8 7 3 4 6
1900 MHZ
NEPTUNE LTS H1 IO_REG (VCC + 2.775V)
1800 MHz U800 A11 PERIPH_IO_REG (VCC + 2.775V)
TX_START
( to Atlas )
DSP Peripherals Power E2 REF_REG (VCC + 1,575V)
(to U200) (Clock ) MCLK
( Frontend Control
T9 accelerator, encryption V5 VBUCK (VCC + 1,875V)
900 MHz (Reset ) MS W10 SPI Timer, Interupts
and Digital Modulation)
(Data In /OUT) MDI
U9 VSIM (from PCAP ) M1200
K2 VSIM (from Atlas)
SIM DIO (Data In /OUT) SIM
850 MHz K3 6 Connector 5
(Transmitt Enable)
RAMP (PA Power Control)
U6 DSP SIM RST (Reset ) GND
DSP SIM J4 2 1.8 or 3V 4
from Neptune V8 L1 Timer Memory VSIM (from Atlas )
UltraLite Interface L1 SIM CLK (Clock ) SIM Card 3
( Frontend Control
104 MHz 1
and Digital Modulation) SIM_PD
R1
RX_ANT_EN
(from PCAP )
(Transmitt Enable)
(Receive Enable)
TX_START
CNTRL_1
CNTRL_2
CNTRL_3
TXI (NC)
VSIM_EN (to Pcap)
(Band select)
M1
TX_EN
MCLK
DATA BUS D0-15
MDI
MS
Shared Memory
1Mbit RAM ADDRESS BUS A1-24
G8 E8 E7 D7 C3 D2 B7 D6 G5 E6 C2
W7 W18 CE_1 K1 U700
DAC1 GPIO MCU External CE_2 (NC) G8
MCU Memory
A2 SAW/ LNA G12 ARM7 Memory V17 CS1B D6
LNA
Matching IIN VoiceBand 52 MHz G17 EB1B F3
RX/TX ADC Sync Anti Anti Chanel DAC A13 Interface FLASH
IBIN LPF F8 K16 EB0B C2
A3 Switch 13 bit Filter Drop Alias Filter 12 bit N10
SAW/ LNA
LNA ENR J19 R WB F4 RESET OUT (from Neptune)
F5,D5
Matching F7 T16 OEB J2,H1,H8
Output Mixer
Quadrature Polyphase
Mixer
DC CLKR 26 MHz T19 BURSTCLK C6 E4... VBUCK (from Atlas)
Filter Correct Serial A4
A5 SAW/ LNA (100KHz) (100KHz)
F6 Oscillator Clock Generator L16 LBAB E5
LNA Interface
Matching FSR N18 ECBB
G7 8MB SRam
QBIN H7 32 MB Flash
A6 SAW/ LNA DRI P2 LCD_RS
LNA RX/TX ADC Sync Anti Anti Chanel DAC
Matching QIN LPF MQSPI N3 LCD_CS
Switch 13 bit Filter Drop Alias Filter 12 bit LCD_CLK_DATA6
Display M4
Quadrature P1 LCD_SDATA_DATA7 (LCD Control via J1300)
1 2 G1 Generator D8 OSCO OSCO_F
U51 Digital TX L3... LCD DATA (0 - 5)
PERIPH_IO_REG
Clock Generator
Interface G7
Oscilator and
1 2 F1 Reference E5 OSCM (Clock enable)
U52 1
EDGE
Devider C5 Y201 2
3 26MHz
U250 GMSK EDGE
FIR C6 U10 TOUT12 (Bias output for THERM signal)
Modulator Modulator
GSM/ EDGE Filter V6 STANDBY_GATEB (to Clock enable Circuit)
TRANCEIVER F4 RF_DATA
(Data In /OUT) GPIO
(Clock ) (U250 Control Bus) U8 Hall Effect
Interface
GMSK/ EDGE Select F5 RF_CLK V7 SPI Switch
Serial
(Chip select)
( VCO Feedback ) G4 RF_CS W9 A14 4
FIN
Devider Pre-Distortion Anti G3 LDTO (NC)
On C14 HS INT U1601 (FlipDetect)Close
Open/
( VCO Tuning) Filter Alias Off C18 LT_SNS_CTL
( Lock Detect Out) 2 1
E1 ADC DATA
VCO1 (TX_LB) One BaseBand UART2 U1600 6 PERIPH_IO_REG
UART / USB Keypad Timer 6
Loop Filter
CP
MQSPI Wire Serial Audio Universal Reg.
Phase Det. ADC H3 VCO_REG Interface Interface Bus Port Interface Asynchron. Interface BT 1
VCO2 (TX_HB) Voltage G7.. PERIPH_IO_REG DS1500
PA Control Reg. (rx) (tx) Rx /Tx
TX_EN
C1.. RF_REG
A17 C15 D15 A15 F3.... V12 W12 D18 T10 V13 E3 T13 A12 B13 N13 D16 B15 Light Sensor 2
(VCC's from Atlas) B16 C16 A16 G3.... W13T11 V11 B14 G8 U13 W5 W11 D13 B12 N17 V16