Text preview for : compal_la-2761_r0.2_schematics.pdf part of acer compal la-2761 r0.2 schematics acer Notebook Ноутбук Acer Aspire 5500 compal_la-2761_r0.2_schematics.pdf
Back to : compal_la-2761_r0.2_schem | Home
A B C D E
Page Index
===============
P01-Cover Page
P02-Block Diagram
P03-Notes List
P04-Dothan(1/2)
P05-Dothan(2/2)
1 1
P06-Alviso HOST(1/5)
P07-Alviso DDR(2/5)
P08-Alviso PCI-E(3/5)
P09-Alviso POWER(4/5)
P10-Alviso POWER(5/5)
P11-DDRI-SODIMM0
Compal Confidential
P12-DDRI-SODIMM1
P13-DDR Decoupling
P14-Clock Generator
P15-CRT Conn.
P16-VGA / LCD Conn.
EFL50/ EFT51 Schematics Document
P17-ICH6(1/4)_HUB,PCI,HOST
P18-ICH6(2/4)_CPU,AC97,IDE,LPC
P19-ICH6(3/4)_USB,PM,LAN,GPIO
2 P20-ICH6(4/4)_POWER&GND 2
P21-HDD/CDROM
Intel Dothan/ Celeron M/ Alviso GM(PM) / DDR-2 / ICH6-M P22-DVI / TV_Out Conn
P23-PCMCIA ENE CB1410 & CB714
P24-PCMCIA SOCKET
P25-TI 1394A TSB43AB21A
(Daughter Card: ATi M24P/ M26P) P26-LAN BCM5788M
P27-LAN Magnetic & RJ45/RJ11
P28-Mimi-PCI Slot
2005 / 03 / 08 (B-Test EVT) P29-AC97 Codec_ALC250D
P30-Audio Line in Switch
P31-AMP & Audio Jack
P32-Super IO SMC217
Rev:0.2 P33-ENE-KB910
P34-MDC / BT / KBD / TP Conn.
3 3
P35-BIOS & I/O Port & SATA HDD
P36-RJ11/LID Switch / Fan / FIR
P37-USB2.0 Conn
P38-Docking Conn.
P39-PWR_OK / RTC
P40-DC INTERFACE
P41-Screws
P42-PWR-DCIN / Precharge
P43-PWR-Charger
P44-PWR-Battery Select
P45-PWR-3V/5V/12V
P46-PWR-GMCH_CORE/1.8V/0.9V
P47-PWR-1.5V/2.5V
P48-PWR-CPU_CORE
4 4
P49-PWR-OTP
P50-PWR-PIR
Security Classification Compal Secret Data
Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title
Cover Sheet
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom EFL50 LA-2761 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 20, 2005 Sheet 1 of 51
A B C D E
A B C D E
Compal confidential
Project Code: EFL50/ EFT51 Intel Dothan/ Celeron M CPU Thermal Sensor Clock Generator
File Name : LA-2761 ADM1032ARM ICS954226AGT
page 4,5
CRT & TV-OUT
page 4 page 14
page 15
1
H_A#(3..31) FSB H_D#(0..63)
1
400 / 533 Mhz
Daughter Card Slot
PCI-Express x16 PCI-E BUS Intel Alviso GM(PM) DDR-2 DDRII-SO-DIMM X2
page 15 BANK 0, 1, 2, 3page 11,12,13
PCBGA 1257
page 6,7,8,9,10 Two Channel DDR-2
ATi M24P/ M26P
VGA Board
page 16
DMI
LCD CONN
page 16
2
USB 2.0 USB conn x 3 2
page 37
Intel ICH6-M USB 2.0 BT Conn
page 34
PCI BUS mBGA-609
Audio CKT Jack x2
AC-LINK AMP & Audio Jack
ALC250-D page 31 page 36
page 17,18,19,20 page 29
Mini PCI BroadCOM 1394 Controller
BCM4401KFB ENE Controller MDC Conn. RJ11 CONN
Socket BCM5788M CB712 TSB43AB21 page 36 page 36
page 28 page 26 page 25
page 23,24
SATA SATA HDD Conn.
page 21
3in1 CardReader LPC BUS
3
RJ45 CONN Slot 0 1 394 Docking Conn. 3
page 27 Slot page 24 Conn.
page 24 page 25
PATA HDD Conn. PCI-E Bridge
CDROM Conn. RJ45
page 21 VGA
Power On/Off CKT. DVI
TV-Out
page 39
SMsC LPC47N217 ENE KB910Q HP-Out/ Line-Out
Mic-in/ Line-in
page 32 page 33
DC/DC Interface CKT. RTC CKT. SPDIF
page 40 page 39 Parallel Port
Serial Port
Int. KBD KB/ Mouse (PS/2)
Power Circuit DC/DC Power OK CKT. Parellel Port Serial Port page 34
DOCKING CONN DOCKING CONN page 39
page 42~49 page 39 Touch Pad
4 page 38 page 38 4
CONN.page 34 BIOS
page 35
Button
LED Security Classification Compal Secret Data
page 38 Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title
Block Diagrams
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom EFL50 LA-2761 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 20, 2005 Sheet 2 of 51
A B C D E
A B C D E
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
Power Plane Description S1 S3 S4/ S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
1 B+ AC or battery power rail for power circuit. N/A N/A N/A 1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
+CPU_CORE Core voltage for CPU ON OFF OFF
+1.05VS 1.05V switched power rail ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+DDRVTT 0.9V switched power rail for DDR terminator ON OFF OFF
+1.5VALW 1.5V always on power rail ON ON ON*
+1.5VS 1.5V switched power rail ON OFF OFF Board ID / SKU ID Table for AD channel
+1.8VS 1.8V switched power rail ON OFF OFF Vcc 3.3V +/- 5%
+DDRVCC 1.8V power rail for DDR ON ON OFF Ra / Rc 100K +/- 5%
+2.5VS 2.5V switched power rail ON OFF OFF Board ID Rb / Rd V AD_BID min V AD_BID typ V AD_BID max
+3VALW 3.3V always on power rail ON ON ON* 0 0 0 V 0 V 0 V
+3V 3.3V power rail ON ON OFF 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+3VS 3.3V switched power rail ON OFF OFF 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+5VALW 5V always on power rail ON ON ON* 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+5VS 5V switched power rail ON OFF OFF 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+5VMOD 5V switched power rail for Module Bay ON OFF OFF 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
2 2
+12VALW 12V always on power rail ON ON ON* 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+RTCVCC RTC power ON ON ON 7 NC 2.500 V 3.300 V 3.300 V
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. BOARD ID Table BTO Option Table
External PCI Devices Board ID PCB Revision BTO Item BOM Structure
Device IDSEL# REQ#/GNT# Interrupts 0 0.1 UMA GM@
C ardBus AD20 2 PIRQA/PIRQB 1 0.2 Discrete PM@
1394 AD16 0 PIRQE 2 LAN 10/100 4401@
SD AD20 2 PIRQA/PIRQB 3 LAN GIGA 5788@
Mini-PCI AD18 1 PIRQG/PIRQH 4 1 Spindle 1S@
LAN AD17 3 PIRQF 5 2 Spindle 2S@
6 2 Spindle with SATA 2SS@
3 3
7 2 Spindle with PATA 2SP@
1 Spindle with SATA 1SS@
EC SM Bus1 address EC SM Bus2 address SKU ID Table 1 Spindle with PATA 1SP@
With Docking WD@
Device Address Device Address SKU ID SKU Without Docking ND@
Smart Battery 0001 011X b ADM1032 1001 110X b 0 With 1394 1394@
EEPROM(24C16/02) 1010 000X b 1 With 1394 4pin 1394<4>@
(24C04) 1011 000Xb 2 With 1394 6pin 1394<6>@
3
4
5
ICH6M SM Bus address 6
7
Device Address
4 4
Clock Generator 1101 001Xb
(ICS 954226AGT)
DDRII DIMM0 1001 000Xb
DDRII DIMM2 1001 010Xb Security Classification Compal Secret Data
Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title
Notes
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom EFL50 LA-2761 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 20, 2005 Sheet 3 of 51
A B C D E
5 4 3 2 1
JP20A
H_A#[3..31]
6 H_A#[3..31]
H_A#3 P4 A19 H_D#0
6 H_REQ#[0..4]
H_REQ#[0..4] H_A#4
H_A#5
U4
A3#
A4#
Dothan D0#
D1# A25 H_D#1
H_D#2
V3 A5# D2# A22
H_RS#[0..2] H_A#6 R3 B21 H_D#3 +3VS
6 H_RS#[0..2] A6# D3#
H_A#7 V2 A24 H_D#4
H_D#[0..63] H_A#8 A7# D4# H_D#5
6 H_D#[0..63] W1 A8# D5# B26
H_A#9 T4 A21 H_D#6
H_A#10 A9# D6# H_D#7
W2 A10# D7# B20
H_A#11 Y4 C20 H_D#8 1
A11# D8#
1
H_A#12 Y1 B24 H_D#9
H_A#13 A12# D9# H_D#10 C401 R379
U1 A13# D10# D24
D H_A#14 AA3 E24 H_D#11 0.1U_0402_16V4Z @ 10K_0402_5% D
H_A#15 A14# D11# H_D#12 2
Y3 A15# D12# C26 1
H_A#16 AA2 B23 H_D#13 C402
2
H_A#17 A16# D13# H_D#14 U29
AF4 A17# D14# E23
H_A#18 AC4 C25 H_D#15 2200P_0402_50V7K THERMDA 2 1
H_A#19 A18# D15# H_D#16 2 D+ VDD1
AC7 A19# D16# H23
H_A#20 AC3 G25 H_D#17 THERMDC 3 6
H_A#21 A20# D17# H_D#18 D- ALERT#
AD3 A21# D18# L23
H_A#22 AE4 M26 H_D#19 EC_SMB_CK2 8 4
A22# D19# 33 EC_SMB_CK2 SCLK THERM#
H_A#23 AD2 H24 H_D#20
H_A#24 A23# D20# H_D#21 EC_SMB_DA2
AB4 A24# D21# F25 33 EC_SMB_DA2 7 SDATA GND 5
H_A#25 AC6 ADDR GROUP DATA GROUP G24 H_D#22
H_A#26 A25# D22# H_D#23
AD5 A26# D23# J23
H_A#27 AE2 M23 H_D#24 ADM1032ARM_RM8
H_A#28 A27# D24# H_D#25
AD6 A28# D25# J25
H_A#29 AF3 L26 H_D#26 SMBus Address: 1001110X (b)
H_A#30 A29# D26# H_D#27
AE1 A30# D27# N24
H_A#31 AF1 M25 H_D#28
A31# D28# H_D#29
D29# H26
H_REQ#0 R2 N25 H_D#30
H_REQ#1 REQ0# D30# H_D#31
P3 REQ1# D31# K25
H_REQ#2 T2 Y26 H_D#32
H_REQ#3 REQ2# D32# H_D#33
P1 REQ3# D33# AA24
H_REQ#4 T1 T25 H_D#34
REQ4# D34# H_D#35
D35# U23
H_ADSTB#0 U3 V23 H_D#36
6 H_ADSTB#0 ADSTB0# D36#
H_ADSTB#1 AE5 R24 H_D#37
6 H_ADSTB#1 ADSTB1# D37# +1.05VS
R26 H_D#38
D38# H_D#39
D39# R23
C A16 AA23 H_D#40 C
ITP_CLK0 D40# H_D#41
A15 ITP_CLK1 D41# U26
V24 H_D#42
CLK_CPU_BCLK D42# H_D#43 ITP_TDI R53 150_0402_5%
13 CLK_CPU_BCLK B15 BCLK0 D43# U25 2 1
CLK_CPU_BCLK# B14 HOST CLK V26 H_D#44
13 CLK_CPU_BCLK# BCLK1 D44#
Y23 H_D#45 ITP_TDO R383 2 1 @ 54.9_0402_1%
D45# H_D#46
D46# AA26
Y25 H_D#47 H_CPURST# R382 2 1 @ 54.9_0402_1%
H_ADS# D47# H_D#48
6 H_ADS# N2 ADS# D48# AB25
H_BNR# L1 AC23 H_D#49 ITP_TMS R54 2 1 40.2_0402_1%
6 H_BNR# BNR# D49#
H_BPRI# J3 AB24 H_D#50
6 H_BPRI# H_BR0# BPRI# D50# H_D#51 PRO_CHOT# R386 56_0402_5%
6 H_BR0# N4 BR0# D51# AC20 2 1
H_DEFER# L4 AC22 H_D#52
6 H_DEFER# H_DRD Y# DEFER# D52# H_D#53 H_PWRGOOD R56 200_0402_5%
6 H_DRDY# H2 DRDY# D53# AC25 2 1
H_HIT# K3 AD23 H_D#54
6 H_HIT# HIT# D54#
H_HITM# K4 CONTROL GROUP AE22 H_D#55 H_IERR# R380 2 1 56_0402_5%
6 H_HITM# HITM# D55#
H_IERR# A4 AF23 H_D#56
H_LOCK# IERR# D56# H_D#57
6 H_LOCK# J2 LOCK# D57# AD24
H_CPURST# B11 AF20 H_D#58
6 H_CPURST# RESET# D58# H_D#59 +3VS
D59# AE21
AD21 H_D#60
H_RS#0 D60# H_D#61
H1 RS0# D61# AF25
H_RS#1 K1 AF22 H_D#62 ITP_DBRRESET# R381 2 1 150_0402_5%
H_RS#2 RS1# D62# H_D#63
L2 RS2# D63# AF26
H_TRDY# M3
6 H_TRDY# TRDY#
D25 H_DINV#0
DINV0# H_DINV#0 6
J26 H_DINV#1 ITP_TRST# R384 2 1 680_0402_5%
DINV1# H_DINV#1 6
C8 T24 H_DINV#2
B BPM0# DINV2# H_DINV#2 6 B
B8 AD20 H_DINV#3 ITP_TCK R385 2 1 27.4_0402_1%
BPM1# DINV3# H_DINV#3 6
A9 BPM2#
C9 TEST1 R55 2 1 @ 1K_0402_5%
BPM3# H_DSTBN#0
DSTBN0# C23 H_DSTBN#0 6
ITP_DBRRESET# A7 K24 H_DSTBN#1 TEST2 R401 2 1 @ 1K_0402_5%
DBR# DSTBN1# H_DSTBN#1 6
H_DBSY# M2 W25 H_DSTBN#2
6 H_DBSY# DBSY# DSTBN2# H_DSTBN#2 6
H_DPSLP# B7 AE24 H_DSTBN#3
17 H_DPSLP# DPSLP# DSTBN3# H_DSTBN#3 6
H_DPRSTP# G1 C22 H_DSTBP#0
17 H_DPRSTP# DPRSTP# DSTBP0# H_DSTBP#0 6
H_DPWR# C19 L24 H_DSTBP#1
6 H_DPWR# DPWR# DSTBP1# H_DSTBP#1 6
A10 MISC W24 H_DSTBP#2
PRDY# DSTBP2# H_DSTBP#2 6
B10 AE25 H_DSTBP#3
PRO_CHOT# B17
PREQ#
PROCHOT#
DSTBP3# H_DSTBP#3 6 0415
H_PWRGOOD E4