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A B C D E
SYSTEM DC/DC
Volvi Block Diagram
MAX8744 36
Project code: 91.4U701.001 INPUTS OUTPUTS
PCB P/N : 07200
5V_S5
REVISION : -1
Mobile CPU
DCBATOUT
3V_S5
4 CLK GEN. Yonah 478 G792 4
ICS 9LPRS502
20 SYSTEM DC/DC
(RTM875T-605) 3 Celeron M PCB STACKUP MAX8717 37
71.09502.00W 62.10079.001 4, 5 TV Out
14 TOP INPUTS OUTPUTS
VCC 1D8V_S3
HOST BUS 400/533/[email protected] CRT DCBATOUT
14 1D05V_S0
DDR2 533/667MHz
S
533/667 MHz Calistoga
AGTL+ CPU I/F
LCD
13
S
TPS51100 39
13,14 GND 1D8V_S3 DDR_VREF
DDR Memory I/F
INTEGRATED GRAHPICS BOTTOM
DDR2 533/667MHz LVDS, CRT I/F
APL5312 39
533/667 MHz 71.CALIS.00U 6,7,8,9,10 VGA Borad 3D3V_S0 2D5V_S0
13,14 X4 DMI 26
3 C-Link0 APL5912 38
3
400MHz
Line In 1D8V_S3 1D5V_S0
Codec AZALIA
ALC268 ICH7M Intersil CHARGER
MAX8731 40
28 4 PCIe ports OZ129 Cardreader
MIC In 1394 INPUTS OUTPUTS
PCI/PCI BRIDGE PCI BUS 1394
14 ACPI 2.0 CardReader CONN 25 MS/MS Pro/xD/ BT+
2 SATA 24 18V 4.0A
MMC/SD DCBATOUT
1 PATA 66/100 5 in 1 25 UP+5V
8 USB 2.0/1.1 ports 5V 100mA
31 OP AMP ETHERNET (10/100/1000MbE)
G1431Q 29 High Definition Audio 22 CPU DC/DC
Giga LAN TXFM RJ45 MAX8770
INT.SPKR LPC I/F BCM5787MKMLG 23 23 35
2 Serial Peripheral I/F 2
OP AMP INPUTS OUTPUTS
G1412 PCIex1 Mini Card VCC_CORE
29 Kedron a/b/g/n 27 DCBATOUT
Line Out 0~1.3V
48A
(No-SPDIF)
MODEM 71.ICH7M.00U
RJ11 MDC Card 15,16,17,18
LPC BUS
21
SATA
PATA
USB
MINI USB KBC SPI I/F BIOS LPC
PCI Express Winbond W25X80-VSS
New card BlueTooth DEBUG
27 22 WPC8768L 32 CONN. 32
30
1 Touch INT. UMA
1
P2231NFC1 CDROM MEDIA BD CIR 31
28 HDD 20 20 31 Pad 31 KB 31 Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
USB Title
4 Port21 CAMERA BLOCK DIAGRAM
Size Document Number Rev
13 A3
Volvi -1
Date: Wednesday, April 18, 2007 Sheet 1 of 43
A B C D E
A B C D E
ICH7M Functional Strap Definitions
ICH8-M EDS 21762 2.0V1 page 16
ICH7M Integrated Pull-up Crestline Strapping Signals and
Signal Usage/When Sampled Comment and Pull-down Resistors Configuration Crestline EDS 20954
page 7
1.0
ICH8-M EDS 21762 2.0V1
HDA_SDOUT XOR Chain Entrance/ Allows entrance to XOR Chain testing when TP3 Pin Name Strap Description Configuration
PCIE Port Config1 bit1, pulled low.When TP3 not pulled low at rising edge
Rising Edge of PWROK of PWROK,sets bit1 of RPC.PC(Config Registers: SIGNAL Resistor Type/Value CFG[2:0] FSB Frequency Select 001 = FSB533
HDA_BIT_CLK PULL-DOWN 20K 011 = FSB667
offset 224h) 010 = FSB800
HDA_RST# NONE others = Reserved
4 HDA_SYNC PCIE config1 bit0,
Rising Edge of PWROK.
This signal has a weak internal pull-down.
Sets bit0 of RPC.PC(Config Registers:Offset 224h) HDA_SDIN[3:0] PULL-DOWN 20K CFG[4:3] Reserved
4
GNT2# PCIE config2 bit0, This signal has a weak internal pull-up. HDA_SDOUT PULL-DOWN 20K CFG5 DMI x2 Select 0 = DMI x2
Rising Edge of PWROK. Sets bit2 of RPC.PC2(Config Registers:Offset 0224h) 1 = DMI x4 (Default)
HDA_SYNC PULL-DOWN 20K CFG[8:6] Reserved
GPIO20 Reserved This signal should not be pulled high.
GNT[3:0] PULL-UP 20K 0 = Normal mode
GNT1#/ ESI Strap (Server Only) ESI compatible mode is for server platforms only. Low Power PCI Express 1 = Low Power mode (Default)
GPIO51 Rising Edge of PWROK This signal should not be pulled low for desttop GPIO[20] PULL-DOWN 20K
and mobile. 0 = Reverse Lanes,15->0,14->1 ect..
LDA[3:0]#/FHW[3:0]# PULL-UP 20K CFG9 PCI Express Graphics 1= Normal operation(Default):Lane
Lane Reversal Numbered in order
Top-Block Sampled low:Top-Block Swap mode(inverts A16 for LAN_RXD[2:0] PULL-UP 10K
GNT3# Swap Override. all cycles targeting FWH BIOS space).
Rising Edge of PWROK. Note: Software will not be able to clear the LDRQ[0] PULL-UP 20K CFG[11:10] Reserved
Top-Swap bit until the system is rebooted XOR/ALL Z test 00 = Reserved
without GNT3# being pulled down.
LDRQ[1]/GPIO23 PULL-UP 20K
CFG[13:12] straps 01 = XOR mode enabled
PME# PULL-UP 20K 10 = All Z mode enabled
GNT0#/ Boot BIOS Destination Controllable via Boot BIOS Destination bit 11 = Normal Operation (Default)
SPI_CS1# Selection. (Config Registers:Offset 3410h:bit 11:10). PWRBTN# PULL-UP 20K
Rising Edge of PWROK. GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC. CFG[15:14] Reserved Reserved
SATALED# PULL-UP 15K
Integrated VccSus1_05, Enables integrated VccSus1_05, VccSus1_5 and CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled
INTVRMEN VccSus1_5 and VccCL1_5 VccCL1_5 VRM's when sampled high SPI_CS1# PULL-UP 20K 1 = Dynamic ODT Enabled (Default)
VRM Enable/Disable.
Always sampled. SPI_CLK PULL-UP 20K
CFG[18:17] Reserved
3 Integrated VccLAN1_05 Enables integrated VccLAN1_05 and VccCL1_05 VRM's
SPI_MOSI PULL-UP 20K
0 = Normal operation (Default):lane 3
LAN100_SLP and VccCL1_05 VRM when sampled high SPI_MISO PULL-UP 20K CFG19 DMI Lane Reversal Numbered in order
Enable/Disable.
TACH_[3:0] PULL-UP 20K 1 =Reverse Lane,4->0,3->1 ect...
Always sampled.
SPKR PULL-DOWN 20K 0 = Only SDVO or PCIE x1 is
PCI Express Lane Signal has weak internal pull-up. Sets bit 27 CFG20 SDVO/PCIE operational (Default)
SATALED# Reversal. Rising Edge of MPC.LR(Device 28:Function 0:Offset D8) TP[3] PULL-UP 20K Concurrent 1 =SDVO and PCIE x1 are operating
of PWROK. simultaneously via the PEG port
USB[9:0][P,N] PULL-DOWN 15K
SPKR No Reboot. If sampled high, the system is strapped to the SDVOCRTL SDVO Present 0 = No SDVO Card present (Default)
Rising Edge of PWROK. "No Reboot" mode(ICH8 will disable the TCO Timer CL_RST# PULL-UP 13K _DATA
system reboot feature). The status is readable 1= SDVO Card present
via the NO REBOOT bit.
NOTE: All strap signals are sampled with respect to the leading
TP3 XOR Chain Entrance. This signal should not be pull low unless using edge of the Crestline GMCH PWORK in signal.
Rising Edge of PWROK. XOR Chain testing.
GPIO33/ Flash Descriptor This signal has a weak internal pull-up.
History
HDA_DOCK Security Override Strap Sampled low:the Flash Descriptor Security will be
_EN# Rising Edge of PWROK overridden. If high,the security measures will be
in effect.This should only be used in manufacturing
environments.
2 2
ICH7M IDE Integrated Series
Termination Resistors
DD[15:0], DIOW#, DIOR#, DREQ,
approximately 33 ohm
DDACK#, IORDY, DA[2:0], DCS1#,
DCS3#, IDEIRQ
page 16
PCIE Routing USB Table PCI Routing
IDSEL INT REQ GNT
LANE1 LAN BCM5787M USB ports definition
LANE2 MiniCard WLAN Pair Device OZ129 AD22 INT_PIRQG# PCI_REQ#0 PCI_GNT#0
LANE3 NewCard WLAN 0 USB1
1 USB3
2 USB2
1 UMA
1
3 USB4
4 MINICARD Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
5 BlueTooth Taipei Hsien 221, Taiwan, R.O.C.
6 CCD Title
7 NewCard Reference
Size Document Number Rev
A3
Volvi -1
Date: Wednesday, April 18, 2007 Sheet 2 of 42
A B C D E
A B C D E
-1 0413 R318 3D3V_S0 -1 0412 RN29
0R3-0-U-GP R297 3D3V_S0 SRN33J-5-GP-U
3D3V_48MPWR_S0 2 1 0R0603-PAD DREFSSCLK_1 2
3D3V_CLKGEN_S0 DREFSSCLK#_1 UMA 3 DREFSSCLK 7
1 2 1 4 DREFSSCLK# 7
1
1
C426 C422
1
1
1
1
1
1
SC4D7U6D3V3KX-GP
SC1U16V3ZY-GP
DY C416 C430 C399 C408 C425 C396
SC4D7U6D3V3KX-GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
RN27
2
2
SRN33J-5-GP-U
2
2
2
2
2
2
CLK_MCH_3GPLL_1 2 3 CLK_MCH_3GPLL 7
CLK_MCH_3GPLL_1# 1
-1 0412 4 CLK_MCH_3GPLL# 7
4 RN25 4
R291 3D3V_S0 SRN33J-5-GP-U
0R0603-PAD CLK_PCIE_ICH_1 2 3 CLK_PCIE_ICH 16
3D3V_CLKPLL_S0 1 2 CLK_PCIE_ICH_1# 1 4 CLK_PCIE_ICH# 16
1
1
1
C393 C392 C412
SC4D7U6D3V3KX-GP
SC1U16V3ZY-GP
SCD1U16V2ZY-2GP
DY RN23
SRN33J-5-GP-U
2
2
2
CLK_PCIE_NEW_R 2 3 CLK_PCIE_NEW 27
CLK_PCIE_NEW#_R 1 4 CLK_PCIE_NEW# 27
RN21
SRN33J-5-GP-U
CLK_PCIE_SATA_1 2 3 CLK_PCIE_SATA 15
CLK_PCIE_SATA_1#1 4 CLK_PCIE_SATA# 15
RN22 SRN33J-5-GP-U
CLK_PCIE_LAN_R 1 4 CLK_PCIE_LAN 22
3D3V_S0 CLK_PCIE_LAN#_R 2 3 CLK_PCIE_LAN# 22
H/L: 100/96MHz
U10
1
RN24 SRN33J-5-GP-U
R325 30 PCLK_KBC 2 R328 1 33R2J-2-GP PCLKKBC 56 17 DREFSSCLK_1 CLK_PCIE_MINI_1 1 4 CLK_PCIE_MINI1 27
10KR2J-3-GP PCI_2/REQ_SEL SRC_0/DOT96SS DREFSSCLK#_1 CLK_PCIE_MINI_1# 2
3 PCI_3 SRC_0#/DOT96SS# 18 3 CLK_PCIE_MINI1# 27
24 PCLK_PCM 2 R331 1 33R2J-2-GP PCLKPCM 4 PCI_4 CLK_MCH_3GPLL_1
5 19
2
PCI_5 SRC_1 CLK_MCH_3GPLL_1# RN26 SRN33J-5-GP-U
3 SS_SEL
-1 0411 Del R321 SS_SEL 9
SRC_1# 20
22 CLK_PCIE_ICH_1 CLK_PCIE_PEG_1 1 4 3
PCIF_1/DOT96SS_SEL# SRC_2 CLK_PCIE_PEG 26
16 CLK_ICHPCI 2 R329 1 33R2J-2-GP PCLKICH 8 23 CLK_PCIE_ICH_1# CLK_PCIE_PEG_1# 2 MXM 3 CLK_PCIE_PEG# 26
PCIF_0/ITP_EN SRC_2# CLK_PCIE_NEW_R
SRC_3 24
1
16 PM_STPPCI# 55 25 CLK_PCIE_NEW#_R
R327 PCI_STOP# SRC_3# CLK_PCIE_SATA_1 RN30 SRN33J-5-GP-U
SRC_4_SATA 26
DY 10KR2J-3-GP 27 CLK_PCIE_SATA_1# CLK_CPU_BCLK_1 1 4 CLK_CPU_BCLK 4
SRC_4_SATA# CLK_PCIE_LAN_R CLK_CPU_BCLK_1# 2
11,18 SMBC_ICH 46 SCLK SRC_5 31 3 CLK_CPU_BCLK# 4
47 30 CLK_PCI