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A B C D E
SYSTEM DC/DC
www.bufanxiu.com Project code: 91.4Y701.001
ISL6236 38
INPUTS OUTPUTS
PCB P/N : 5V_S5(5A)
REVISION : 07242-1 DCBATOUT
3D3V_S5(5A)
4 CLK GEN.
Mobile CPU SYSTEM DC/DC 4
ICS 9LPRS365 Penryn G7921 TPS51124 40
07
RTM875N 3 PCB 8-LAYER STACKUP
4, 5
Hyper INPUTS OUTPUTS
TOP 1D05V_M(11A)
HOST BUS 667/800/[email protected]
design DCBATOUT
CRT 18 GND
1D5V_S3(10A)
S
TPS51117 39
UMA LCD
DDR3 socket Cantiga 17
800/1066MHz (only support CRT /LCD) 1D8V_S3
DCBATOUT (2.5A)
S
AGTL+ CPU I/F
15 PWR
DDR Memory I/F PCIE*16 CRT TPS51100 39
INTEGRATED GRAHPICS
18 S DDR_VREF_S0
Extended VGA (1.5A)
DDR3 socket 800/1066MHz LVDS, CRT I/F
LCD 1D8V_S3
17 GND DDR_VREF_S3
8,9,10,11,12,13,14 ATI M82s
16 X4 DMI 19,20,21,22,23,24 HDMI BOTTOM APL5308 39
3 C-Link0 3
400MHz 25 3D3V_S0 2D5V_S0
HP/SPDIF (300mA)
Codec Ricoh CHARGER
ALC269
AZALIA
ICH9M PCI BUS R5C833 1394 BQ24750 42
INT.SPKR (include AMP) CONN 33 MS/MS Pro/xD/ INPUTS OUTPUTS
34 6 PCIe ports
PCI/PCI BRIDGE MMC/SD CHG_PWR
Support Dolby HT
ACPI 1.1 Cardreader 5 in 1
33 18V 4.0A
4 SATA
32,33 DCBATOUT
UP+5V
12 USB 5V 100mA
MIC In LAN
Boardcom CPU DC/DC
ISL6266A
High Definition Audio
10 /100M RJ45 37
INT MIC ARRAY LPC I/F 36
2 Serial Peripheral I/F BCM5906 35 INPUTS OUTPUTS 2
VCC_CORE_S0
PCIe x1 Mini Card *2 DCBATOUT
0~1.3V 47A
Kedron a/b/g/n 40
NB DC/DC
MODEM ISL6263A 41
RJ11 MDC Card 26,27,28,29,30 LPC BUS INPUTS OUTPUTS
39
(option)
SATA
DCBATOUT GFX_CORE
SATA
MINI USB KBC BIOS LPC
USB
SPI I/F
New card PCI Express
BlueTooth 39 Winbond 2M byte DEBUG
41 WPC776
38
51 CONN. 31 SC411 48
DCBATOUT 1D5V_S3
1 Power switch Touch INT. BOM
1
SATA-HDD SATA-CDROM
29 31 31 22 Pad 51 KB 51 CIR 39 Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
USB Title
3 Port 42 CAMERA BLOCK DIAGRAM
Size Document Number Rev
17 A3
LT32P -1
Date: W ednesday, June 18, 2008 Sheet 1 of 53
A B C D E
A B C D E
www.bufanxiu.com
ICH9M Integrated Pull-up Cantiga chipset and ICH9M I/O controller
ICH9M Functional Strap DefinitionsRev.1.5 Hub strapping configuration
ICH9 EDS 642879 page 92
and Pull-down Resistors
4 Signal Usage/When Sampled Comment ICH9 EDS 642879 Rev.1.5
Montevina Platform Design guide 22339
page 218
0.5
4
HDA_SDOUT XOR Chain Entrance/
PCIE Port Config1 bit1,
Allows entrance to XOR Chain testing when TP3
pulled low.When TP3 not pulled low at rising edge SIGNAL Resistor Type/Value Pin Name Strap Description Configuration
Rising Edge of PWROK of PWROK,sets bit1 of RPC.PC(Config Registers: CL_CLK[1:0] PULL-UP 20K CFG[2:0] FSB Frequency 000 = FSB1067
Select 011 = FSB667
offset 224h). This signal has weak internal pull-down
CL_DATA[1:0] PULL-UP 20K 010 = FSB800
others = Reserved
HDA_SYNC PCIE config1 bit0, This signal has a weak internal pull-down. CL_RST0# PULL-UP 20K
Rising Edge of PWROK. Sets bit0 of RPC.PC(Config Registers:Offset 224h) CFG[4:3] Reserved
DPRSLPVR/GPIO16 PULL-DOWN 20K CFG8
GNT2#/ PCIE config2 bit2, This signal has a weak internal pull-up. CFG[15:14]
GPIO53 Rising Edge of PWROK. Sets bit2 of RPC.PC2(Config Registers:Offset 0224h) ENERGY_DETECT PULL-UP 20K CFG[18:17]
GPIO20 Reserved This signal should not be pulled high. HDA_BIT_CLK PULL-DOWN 20K
CFG5 DMI x2 Select 0 = DMI x2
GNT1#/ ESI Strap (Server Only) ESI compatible mode is for server platforms only. HDA_DOCK_EN#/GPIO33 PULL-UP 20K 1 = DMI x4 (Default)
GPIO51 Rising Edge of PWROK This signal should not be pulled low for desttop CFG6 iTPM Host 0= The iTPM Host Interface is enabled(Note2)
and mobile. HDA_RST# PULL-DOWN 20K Interface 1=The iTPM Host Interface is disalbed(default)
HDA_SDIN[3:0] PULL-DOWN 20K 0 = Transport Layer Security (TLS) cipher
Top-Block Sampled low:Top-Block Swap mode(inverts A16 for CFG7 Intel Management suite with no confidentiality
GNT3#/ Swap Override. all cycles targeting FWH BIOS space). HDA_SDOUT PULL-DOWN 20K engine Crypto strap 1 = TLS cipher suite with
GPIO55 Rising Edge of PWROK. Note: Software will not be able to clear the confidentiality (default)
Top-Swap bit until the system is rebooted HDA_SYNC PULL-DOWN 20K
0 = Reverse Lanes,15->0,14->1 ect..
without GNT3# being pulled down. GLAN_DOCK# The pull-up or pull-down active when configured for native CFG9 PCIE Graphics Lane 1= Normal operation(Default):Lane
GLAN_DOCK# functionality and determined by LAN controller Numbered in order
GNT0#: Boot BIOS Destination Controllable via Boot BIOS Destination bit GNT[3:0]#/GPIO[55,53,51] PULL-UP 20K
SPI_CS1#/ Selection 0:1. (Config Registers:Offset 3410h:bit 11:10). 0 = Enable (Note 3)
GPIO58 Rising Edge of PWROK. GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC. GPIO[20] PULL-DOWN 20K CFG10 PCIE Loopback enable 1= Disabled (default)
Integrated TPM Enable, Sample low: the Integrated TPM will be disabled. GPIO[49] PULL-UP 20K 00 = Reserve
Rising Edge of CLPWROK Sample high: the MCH TPM enable strap is sampled CFG[13:12] XOR/ALL 10 = XOR mode Enabled
SPI_MOSI low and the TPM Disable bit is clear, the LDA[3:0]#/FHW[3:0]# PULL-UP 20K 01 = ALLZ mode Enabled (Note 3)
11 = Disabled (default)
Integrated TPM will be enable.
LAN_RXD[2:0] PULL-UP 20K
3 DMI Termination Voltage, The signal is required to be low for desktop
Rising Edge of PWROK. applications and required to be high for
LDRQ[0] PULL-UP 20K
CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled (Default) 3
GPIO49 mobile applications. LDRQ[1]/GPIO23 PULL-UP 20K 0 = Normal operation(Default):
CFG19 DMI Lane Reversal Lane Numbered in Order
PME# PULL-UP 20K
1 = Reverse Lanes
PCI Express Lane Signal has weak internal pull-up. Sets bit 27 PWRBTN# PULL-UP 20K DMI x4 mode[MCH -> ICH]:(3->0,2->1,1->2and0->3)
SATALED# Reversal. Rising Edge of MPC.LR(Device 28:Function 0:Offset D8) DMI x2 mode[MCH -> ICH]:(3->0,2->1)
of PWROK. SATALED# PULL-UP 15K
SPKR No Reboot. If sampled high, the system is strapped to the SPI_CS1#/GPIO58/CLGPIO6 PULL-UP 20K Digital Display Port 0 = Only Digital Display Port
Rising Edge of PWROK. "No Reboot" mode(ICH9 will disable the TCO Timer (SDVO/DP/iHDMI) or PCIE is operational (Default)
system reboot feature). The status is readable SPI_MOSI PULL-DOWN 20K CFG20 Concurrent with PCIe 1 =Digital display Port and PCIe are
via the NO REBOOT bit. operting simulataneously via the PEG port
SPI_MISO PULL-UP 20K
0 =No SDVO Card Present (Default)
TP3 XOR Chain Entrance. This signal should not be pull low unless using SPKR PULL-DOWN 20K SDVO_CTRLDATA SDVO Present
Rising Edge of PWROK. XOR Chain testing. 1 = SDVO Card Present
TACH_[3:0] PULL-UP 20K
0 = LFP Disabled (Default)
GPIO33/ Flash Descriptor Sampled low:the Flash Descriptor Security will be TP[3] PULL-UP 20K Local Flat Panel
HDA_DOCK Security Override Strap overridden. If high,the security measures will be L_DDC_DATA (LFP) Present 1= LFP Card Present; PCIE disabled
_EN# Rising Edge of PWROK in effect.This should only be enabled in manufacturing USB[11:0][P,N] PULL-DOWN 15K
environments using an external pull-up resister. NOTE:
1. All strap signals are sampled with respect to the leading edge of
the (G)MCH Power OK (PWROK) signal.
2. iTPM can be disabled by a 'Soft-Strap' option in the
Flash-decriptor section of the Firmware. This 'Soft-Strap' is
activated only after enabling iTPM via CFG6.
Only one of the CFG10/CFG/12/CFG13 straps can be enabled at any time.
SMBus 17,43,44,46,47,48,49,50,51 DCBATOUT DCBATOUT
7,28,38,43,51,53 3D3V_AUX_S5 3D3V_AUX_S5
2 SMBC_G792 Thermal
40,43,51 5V_AUX_S5 5V_AUX_S5 2
MXM
KBC 13,25,26,27,29,30,35,37,38,39,41,42,43,48,49,50,51,53 3D3V_S5 3D3V_S5
BAT_SCL
USB Table BATTERY 17,29,31,42,43,46,47,48,49,50 5V_S5 5V_S5
PCI Routing page 17
USB
IDSEL INT REQ GNT Pair Device
10,12,13,15,16,29,39,48,50 1D5V_S3 1D5V_S3
G:CARDBUS 0 0 0 Combo(ESATA/USB)
TI7412 AD22 B:1394
F:Flash Media 1 NC 15,16,48 0D75V_S3 0D75V_S3
G:SD Host 2 USB2
SMB_CLK 17,49,50 1D8V_S3 1D8V_S3
3 USB4 LAN
ICH9M
4 USB3 3,7,10,11,13,15,16,17,18,23,24,25,26,27,28,29,30,31,32,33,34,35,38,39,40,41,44,46,50,51,53 3D3V_S0 3D3V_S0
PCIE Routing 5 BLUETOOTH
7,13,18,21,24,25,29,30,31,34,42,44,50,51,53 5V_S0 5V_S0
6 WEBCAM
4,5,6,8,10,11,12,13,28,29,44,46 1D05V_S0 1D05V_S0
LANE2 MiniCard WLAN 7 FT
SMBC_ICH CK505
LANE3 NewCard WLAN 8 MINICARD 3,5,13,26,28,29,34,40,41,50,53 1D5V_S0 1D5V_S0
9 NEW1 DDR
19,21,22,23,24,50 1D8V_S0 1D8V_S0
20,21,23,48 1D1V_S0 1D1V_S0
1 21,23,24,47 VGA_CORE_S0 VGA_CORE_S0
1
BOM
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Reference
Size Document Number Rev
C
Olympus -1
Date: Wednesday, July 09, 2008 Sheet 2 of 53
A B C D E
A B C D E
www.bufanxiu.com
4 4
3D3V_S0 3D3V_S0_CK505
1D5V_S0
L50
L22
1 2
2 1
C696BLM18AG601SN-3GP C343 3D3V_S0_CK505
1
1
1
1
1
1
1
1
C704 C337 C359 C347 C352 C701
BLM18AG601SN-3GP
1
1
1
1
1
1
1
1
C335 C341 C350 C338 C707 C358 C334 C331
SC1U10V3KX-3GP
SC10U10V5ZY-1GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
2
2
2
2
2
2
2
2
SC1U10V3KX-3GP
SC10U10V5ZY-1GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2Z