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A B C D E
1 1
Compal Confidential
2 2
JE50/HM50/SJV50_BZ
P5WE6/P5WH6/P5WS6 Schematics Document
AMD Brazos
Brazos with Zacate / Hudson M1 / Seymour XT
DIS only / UMA only / PX Muxless / PX Muxless with BACO
3 3
2010-11-16 ZZZ
LA-7092P REV: 1.0 PCB
Part Number = DAZ0IC00100
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/08/20 Deciphered Date 2011/08/20 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7092P P5WE6/H6/S6
Date: Tuesday, November 16, 2010 Sheet 1 of 47
A B C D E
A B C D E
Compal Confidential
Model Name : P5WE6/P5WH6/P5WS6
JE50/HM50/SJV50_BZ VRAM 512M/1G
64M16/128M16 x 4
1
PCB PN : DAZ0IC00100
DDR3
page 23
Brazos 1
ATI Vancuver Seymour Memory BUS(DDR3) 204pin DDRIII-SO-DIMM X2
Single Channel BANK 0, 1, 2, 3 page 8,9
uFCBGA-962 PCI-Express x 4
Thermal Sensor AMD Brazos APU 1.5V DDRIII 800~1066MHz
Page 18,19,20,21,22 Gen2
ADM1032
page 19 FT1
DP0 BGA 413-Ball
19mm x 19mm
LVDS
page 10
DP1 page 5,6,7
2 2
CRT USB port 0,1,2 USB port 5 USB port 7 USB port6 USB port 8
page 12
UMI Gen.1 x4 USB CMOS Bluetooth Card Mini
PCI-Express Reader card
HDMI 2.5GT/s per lane Conn x 3 Camera Conn
RT5137 (WL)X1
Conn.
page 11
page 33 page 10 page 33 page 29 page 29
FCH
3.3V 48MHz USB
Hudson-M1
3.3V 24.576MHz/48Mhz HD Audio
BGA 605-Ball
23mm x 23mm
S-ATA Gen2
page 13,14,15,16,17
MINI Card LAN(GbE)
LED Atheros HDA Codec
3
page 32 WLAN AR8151 CX20584 27 3
page 29 page 26 page
GPP3 GPP2 LPC BUS SATA HDD SATA ODD
RTC CKT. Conn. page 30 Sub/B page 30
RJ45 MIC Jack x 1
page 13 port 0 port 1
page 26
HP Jack x 1
Int MIC x 1
Power On/Off CKT. ENE KB930
page 34
Int SPK x 1
page 31 page 28
Power sequence
VGA DC/DC Touch Pad Int.KBD
page 24,25 page 32 page 32
DC/DC Interface CKT. Fan Control EC I/O Buffer BIOS
4
page 34 4
page 32 page 32
page 35
Extend Card/B
Power Circuit 1. USB X2 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/08/20 Deciphered Date 2011/08/20 Title
page 36,37,38,39,40,41 Block Diagrams
42,43,44,45 2. ODD X1 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7092P P5WE6/H6/S6
Date: Monday, November 15, 2010 Sheet 2 of 47
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A B C D E
Voltage Rails BOARD ID Table
SIGNAL
Power Plane Description S1 S3 S5 STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Board ID PCB Revision
VIN Adapter power supply (19V) N/A N/A N/A Full ON HIGH HIGH HIGH HIGH ON ON ON ON 0
B+ AC or battery power rail for power circuit. N/A N/A N/A 1
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
+VSB VSB always on power rail ON ON ON* 2
+3VALW 3.3V always on power rail ON ON ON* S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF 3
1 1
+5VALW 5V always on power rail ON ON ON*
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
4
+1.1VALW 1.1V always on power rail ON ON ON* 5
+APU_CORE Core voltage for CPU (0.7-1.2V) ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF 6
+APU_CORE_NB 1.0V switched power rail ON OFF OFF 7
+1.5V 1.5V power rail for CPU VDDIO and DDRIII ON ON OFF Board ID / SKU ID Table for AD channel
+0.75VS 0.75VS switched power rail for DDR terminator ON OFF OFF Vcc 3.3V +/- 5%
+1.05VS 1.05V switched power rail for APU VDD10 ON OFF OFF Ra/Rc/Re 100K +/- 5% Project ID Table
+1.1VS 1.1VS switched power rail ON OFF OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
Board ID PCB Revision
+1.8VS 1.8V switched power rail ON OFF OFF 0 0 0 V 0 V 0 V
0
+3VS 3.3V switched power rail ON OFF OFF 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
1
+5VS 5V switched power rail ON OFF OFF 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
2
+VGA_CORE Core voltage for GPU ON OFF OFF 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
3
+3VSG 3.3V switched power rail for GPU ON OFF OFF 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
4
+1.8VSG 1.8V switched power rail for GPU ON OFF OFF 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
5
+1.5VSG 1.5V switched power rail for GPU ON OFF OFF 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
6
+1.0VSG 1.0V switched power rail for GPU ON OFF OFF 7 NC 2.500 V 3.300 V 3.300 V
2
+3V_LAN 3.3V power rail for LAN ON ON ON
7 2
+RTCVCC RTC power ON ON ON
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
BOARD ID Table
BTO Option Table
Board ID PCB Revision
EC SM Bus1 address EC SM Bus2 address 0 w/ X'tal X1 BTO Item BOM Structure
1 wo/ X'tal X1 Display from APU UMA@
Device Address HEX Device Address HEX 2 Display from VGA DISO@
ADM1032 (GPU) 1001-101xb 9AH 3 Use VGA VGA@
4 Muxless w/BACO BACO@
5 Muxless wo/BACO WOBACO@
SM Bus Controller 0 (FCH_SMB1 ~ FCH_SMB4, SMB_ALERT#)
6 Muxless PX@
7 w/Vancouver Serise VAN@
Device Address HEX w/Manhttan Serise MAN@
APU SIC/SID (FCH_SMB3)
Bluetooth BT@
3
H_THERMTRIP# (FCH_ALERT#)
Project ID Table AR8151 8151@ 3
Seymour Seymour@
Board ID PCB Revision
wo/Muxless WOPX@
SM Bus Controller 1 (FCH_SMB0)
0
wo/VGA WOVGA@
1
APU 1.5G 15G@
Device Address HEX 2
APU 1.6G 16G@
DDR DIMM1 (FCH_SMB0) 1001-000xb
3
90
DDR DIMM2 (FCH_SMB0) 1001-001xb
4
92
WLAN (FCH_SMB0)
5
6
7
*UMA only : UMA@ BT@ 8151@ WOVGA@ WOPX@
VGA Chip SEL: APU Chip SEL:
1. Seymour@ + Van@ 1. 16G@
2. Robson@ + Man@ 2. 15G@
*DIS only : VGA@ DISO@ WOBACO@ BT@ 8151@ WOPX@
4 *Muxless w/BACO : UMA@ VGA@ PX@ BACO@ BT@ 8151@ 4
Muxless wo/BACO : UMA@ VGA@ PX@ WOBACO@ BT@ 8151@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/08/20 Deciphered Date 2011/08/20 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7092P P5WE6/H6/S6
Date: Tuesday, November 16, 2010 Sheet 3 of 47
A B C D E
5 4 3 2 1
Without BACO option :
Power-Up/Down Sequence PE_GPIO0 : Low -> Reset dGPU ; High ->Normal operation
1. All the ASIC supplies must fully reach their respective nominal voltages within 20 ms of the start of the ramp-up PE_GPIO1 : Low -> dGPU Power OFF ; High -> dGPU Power ON
sequence, though a shorter ramp-up duration is preferred.
BACO option :
2. VDDR3 should ramp-up before or simultaneously with VDDC. PE_GPIO0 : High ->Normal operation (dGPU is not reseton BACO mode)
PE_GPIO1 : Low -> dGPU Power OFF ; High -> dGPU Power ON (always High)
3. For LVDS, DPx_VDD10 should ramp-up before DPx_VDD18 and the PCIe Reference clock should begin before
D DPx_VDD18. For power-down, DPx_VDD18 should ramp-down before DPx_VDD10. dGPU Power Pins Voltage PX 3.0 BACO Mode Max current
D
4. The external pull-ups on the DDC/AUX signals (if applicable) should ramp-up before or after both VDDC and PCIE_PVDD, PCIE_VDDR, TSVDD, VDDR4, VDD_CT, 1.8V OFF ON 1679mA
VDD_CT have ramped up. DPE_PVDD, DP[F:E]_VDD18, DP[D:A]_PVDD,
DP[D:A]_VDD18, AVDD, VDD1DI, A2VDDQ, VDD2DI,
5.VDDC and VDD_CT should not ramp-up simultaneously. (e.g., VDDC should reach 90% before VDD_CT starts to
DPLL_PVDD, MPV18, and SPV18
ramp-up (or vice versa).)
DP[F:E]_VDD10, DP[D:A]_VDD10, DPLL_VDDC, and 1.0V OFF ON 575mA
SPV10
PCIE_VDDC 1.0V OFF ON 2A
VDDR3(3.3VSG) Note: Do not drive any IOs before VDDR3 is ramped up.
VDDR3 , and A2VDD 3.3V OFF ON 190mA
BIF_VDDC (current consumption = [email protected], in Same as OFF ON 70mA
PCIE_VDDC(1.0V) BACO mode) VDDC Same as
PCIE_VDDC
VDDR1 1.5V OFF OFF 2.8A
C
VDDR1(1.5VSG) VDDC/VDDCI 1.12V OFF OFF 12.9A C
VDDC/VDDCI(1.12V)
VDD_CT(1.8V)
PE_GPIO0 PE_EN BACO Switch
iGPU dGPU
PERSTb BIF_VDDC
PE_GPIO1
REFCLK PX_mode
B +3.3VALW MOS
+3.3VSG B
Straps Reset 1
+1.5V SI4800
+1.5VSG
Straps Valid +1.0V +1.0VSG
Regulator
2 3
Global ASIC Reset
+B Regulator
+VGA_CORE
+1.8V +1.8VSG
T4+16clock
SI4800
5 4
PWRGOOD
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/08/20 Deciphered Date 2011/08/20 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
dGPU Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7092P P5WE6/H6/S6
Date: Monday, November 15, 2010 Sheet 4 of 47
5 4 3 2 1
5 4 3 2 1
+1.8VS U22B
R398 1 2 150_0402_1%
DISPLAYPORT 1
<11> APU_HDMI_TX2P A8 TDP1_TXP0 DP_ZVSS H3
DP MISC
<11> APU_HDMI_TX2N B8
TDP1_TXN0
DP_BLON G2 APU_ENBKL <10>
R399 1 2 1K_0402_5% APU_SVC B9 H2
<11> APU_HDMI_TX1P TDP1_TXP1 DP_DIGON APU_ENVDD <10>
R400 1 2 1K_0402_5% APU_SVD A9 H1
D APU_RST# <11> APU_HDMI_TX1N TDP1_TXN1 DP_VARY_BL APU_BLPWM <10> D
R142 2 1 300_0402_5%
R401 2 1 300_0402_5% APU_PWRGD D10
TEST_25_L <11> APU_HDMI_TX0P TDP1_TXP2 APU_HDMI_CLK
R402 1 2 510_0402_1% C10 B2
<11> APU_HDMI_TX0N TDP1_TXN2 TDP1_AUXP APU_HDMI_CLK <11>
R141 1 2 1K_0402_5% TEST36 C2 APU_HDMI_DATA
TDP1_AUXN APU_HDMI_DATA <11>
<11> APU_HDMI_CLKP A10
TDP1_TXP3
<11> APU_HDMI_CLKN B10 TDP1_TXN3 TDP1_HPD C1 APU_HDMI_HPD <11>
C237 0.01U_0402_25V7K B5 A3 APU_LCD_CLK
<10> APU_TXOUT2+ LTDP0_TXP0 LTDP0_AUXP APU_LCD_CLK <10>
1 @ 2 APU_RST# APU_LCD_DATA
DISPLAYPORT 0
<10> APU_TXOUT2- A5 LTDP0_TXN0 LTDP0_AUXN B3 APU_LCD_DATA <10>
C238 0.01U_0402_25V7K
1 @ 2 APU_PWRGD D6 D3 R406 1 2 100K_0402_5%
<10> APU_TXOUT1+ LTDP0_TXP1 LTDP0_HPD
<10> APU_TXOUT1- C6
LTDP0_TXN1
DAC_RED C12 APU_CRT_R <12>
A6 D13 R407 1 2 150_0402_1%
<10> APU_TXOUT0+ LTDP0_TXP2 DAC_REDB
<10> APU_TXOUT0- B6 A12 APU_CRT_G <12>
+3VS LTDP0_TXN2 DAC_GREEN R408 1
B12 2 150_0402_1%
DAC_GREENB
D8 A13
VGA DAC
APU_PROCHOT# <10> APU_TXCLK+ LTDP0_TXP3 DAC_BLUE APU_CRT_B <12>
R410 1 2 1K_0402_5% C8 B13 R409 1 2 150_0402_1%
<10> APU_TXCLK- LTDP0_TXN3 DAC_BLUEB
R109 1 UMA@ 2 4.7K_0402_5% APU_CRT_DDC_SCL V2 E1
<13> APU_CLKP CLKIN_H DAC_HSYNC APU_CRT_HSYNC <12>
<13> APU_CLKN V1 E2 APU_CRT_VSYNC <12>
R155 1 UMA@ 2 4.7K_0402_5% APU_CRT_DDC_SDA CLKIN_L DAC_VSYNC
CLK
<13> APU_DISP_CLKP