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Compal Confidential
Model Name : EA/EG50_CX (Z5WE1)
File Name : LA-9535P
1 1
Compal Confidential
2 2
EA/EG50_CX (Z5WE1) M/B Schematics Document
Intel Ivy Bridge ULV Processor + Panther Point PCH
Nvidia N14M-GE & N14P-GV2
2013-06-07
3 3
REV:1.0
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
2013/02/04 EOP Title
Issued Date Deciphered Date Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9535P M/B Schematics
Date: Friday, June 07, 2013 Sheet 1 of 55
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A B C D E
Fan Control
page 40
1
204pin DDR3-SO-DIMM X1 1
BANK 0, 1, 2, 3 page 11
Nvidia N14P series Intel Memory BUS
with DDR3 x 4
page 22~28 Ivy Bridge Dual Channel
ULV Processor 1.5V DDR3 1333/1600 204pin DDR3-SO-DIMM X1
BANK 4, 5, 6, 7 page 12
eDP
eDP Conn. BGA1023
page 29
page 4~10
CRT Conn. HDMI Conn. LVDS
page 31 page 30 FDI x8 DMI x4
CLK=100MHz CLK=100MHz
HDMI x 4 lanes
2.7GT/s 2.5GB/s x4 Touch USB 3.0 USB 2.0 CMOS
2.97GT/s
2 Screen conn x1 conn x2 Camera 2
USB port 3 USB port 0 USB/B (port 1,2) USB port 10
Intel page 29 page 36 page 36 page 29
PCIE 48MHz
Panther Point-M USBx8
PCIe 2.0 PCIe 2.0
5GT/s 5GT/s PCH
SATA HD Audio 3.3V 24MHz
port 1 port 2
989pin BGA
page 13~21 SPI
SATA3.0 SATA3.0 HDA Codec
LAN(GbE) MINI Card 6.0 Gb/s 6.0 Gb/s ALC3225
Boardcom WLAN port 0 port 2 page 39
57786Xpage 32~33
USB port 8 page 34
SATA HDD SATA CDROM
3 Conn. Conn. LPC BUS 3
page 35 page 35 SPI ROM x1 Int. Speaker Int. MIC Combo Jack
CLK=24MHz
Card Reader
2 in 1 page 13
ENE page 39 page 39 page 39
(SD/MMC)
page 32~33 KB9012
page 37
RTC CKT. Sub Board
page 13
Touch Pad Int.KBD
LS-9531P page 38 page 38
Power On/Off CKT. PWR/B
page 36
page 38
LS-9532P
4
DC/DC Interface CKT. USB/B (port 1,2)
4
page 41 page 36
Security Classification Compal Secret Data Compal Electronics, Inc.
2013/02/04 EOP Title
Power Circuit DC/DC Issued Date Deciphered Date Block Diagrams
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
page 42~52 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9535P M/B Schematics
Date: Friday, June 07, 2013 Sheet 2 of 55
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SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails Full ON HIGH HIGH HIGH HIGH ON ON ON ON
Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
VIN Adapter power supply (19V) N/A N/A N/A
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
BATT+ Battery power supply (12.6V) N/A N/A N/A
B+ AC or battery power rail for power circuit. N/A N/A N/A S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
1 +CPU_CORE Core voltage for CPU ON OFF OFF 1
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+VGA_CORE Core voltage for GPU ON OFF OFF
+0.75VS +0.675VSP to +0.675VS switched power rail for DDR terminator ON OFF OFF Board ID / SKU ID Table for AD channel
+1.05VSDGPU +1.0VSDGPU switched power rail for GPU ON OFF OFF Vcc 3.3V +/- 5%
+0.95VSDGPU +0.95VSDGPUP to +0.95VSDGPU switched power rail for CPU ON OFF OFF Ra/Rc/Re 100K +/- 5%
+1.5V +1.35VP to +1.35V power rail for DDRIIIL ON ON OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+1.5VS +1.5V to +1.5VS switched power rail ON OFF OFF 0 0 0 V 0 V 0 V BTO Option Table
+1.5VSDGPU +1.5VSDGPUP to +1.5VSDGPU switched power rail for GPU ON OFF OFF 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V BTO Item BOM Structure
+1.8VS +3VS to 1.8V switched power rail to CPU ON OFF OFF 2 18K +/- 5% 0.436 V 0.503 V 0.538 V Unpop @
+1.8VSDGPU +1.8VS to +1.8VSDGPU switched power rail for GPU ON OFF OFF 3 33K +/- 5% 0.712 V 0.819 V 0.875 V Connector CONN@
+3VALW +3VALW always on power rail ON ON ON* 4 56K +/- 5% 1.036 V 1.185 V 1.264 V PCH RTC CMOS SP@
+3VLP B+ to +3VLP power rail for suspend power ON ON ON 5 100K +/- 5% 1.453 V 1.650 V 1.759 V TEST PAD TP@
+3VS +3VALW to +3VS power rail ON OFF OFF 6 200K +/- 5% 1.935 V 2.200 V 2.341 V Unpop SPI2 SPI2@
+3VSDGPU +3VS to +3VSDGPU switched power rail for GPU ON OFF OFF 7 NC 2.500 V 3.300 V 3.300 V Unpop CPU CPU@
+5VALW +5VALWP to +5VALW power rail ON ON ON* Unpop GPU GPU@
+5VS +5VALW to +5VS switched power rail ON OFF OFF BOARD ID Table
+VSB +VSBP to +VSB always on power rail for sequence control ON ON ON* Unpop VRAM VRAM@
2
+RTCVCC RTC power ON ON ON
Board ID PCB Revision 2
0 0.1
Back light BL@
1 0.2
IOAC IOAC@
2 0.3
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
3 1.0 Celeron 847 847@
4
Celeron 1007 1007@
EC SM Bus1 address EC SM Bus2 address 5
I3-3227M I33227@
6
I5-3337M I53337@
Device Address Device Address 7
I7-3537M I73537@
Smart Battery 0001 011X
USB Port Table UMA ONLY GPIO UMAO@
VGA Internal Thermal Senser 1001 111x (0x9E)
3 External EDP EDP@
USB 2.0 Port
USB Port LVDS LVDS@
PCH SM Bus address 0 USB Port(Left 3.0)
Device Address
1 USB Port(Right 2.0)
ChannelA DIMM0 1001 000x JDIMM1
2 USB Port(Right 2.0)
ChannelB DIMM1 1001 010x JDIMM2
3 Touch Screen EMC POP EMC@
EHCI1
3
4 EMC NON POP XEMC@ 3
5
6 N14M-GE option N14MGE@
7 N14P-GT option N14PGT@
N14P-GV2 option N14PGV2@
USB 2.0 Port N14P-GT/GV2 Strap GV2GT@
VGA SKU VGA@
8 Mini Card (WLAN+BT)
VRAM x 8pcs 128@
9
PEG 16X 16X@
10 Camera
PEG 8X 8X@
11
EHCI2 GC6 GC6@
12
NON GC6 NGC6@
13
USB 3.0 Port
0 USB Port(Left 3.0)
BOM Config
1
UMAO: EDP@/IOAC@/BL@/EMC@/UMAO@/ CPU config XHCI
2
4
DIS GV2: EDP@/IOAC@/BL@/EMC@/VGA@/ GC6@/N14PGV2@/GV2GT@/8X@/ CPU config + X76 3 4
DIS GE: EDP@/IOAC@/BL@/EMC@/VGA@/ GC6@/N14MGE@/8X@/ CPU config + X76
Security Classification Compal Secret Data Compal Electronics, Inc.
2013/02/04 EOP Title
Issued Date Deciphered Date Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9535P M/B Schematics
Date: Friday, June 07, 2013 Sheet 3 of 55
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A B C D E
ZZZ
Part Number Description REV0 DA6000ZK000
DAZ10O00100 PCB Z5WE1 LA-9535P LS-9531P/LS-9532P REV1 DA6000ZK010
LA9535_PCB
UCPU1
S IC AV8063801119500 SR0XF L1 1.9G ABO!
I33227@ SA00006D990
1. PEG_RCOMPO and PEG_ICOMPI should be connected together with 4-mil width first. Then be connected to R1 from ball of PEG_ICOMPI.
AV8063801119500 SR0XF L1 1.9G ABO!
2. PEG_ICOMPO should be connected to R1 with width 12-mil.
UCPU1 3. No longer than 500-mil to above two.
1 1
S IC AV8063801129900 SR0XL L1 1.8G ABO!
I53337@ SA00006D860
+1.05VS_VTT
AV8063801129900 SR0XL L1 1.8G ABO! PEG_GTX_HRX_P[0..15]
PEG_GTX_HRX_P[0..15] 22
1
UCPU1 PEG_GTX_HRX_N[0..15]
PEG_GTX_HRX_N[0..15] 22
S IC AV8063801119700 SR0XG L1 2G ABO! R1
PEG_HTX_C_GRX_P[0..15]
PEG_HTX_C_GRX_P[0..15] 22
I73537@ SA00006DB90 24.9_0402_1%
UCPU1A PEG_HTX_C_GRX_N[0..15]
2
G3 PEG_HTX_C_GRX_N[0..15] 22
PEG_COMP
AV8063801119700 SR0XG L1 2G ABO! PEG_ICOMPI G1
M2 PEG_ICOMPO G4
15 DMI_CRX_PTX_N0 DMI_RX#[0] PEG_RCOMPO
UCPU1 P6
15 DMI_CRX_PTX_N1 DMI_RX#[1]
S IC AV8062700852800 SR08N Q0 1.1G ABO! P1
15 DMI_CRX_PTX_N2 DMI_RX#[2]
P10 H22
15 DMI_CRX_PTX_N3 DMI_RX#[3] PEG_RX#[0]
847@ SA00005VK20 J21
N3 PEG_RX#[1] B22
15 DMI_CRX_PTX_P0 DMI_RX[0] PEG_RX#[2]
P7 D21
15 DMI_CRX_PTX_P1 DMI_RX[1] PEG_RX#[3]
DMI
DMI
AV8062700852800 SR08N Q0 1.1G ABO! P3 A19
15 DMI_CRX_PTX_P2 DMI_RX[2] PEG_RX#[4]
P11 D17
15 DMI_CRX_PTX_P3 DMI_RX[3] PEG_RX#[5]
UCPU1 B14
K1 PEG_RX#[6] D13
S IC AV8063801118700 SR109 P0 1.5G ABO! 15 DMI_CTX_PRX_N0 DMI_TX#[0] PEG_RX#[7]
M8 A11 PEG_GTX_C_HRX_N7 C1 1 2 8X@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N7
15 DMI_CTX_PRX_N1 N4 DMI_TX#[1] PEG_RX#[8] B10 1 2
1007@ SA00006EW30 PEG_GTX_C_HRX_N6 C2 8X@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N6
15 DMI_CTX_PRX_N2 DMI_TX#[2] PEG_RX#[9]
R2 G8 PEG_GTX_C_HRX_N5 C3 1 2 8X@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N5
15 DMI_CTX_PRX_N3 DMI_TX#[3] PEG_RX#[10] A8 PEG_GTX_C_HRX_N4 C4 1 2 8X@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N4
AV8063801118700 SR109 P0 1.5G ABO! IVY BRIDGE K3 PEG_RX#[11] B6 PEG_GTX_C_HRX_N3 C5 1 2 8X@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N3
15 DMI_CTX_PRX_P0 M7 DMI_TX[0] PEG_RX#[12] H8 PEG_GTX_C_HRX_N2 1 2 PEG_GTX_HRX_N2
C6 8X@ 0.22U_0402_6.3V6K
15 DMI_CTX_PRX_P1 P4 DMI_TX[1] PEG_RX#[13] E5 1 2
PEG_GTX_C_HRX_N1 C7 8X@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N1
15 DMI_CTX_PRX_P2 T3 DMI_TX[2] PEG_RX#[14] K7 1 2
UCPU1 PEG_GTX_C_HRX_N0 C8 8X@ 0.22U_0402_6.3V6K PEG_GTX_HRX_N0
2 15 DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15] 2
S IC AV8063801130300 SR10A P0 1.6G ABO!
K22
1017@ PEG_RX[0] K19
SA00006UH50 PEG_RX[1] C21
U7 PEG_RX[2] D19
15 FDI_CTX_PRX_N0 W11 FDI0_TX#[0] PEG_RX[3] C19
AV8063801130300 SR10A P0 1.6G ABO!
15 FDI_CTX_PRX_N1 W1 FDI0_TX#[1] PEG_RX[4] D16
15 FDI_CTX_PRX_N2 AA6 FDI0_TX#[2] PEG_RX[5] C13
UCPU1
15 FDI_CTX_PRX_N3 FDI0_TX#[3] PEG_RX[6]
S IC AV8063801058800 SR0VQ P0 1.8G ABO! W6 D12
15 FDI_CTX_PRX_N4 V4 FDI1_TX#[0] PEG_RX[7] C11 1 2
PEG_GTX_C_HRX_P7 C9 8X@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P7
PCI EXPRESS -- GRAPHICS
15 FDI_CTX_PRX_N5 Y2 FDI1_TX#[1] PEG_RX[8] C9 1 2
2117@ SA000061240 PEG_GTX_C_HRX_P6 C10 8X@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P6
15 FDI_CTX_PRX_N6 AC9 FDI1_TX#[2] PEG_RX[9] F8 1 2
PEG_GTX_C_HRX_P5 C11 8X@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P5
15 FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10]
Intel(R) FDI
Intel(R) FDI
C8 PEG_GTX_C_HRX_P4 C12 1 2 8X@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P4
AV8063801058800 SR0VQ P0 1.8G ABO! PEG_RX[11] C5 PEG_GTX_C_HRX_P3 C13 1 2 8X@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P3
U6 PEG_RX[12] H6 PEG_GTX_C_HRX_P2 C14 1 2 8X@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P2
15 FDI_CTX_PRX_P0 FDI0_TX[0] PEG_RX[13]
UCPU1 W10 F6 PEG_GTX_C_HRX_P1 C15 1 2 8X@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P1
15 FDI_CTX_PRX_P1 W3 FDI0_TX[1] PEG_RX[14] K6 1 2
S IC AV8063801119100 SR105 P0 1.9G ABO! PEG_GTX_C_HRX_P0 C16 8X@ 0.22U_0402_6.3V6K PEG_GTX_HRX_P0
15 FDI_CTX_PRX_P2 AA7 FDI0_TX[2] PEG_RX[15]
15 FDI_CTX_PRX_P3 W7 FDI0_TX[3] G22
2127@ SA00006UG30 15 FDI_CTX_PRX_P4 T4 FDI1_TX[0] PEG_TX#[0] C23
15 FDI_CTX_PRX_P5 AA3 FDI1_TX[1] PEG_TX#[1] D23
15 FDI_CTX_PRX_P6 FDI1_TX[2] PEG_TX#[2]
AV8063801119100 SR105 P0 1.9G ABO! AC8 F21
15 FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3] H19
UCPU1 AA11 PEG_TX#[4] C17
15 FDI_FSYNC0 FDI0_FSYNC PEG_TX#[5]
S IC AV8063801058401 SR0N9 L1 1.8G ABO! AC12 K15
+1.05VS_VTT 15 FDI_FSYNC1 FDI1_FSYNC PEG_TX#[6] F17
I33217@ U11 PEG_TX#[7] F14 PEG_HTX_GRX_N7 C17 1 2 8X@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N7
SA00005L5C0 15 FDI_INT FDI_INT PEG_TX#[8] A15 PEG_HTX_GRX_N6 C18 1 2 8X@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N6
AA10 PEG_TX#[9] J14 PEG_HTX_GRX_N5 C19 1 2 8X@ 0.22U_0402_6.3V6K PEG_HTX_C_GRX_N5
15 FDI_LSYNC0
1
1
AV8063801058401 SR0N9 L1 1.8G ABO!