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8 7 6 5 4 3 2 1
Version 0B
Cover Sheet
Block Diagram
1
2
MS-6507 06/29/2001 Update
INTEL (R) Brookdale Chipset
GPIO Spec. 3
D
Willamette/Northwood 478pin mPGA-B Processor Schematics D
Clock CY28324 & ATA100 IDE CONNECTORS 4
mPGA478-B INTEL CPU Sockets 5-6
INTEL Brookdale MCH -- North Bridge 7-8
INTEL ICH2 -- South Bridge 9 - 10
LPC I/O W83627HF 11 CPU:
Willamette/Northwood mPGA-478B Processor
CNR RISER 12
AC'97 Codec 13
C
System Brookdale Chipset: C
Audio Amp TL072 & GAME 14
INTEL MCH (North Bridge) +
FWH-- BIOS & VCCVID 15 INTEL ICH2 (South Bridge)
SDR DIMM-168PIN DIMM1,2 16 On Board Chipset:
AGP 4X SLOT (1.5V) 17 BIOS -- FWH
PCI SLOT 1 & 2 & 3 18 LPC Super I/O -- W83627HF
Front Panel & Connectors 19 Clock Generation -- CY28324
USB & FAN Connectors 20 PCI SOUND -- C-MEDIA CMI8738
B B
D-LED & AUDIO 6 CHANNEL CONTROL 21
Votlage Regulator 22 Expansion Slots:
AGP2.0 SLOT * 1
HIP6301V CPU Power ( PWM )-VRM9.2 23
PCI2.2 SLOT * 3
IO Connectors 24
Realtek RTL8100(L) LAN 25
DDR Damping 26
DDR Termination 27
A A
DDR Termination Power 28
Title Rev
Jumper setting 29 M i c ro-Star MS-6507 0B
Document Number
Power Delivery Map 30 Cover Sheet
Last Revision Date:
Monday, July 23, 2001 Sheet 1 of 36
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
(478PINS)
(100MHz)
Power
Supply VRM Willamette/Northwood CK408 Clock
CONN 9.2 Socket (mPGA478-B) (100MHz)
(400MHz) Scalable Bus Scalable Bus/2
AGP 4 X (66MHz) AGP
AGP 4X
4X(1.5V) MCH: Memory
(1.5V)
AGP CONN
Controller HUB
( 5 93PINS/FCBGA) (133MHz)
DDR 1:2
( 66MHz X 4 ) HUB Interface
(14.318MHz)
C Heceta Hardware SM Bus C
Monitor ICH2: I/O PCI (33MHz)
PCI Slots 1:3
( 3 60PINS/EBGA)
Controller HUB
IDE CONN 1&2
(48MHz)
(33MHz)
(33MHz)
LPC Bus AC Link
USB Port 0:3 CNR Riser
(Shared slot)
AC '97 Audio
FWH: Firmware HUB AMP
Codec
PCI LAN / SIO
Realtek Line Out
Telephone In
RTL8100 MIC In
B Audio In B
Line In
PS2 Mouse & Parallel (1) Floppy Disk
DLED CD-ROM
Keyboard Serial (2) Drive CONN
A A
Title Rev
M i c ro-Star MS-6507 0B
Document Number
Block Diagram
Last Revision Date:
Monday, July 23, 2001 Sheet 2 of 36
8 7 6 5 4 3 2 1
5 4 3 2 1
General Purpose I/O Spec.
D D
ICH2
GPIO Pin Type Function
GPIO 0 I Non Connect
GPIO 1 I Non Connect
GPIO 2~4 I Not Implemented
DEVICE ICH INT Pin IDSEL
GPIO 5 I Non Connect
GPIO 6 I AC97 Enabled/Disabled
FWH PCI Slot 1 INTA# AD16
GPIO Pin Type Function INTB#
GPIO 7 I None
INTC#
C
GPI 0 I ATA IDE 1 Detect C
GPIO 8 I LAN Wake Up INTD#
GPI 1 I ATA IDE 2 Detect
GPIO 9 I AC'97 Serial Data In
PCI Slot 2 INTB# AD17
GPI 2 I Reserved
GPIO 10 I Non Connect INTC#
GPI 3 I Reserved INTD#
GPIO 11 I Non Connect
INTA#
GPIO 12 I External SMI
GPIO 13 I LPC PME DLED-Super I/O PCI Slot 3 INTC# AD18
INTD#
GPIO 14~15 I Not Implemented GPIO Pin Type Function INTA#
INTB#
GPIO 16 O Non Connect GP32 I/OD DLED1
GPIO 17 O Non Connect GP24 I/OD DLED2 PCI Audio INTD#/INTE# AD23
INTA#
B GPIO 18 O Not Implemented GP34 I/OD DLED3 B
INTB#
GPIO 19 O Not Implemented GP33 I/OD DLED4 INTC#
GPIO 20 O Not Implemented
PCI Lan INTC#/INTF# AD22
GPIO 21 O Audio 6 channel control INTD#
INTA#
GPIO 22 O Non
INTB#
GPIO 23 OD BIOS Locked/Unlocked
GPIO 24 O Non
GPIO 25 O Non
GPIO 26 O Non
GPIO 27 I/O Non
A A
GPIO 28 I/O non
GPIO 29~31 I/O Not Implemented Title Rev
M i c ro-Star MS-6507 0B
Document Number
GPIO Spec.
Last Revision Date:
Monday, July 23, 2001 Sheet 3 of 36
5 4 3 2 1
8 7 6 5 4 3 2 1
*Trace less 0.5"
CLOCK GENERATOR BLOCK Shut Source Termination Resistors Pull-Down Capacitors
for good filtering from 10K~1M
CPUCLK R233 49.9
U18 CPUCLK# R234 49.9
FB18 X_600 39 41 R246 33 CPUCLK MCHCLK R229 49.9
VCC3 CPU_VDD CPU0 CPUCLK 5
40 R247 33 CPUCLK# MCHCLK# R230 49.9
+
CPU0# CPUCLK# 5
CB145 Rubycon CT34 CB144 CB154 ITP_CLK R232 X_49.9
0.1u 1u 0.1u 36 38 R239 33 MCHCLK ITP_CLK# R236 X_49.9
CPU_GND CPU1 MCHCLK 7
X_COPPER 37 R240 33 MCHCLK#
CPU1# MCHCLK# 7
D CP600 10u D
46
MREF_VDD 45 C_STP R243 X_33 ITP_CLK
CB151 3VMREF/CPU_STP# 44 P_STP R244 X_33 ITP_CLK# ITP_CLK 5 Trace less 0.2"
3VMREF#/PCI_STP# ITP_CLK# 5
0.1u 43
MREF_GND 49.9ohm for 50ohm M/B impedance CN16
32 31 1 2 MCH_66
3V66_VDD 3V66_0 MCH_66 7
30 RN17 3 4 ICH_66 X_10p
3V66_1 ICH_66 10
CB153 28 33 5 6 AGPCLK MCH_66 1 2
R228 0.1u 29 3V66_2 27 7 8 C157 10p AGPCLK 17 CLOCK STRAPPING RESISTORS ICH_66 3 4
for good filtering from 10K~1M X_0 3V66_GND 3V66_3 3V66_3 RN25 AGPCLK 5 6
6 FS2 7 8 7 8
FB20 X_600 VCC3V 9 FS2/PCI_F0 7 FS3 5 6 ICH_PCLK FS4 R324 10K VCC3V
VCC3 PCI_VDD FS3/PCI_F1 ICH_PCLK 9
8 MODE 3 4 FWH_PCLK FS3 R334 10K VCC3V CN18
+
MODE/PCI_F2 FWH_PCLK 15
CB166 Rubycon CT36 CB178 CB183 1 2 SIO_PCLK X_10p
SIO_PCLK 11
0.1u 1u 0.1u 5 10 FS4 FS1 R282 X_10K VCC3V SIO_PCLK 8 7
X_COPPER PCI_GND FS4/PCI0 11 BSEL0 R749 X_10K R283 10K FWH_PCLK 6 5
PCI1 5 BSEL0
CP601 10u 18 12 33 ICH_PCLK 4 3
PCI_VDD PCI2
100/133 select
14 7 8 PCICLK0 2 1
PCI3 PCICLK0 18
CB177 15 RN24 5 6 PCICLK1 FS0 R321 10K VCC3V
PCI4 PCICLK1 18
0.1u 13 16 33 3 4 PCICLK2 R322 X_10K CN17
PCI_GND PCI5 PCICLK2 18
17 1 2 PCICLK3 X_10p
*Put GND copper under Clock Gen. PCI6 PCICLK3 25 FS2 R326 X_10K PCICLK0 7 8
connect to every GND pin 24 R325 10K VCC3V PCICLK1 5 6
48_VDD FS0 R307 33 ICH_48 PCICLK2
* 40 mils Trace on Layer 4 22 3 4
FS0/48MHz ICH_48 10
CB164 23 FS1 R281 33 SIO_48 MODE R336 X_10K PCICLK3 1 2
with GND copper around it FS1/24_48MHz SIO_48 11
0.1u 21
48_GND
* put close to every power pin
C 2 C
REF_VDD 48 MUL0 R251 33 ICH_14 MUL0 R241 X_10K VCC3V ICH_48 C175 10p
* Trace Width 7mils. CB165 MUL0/REF0 MUL1 ICH_14 10 R231 10K SIO_48 C169 10p
1
0.1u 47 MUL1/REF1
* Same Group spacing 15mils REF_GND MUL1 R316 10K VCC3V
34 3 C171 18p R315 X_10K
* Different Group spacing 30mils CORE_VDD X1 32pF
CB152 X1 14M-32pf-HC49S-D
* Different mode spacing 7mils on itself 0.1u 33 4 C166 18p CRST# R305 10K VCC3V ICH_14 C164 10p
CORE_GND X2
SMBCLK 26 35 R227 475
10,11,12,16 SMBCLK SCLK IREF
R323 VTT_GD# SMBDATA 25 SMBCLK R255 4.7K
VCC3 10K 10,11,12,16 SMBDATA SDATA CRST# R306 0 CLK_RST# SMBDATA R254 4.7K VCC3 used only for EMI issue
20 CLK_RST# 19
R318 X_1K
VTT_GD# 19 RST# 42 R245 4.7K VCC3V
Q36 VTT_GD# PWR_DN# VCC3V Trace less 0.2"
VCCP NPN-3904LT1-S-SOT23 CYP-CY28324 C_STP R242 X_1K VCC3V
R304 220 ICS950208 P_STP R235 X_1K
CY28323
R719 4.7K R718 220 Q705
+12V PRIMARY IDE BLOCK SECONDARY IDE BLOCK
R733
NPN-3904LT1-S-SOT23 ATA100 IDE CONNECTORS
C702 R190 4.7K IDE1 R186 4.7K IDE2
4.7u-0805 4.7K D2x20-1:21-BL-ZBT D2x20-1:21-WH-SBT
HD_RST# R188 33 1 2 HD_RST# R187 33 1 2
PDD7 3 4 PDD8 SDD7 3 4 SDD8
B 10 PDD[0..7] PDD[8..15] 10 10 SDD[0..7] SDD[8..15] 10 B
PDD6 5 6 PDD9 SDD6 5 6 SDD9
PDD5 7 8 PDD10 SDD5 7 8 SDD10
PDD4 9 10 PDD11 SDD4 9 10 SDD11
PDD3 11 12 PDD12 SDD3 11 12 SDD12
PDD2 13 14 PDD13 SDD2 13 14 SDD13
PDD1 15 16 PDD14 SDD1 15 16 SDD14
PDD0 17 18 PDD15 SDD0 17 18 SDD15
19 19
21 22 21 22
10 PD_DREQ 10 SD_DREQ
23 24 23 24
10 PD_IOW# 10 SD_IOW#
10 PD_IOR# 25 26 10 SD_IOR# 25 26
27 28 R129 470 27 28 R128 470
10 PD_IORDY 10 SD_IORDY
29 30 29 30
10 PD_DACK# 10 SD_DACK#
9 IRQ14 31 32 9 IRQ15 31 32
33 34 33 34
10 PD_A1 PD_DET 15 10 SD_A1 SD_DET 15
35 36 35 36
10 PD_A0 PD_A2 10 10 SD_A0 SD_A2 10
37 38 37 38
10 PD_CS#1 PD_CS#3 10 10 SD_CS#1 SD_CS#3 10
R189 33 39 40 R101 33 39 40
19 PD_LED 19 SD_LED
C79 R119 C76 C81 R120 C77
R191 8.2K 220p 10K X_4700p R103 8.2K 220p 10K X_4700p
VCC5 VCC5
VCC3 VCC3
R407 1K
VCC5_SB VCC5
14
A RESET BLOCK PCIRST# 9 8 HD_RST# A
7
U21D
VCC5_SB 7407-SOIC14
R388 330 Title Rev
VCC3
14
9 PCIRST# PCIRST# 1 2 PCIRST#1 7,11,15,25
VCC5_SB M i c ro-Star MS-6507 0B
7 R197 330 VCC3
U21A 14 Document Number
7407-SOIC14 C199 PCIRST# 3 4 PCIRST#2 17,18 Clock CY28323/4 & ATA100 IDE
7
X_10p U21B Last Revision Date:
7407-SOIC14 Monday, August 06, 2001 Sheet 4 of 36
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU SIGNAL BLOCK CPU GTL REFERNCE VOLTAGE BLOCK
VCCP
VCCPS+ 23
7 HA#[3..31] VCCPS- 23
ITP_CLK# 4 R81
ITP_CLK 4 2/3*Vccp 49.9
VID[0..4] 11,23 GTLREF1
HA#28
HA#18
1
0
9
7
6
5
4
3
2
1
0
9
7
6
5
4
3
2
1
0
HA#3
HA#3
HA#2
HA#2
HA#2
HA#2
HA#2
HA#2
HA#2
HA#2
HA#2
HA#1
HA#1
HA#1
HA#1
HA#1
HA#1
HA#1
HA#1
HA#1
HA#9
HA#7
HA#6
HA#5
HA#4
HA#3
HA#8
VID2
VID0
VID4
VID3
VID1
C49 C48 C58 R79
220p 220p 1u 100
AD26
AC26
AE25
D D
AB1
AE1
AE2
AE3
AE4
AE5
W2
W1
M1
M4
M3
M6
T5
T4
T2
T1
U4
R6
U3
U1
R3
R2
N5
N4
N2
N1
Y1
V3