Text preview for : compal_la-7221p_r0.5_schematics.pdf part of acer compal la-7221p r0.5 schematics acer Notebook Ноутбук Acer Aspire 5830 compal_la-7221p_r0.5_schematics.pdf



Back to : compal_la-7221p_r0.5_sche | Home

A B C D E




Compal Confidential
Model Name : P5LJ0 & P5LS0
File Name : LA-7221P
1 1




2 Compal Confidential 2




JM50-HR M/B Schematics Document
Intel Sandy Bridge Processor with DDRIII + Cougar Point PCH
Nvidia N12P-GS/GV
3 3




2010-02-16
REV:0.5

MB PCB
Part Number Description

DA80000MA00 PCB 0IN LA-7221P REV0 M/B


4 4




Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7221P
Date: Friday, February 18, 2011 Sheet 1 of 59

A B C D E
A B C D E




Fan Control
page 45




1 1




100MHz PCI-E 2.0x16 5GT/s PER LANE
PEG(DIS) Intel Memory BUS(DDRIII)
133MHz Dual Channel 204pin DDRIII-SO-DIMM X2
Nvidia N12P-GS/GV Sandy Bridge BANK 0, 1, 2, 3 page 11,12
973pin BGA Processor 1.5V DDRIII 1066/1333

page22~30
EDP rPGA989
(reserved)
page 32
HDMI(Optimus1.1)
page 4~10


FDI x8 DMI x4 USB 2.0 conn x3 Bluetooth CMOS Camera Mini Card
Conn (WWAN,SIM)
USB port 0,1,2 on USB/B USB port 13 USB port 10 USB port 9,12 on 3G/B
HDMI Conn. CRT Conn. LVDS Conn. 100MHz 100MHz
page 37 page 37 page 31 page 37
page 33 page 32 page 31 2.7GT/s 1GB/s x4
2 USBx14 3.3V 48MHz 2


HDMI(Optimus1.0) LVDS(UMA/Optimus)
Intel
CRT(UMA/Optimus) HD Audio 3.3V 24MHz

HDMI(UMA/Optimus) Cougar Point-M
100MHz
PCH
PCI-Express x 8 (ARD PCIE2.0 2.5GT/s)
HDA Codec
port 4 port 3 port 2 port 1 SATA x 6 100MHz 989pin BGA CX20584
page 42
(GEN1 1.5GT/S ,GEN2 3GT/S) page 13~21 SPI
USB uPD720200A MINI Card x1 LAN(GbE)
USB 3.0 conn x1 WLAN
AR8151/8152
page 44.45 USB port 8
page 37 page 35
SPI ROM x1
port 2 page 13 (SJM) (JM)
Card Reader port 0
SATA HDD SATA CDROM
RTS5209 RJ45 Audio AMP
Conn. Conn.
3 page 38 page 36 page 34 page 34 LPC BUS TI TPS6017 3


33MHz page 43


Sub-board ENE KB930
page 39
LS-7221P LS-7225P
RTC CKT. USB/B 3 port USB/B/DW 3 port
USB Port0,1,2 page 37 USB Port0,1,2 page 37 Int. Speaker MIC Jack SPDIF Jack
page 13
Touch Pad Int.KBD
page 40 page 40 page 43 page 43 page 43

Power On/Off CKT. LS-7222P(JM) LS-7226P(SJM)
3G/B 3G/B
page 40 USB Port 9,12 page 37 USB Port 9,12 page 37
BIOS ROM CPU XDP
page 39
DC/DC Interface CKT. LS-7223P(JM) LS-7227P(SJM)
Power/B Power/B page 5
4
page 46 4

page 41 page 41

Power Circuit DC/DC LS-7224P(JM)
page 47~55 LED/B Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title
page 41 Block Diagrams
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7221P
Date: Wednesday, February 16, 2011 Sheet 2 of 59
A B C D E
A B C D E




Voltage Rails
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Power Plane Description S1 S3 S5
VIN Adapter power supply (19V) N/A N/A N/A Full ON HIGH HIGH HIGH HIGH ON ON ON ON
BATT+ Battery power supply (12.6V) N/A N/A N/A
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
B+ AC or battery power rail for power circuit. N/A N/A N/A
1 1
+CPU_CORE Core voltage for CPU ON OFF OFF S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
+VGA_CORE Core voltage for GPU ON OFF OFF
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
+VGFX_CORE Core voltage for UMA graphic ON OFF OFF
+0.75VS +0.75VP to +0.75VS switched power rail for DDR terminator ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.0VSDGPU +1.0VSPDGPU to +1.0VSDGPU switched power rail for GPU ON OFF OFF
+1.05VS_VCCP +1.05VS_VCCPP to +1.05VS_VCCP switched power rail for CPU ON OFF OFF
+1.05VS_PCH +1.05VS_VCCP to +1.05VS_PCH power for PCH ON OFF OFF Board ID / SKU ID Table for AD channel
+1.5V +1.5VP to +1.5V power rail for DDRIII ON ON OFF Vcc 3.3V +/- 5%
+1.5VS +1.5V to +1.5VS switched power rail ON OFF OFF Ra/Rc/Re 100K +/- 5%
+1.5VSDGPU +1.5VS to +1.5VSDGPU switched power rail for GPU ON OFF OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+1.8VS (+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU ON OFF OFF 0 0 0 V 0 V 0 V
+3VALW +3VALW always on power rail ON ON ON* 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+3VALW_EC +3VALW always to KBC ON ON ON* 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+3V_LAN +3VALW to +3V_LAN power rail for LAN ON ON ON* 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+3VALW_PCH +3VALW to +3VALW_PCH power rail for PCH (Short Jumper) ON ON ON* 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+3VS +3VALW to +3VS power rail ON OFF OFF 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
2 2
+5VALW +5VALWP to +5VALW power rail ON ON ON* 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+5VALW_PCH +5VALW to +5VALW_PCH power rail for PCH (Short resister) ON ON ON* 7 NC 2.500 V 3.300 V 3.300 V
+5VS +5VALW to +5VS switched power rail ON OFF OFF
+VSB +VSBP to +VSB always on power rail for sequence control ON ON ON*
BOARD ID Table BTO Option Table
+RTCVCC RTC power ON ON ON
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. Board ID PCB Revision BTO Item BOM Structure
0 0.1 UMA Only UMAO@
1 0.2 UMA with OPTIMUS UMA@
EC SM Bus1 address EC SM Bus2 address 2 0.3 OPTIMUS1.0 OPT@
3 1.0 OPTIMUS1.1 OPT11@
Device Address Device Address 4 N12P-GS@ GS@
Smart Battery 0001 011X b 5 N12P-GV@ GV@
6 VRAM X76@
7 Connector CONN@
PCH SM Bus address 3G 3G@
USB Port Table Blue Tooth BT@
3 3
Device Address EDP EDP@
3 External
Clock Generator (9LVS3199AKLFT, 1101 0010b
USB 2.0 USB 1.1 Port USB Port LAN Chip AR8151 8151@
RTM890N-631-VB-GRT) LAN Chip AR8152 8152@
DDR DIMM0 1001 000Xb
0 USB/B (Right Side)
UHCI0 JM Board JM@
DDR DIMM2 1001 010Xb
1 USB/B (Right Side)
SJM Board SJM@
2 USB/B (Right Side)
UHCI1 Unpop @
3
3G & BT Config EHCI1 Power GPU VGA@
4
3G SKU: 3G@ UHCI2
5
BT SKU: BT@
6
UHCI3
7
BOM Config 8 Mini Card(WLAN)
JM UMA Only: BT@/3G@/UMA@/UMAO@/JM@/8151@ UHCI4
9 Mini Card(WWAN)
JM OPTIMUS: BT@/3G@/UMA@/OPT@/JM@/8151@/GV@/GS@
10 Camera
SJM UMA Only: BT@/3G@/UMA@/UMAO@/SJM@/8151@ EHCI2 UHCI5
11
SJM OPTIMUS: BT@/3G@/UMA@/OPT@/SJM@/8151@/GV@/GS@
12 SIM Card
UHCI6
4 BOM P/N(JM/SJM) VRAM BOM Config 13 Blue Tooth 4

4319BOBOL01/L21 UMA W3G HDMI X76289BOL01 512M SAM 64M16
4319BOBOL02/L22 UMA N3G HDMI X76289BOL02 512M HYN 64M16
4319BOBOL03/L23 N12PGS 1GW3G HDMI X76289BOL03 1G SAM 64M16
4319BOBOL04/L24 N12PGS 1GN3G HDM X76289BOL04 1G HYN 64M16
4319BOBOL05/L25 N12PGS 2GW3G HDMI X76289BOL05 2G SAM 128M16 Security Classification Compal Secret Data Compal Electronics, Inc.
4319BOBOL06/L26 N12PGS 2GN3G HDMI X76289BOL06 2G HYN 128M16 Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title
4319BOBOL07/L27 N12PGV 512W3G HDMI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
4319BOBOL08/L28 N12PGV 512N3G HDMI AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-7221P
Date: Wednesday, February 16, 2011 Sheet 3 of 59
A B C D E
5 4 3 2 1




D D
PEG_ICOMPI and RCOMPO signals should
be shorted and routed
with - max length = 500 mils - typical
+1.05VS_VCCP impedance = 43 mohms
PEG_ICOMPO signals should be routed with -




1
max length = 500 mils
R1
24.9_0402_1%
- typical impedance = 14.5 mohms
JCPU1A




2
J22 PEG_COMP
PEG_ICOMPI
J21
PEG_ICOMPO
15 DMI_CRX_PTX_N0 B27 H22
DMI_RX#[0] PEG_RCOMPO
15 DMI_CRX_PTX_N1 B25 DMI_RX#[1]
15 DMI_CRX_PTX_N2 A25
DMI_RX#[2] PEG_GTX_C_HRX_N15
15 DMI_CRX_PTX_N3 B24 DMI_RX#[3] PEG_RX#[0] K33
M35 PEG_GTX_C_HRX_N14
PEG_RX#[1] PEG_GTX_C_HRX_N13
15 DMI_CRX_PTX_P0 B28 L34
DMI_RX[0] PEG_RX#[2] PEG_GTX_C_HRX_N12
15 DMI_CRX_PTX_P1 B26 J35
DMI_RX[1] PEG_RX#[3] PEG_GTX_C_HRX_N11
15 DMI_CRX_PTX_P2 A24 J32




DMI
DMI_RX[2] PEG_RX#[4] PEG_GTX_C_HRX_N10
15 DMI_CRX_PTX_P3 B23 DMI_RX[3] PEG_RX#[5] H34
H31 PEG_GTX_C_HRX_N9
PEG_RX#[6] PEG_GTX_C_HRX_N8
15 DMI_CTX_PRX_N0 G21 DMI_TX#[0] PEG_RX#[7] G33
E22 G30 PEG_GTX_C_HRX_N7
15 DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8] PEG_GTX_C_HRX_N6
15 DMI_CTX_PRX_N2 F21 F35
DMI_TX#[2] PEG_RX#[9] PEG_GTX_C_HRX_N5
15 DMI_CTX_PRX_N3 D21 DMI_TX#[3] PEG_RX#[10] E34 PEG_GTX_C_HRX_N[0..15] 22
E32 PEG_GTX_C_HRX_N4
PEG_RX#[11] PEG_GTX_C_HRX_N3 PEG_GTX_C_HRX_P[0..15] 22
15 DMI_CTX_PRX_P0 G22 D33
DMI_TX[0] PEG_RX#[12] PEG_GTX_C_HRX_N2
15 DMI_CTX_PRX_P1 D22 D31 PEG_HTX_C_GRX_N[0..15] 22
C DMI_TX[1] PEG_RX#[13] PEG_GTX_C_HRX_N1 C
15 DMI_CTX_PRX_P2 F20 DMI_TX[2] PEG_RX#[14] B33 PEG_HTX_C_GRX_P[0..15] 22




PCI EXPRESS* - GRAPHICS
C21 C32 PEG_GTX_C_HRX_N0
15 DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15]
J33 PEG_GTX_C_HRX_P15
PEG_RX[0] PEG_GTX_C_HRX_P14
PEG_RX[1] L35
K34 PEG_GTX_C_HRX_P13
PEG_RX[2] PEG_GTX_C_HRX_P12
15 FDI_CTX_PRX_N0 A21 FDI0_TX#[0] PEG_RX[3] H35
H19 H32 PEG_GTX_C_HRX_P11
15 FDI_CTX_PRX_N1 FDI0_TX#[1] PEG_RX[4] PEG_GTX_C_HRX_P10
15 FDI_CTX_PRX_N2 E19 FDI0_TX#[2] PEG_RX[5] G34
F18 G31 PEG_GTX_C_HRX_P9
15 FDI_CTX_PRX_N3 FDI0_TX#[3] PEG_RX[6]




Intel(R) FDI
B21 F33 PEG_GTX_C_HRX_P8
15 FDI_CTX_PRX_N4 FDI1_TX#[0] PEG_RX[7]
C20 F30 PEG_GTX_C_HRX_P7
15 FDI_CTX_PRX_N5 FDI1_TX#[1] PEG_RX[8]
D18 E35 PEG_GTX_C_HRX_P6
15 FDI_CTX_PRX_N6 FDI1_TX#[2] PEG_RX[9] PEG_GTX_C_HRX_P5
15 FDI_CTX_PRX_N7 E17 E33
FDI1_TX#[3] PEG_RX[10] PEG_GTX_C_HRX_P4
F32
PEG_RX[11] PEG_GTX_C_HRX_P3
D34
PEG_RX[12] PEG_GTX_C_HRX_P2
15 FDI_CTX_PRX_P0 A22 E31
FDI0_TX[0] PEG_RX[13] PEG_GTX_C_HRX_P1
15 FDI_CTX_PRX_P1 G19 C33
FDI0_TX[1] PEG_RX[14] PEG_GTX_C_HRX_P0
15 FDI_CTX_PRX_P2 E20 B32
FDI0_TX[2] PEG_RX[15]
15 FDI_CTX_PRX_P3 G18 FDI0_TX[3]
B20 M29 PEG_HTX_GRX_N15 C1 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N15
15 FDI_CTX_PRX_P4 FDI1_TX[0] PEG_TX#[0]
C19 M32 PEG_HTX_GRX_N14 C2 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N14
15 FDI_CTX_PRX_P5 FDI1_TX[1] PEG_TX#[1] PEG_HTX_GRX_N13 PEG_HTX_C_GRX_N13
D19 M31 C3 1 2 OPT@ 0.1U_0402_10V7K
15 FDI_CTX_PRX_P6 FDI1_TX[2] PEG_TX#[2]
F17 L32 PEG_HTX_GRX_N12 C4 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N12
15 FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3] PEG_HTX_GRX_N11 PEG_HTX_C_GRX_N11
L29 C5 1 2 OPT@ 0.1U_0402_10V7K
+1.05VS_VCCP PEG_TX#[4] PEG_HTX_GRX_N10 C6 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N10
15 FDI_FSYNC0 J18 K31 1 2
FDI0_FSYNC PEG_TX#[5] PEG_HTX_GRX_N9 C7 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N9
15 FDI_FSYNC1 J17 FDI1_FSYNC PEG_TX#[6] K28 1 2
J30 PEG_HTX_GRX_N8 C8 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N8
PEG_TX#[7] PEG_HTX_GRX_N7 C9 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N7
15 FDI_INT H20 J28 1 2
FDI_INT PEG_TX#[8] PEG_HTX_GRX_N6 PEG_HTX_C_GRX_N6
eDP_COMPIO and ICOMPO signals PEG_TX#[9]
H29 C10 1 2 OPT@ 0.1U_0402_10V7K
1




J19 G27 PEG_HTX_GRX_N5 C11 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N5
should be shorted near balls R2
15 FDI_LSYNC0
H17
FDI0_LSYNC PEG_TX#[10]
E29 PEG_HTX_GRX_N4 C12 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N4
15 FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11]
B and routed with typical 24.9_0402_1% F27 PEG_HTX_GRX_N3 C13 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N3 B
PEG_TX#[12] PEG_HTX_GRX_N2 C14 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N2
impedance <25 mohms PEG_TX#[13] D28 1 2
F26 PEG_HTX_GRX_N1 C15 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N1
2




PEG_TX#[14] PEG_HTX_GRX_N0 C16 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N0
PEG_TX#[15] E25 1 2
A18
EDP_COMP eDP_COMPIO PEG_HTX_GRX_P15 C17 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_P15
A17 M28 1 2
eDP_ICOMPO PEG_TX[0] PEG_HTX_GRX_P14 C18 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_P14
31 EDP_HPD# B16 M33 1 2
eDP_HPD PEG_TX[1] PEG_HTX_GRX_P13 C19 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_P13
M30 1 2
PEG_TX[2] PEG_HTX_GRX_P12 C20 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_P12
L31 1 2
PEG_TX[3] PEG_HTX_GRX_P11 C21 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_P11
31 EDP_AUXP C15 eDP_AUX PEG_TX[4] L28 1 2
D15 K30 PEG_HTX_GRX_P10 C22 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_P10
31 EDP_AUXN eDP_AUX# PEG_TX[5]
K27 PEG_HTX_GRX_P9 C23 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_P9
eDP




PEG_TX[6] PEG_HTX_GRX_P8 C24 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_P8
PEG_TX[7] J29 1 2